Commit graph

581 commits

Author SHA1 Message Date
Álvaro Fernández Rojas
0c9152d320 mips: bmips: bcm63268: fix brcm, bcm6328-mc size
Shrink brcm,bcm6328-mc size to avoid overlapping with other controllers

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-12 13:20:03 +02:00
Álvaro Fernández Rojas
44d8514f54 mips: bmips: bcm6328: fix brcm, bcm6328-mc size
Shrink brcm,bcm6328-mc size to avoid overlapping with other controllers

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-12 13:20:03 +02:00
Álvaro Fernández Rojas
4153e47767 mips: bmips: bcm6358: fix brcm, bcm6358-mc size
Shrink brcm,bcm6358-mc size to avoid overlapping with other controllers

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-12 13:20:03 +02:00
Álvaro Fernández Rojas
a1b5e5e7c1 mips: bmips: add bcm6328-power-domain driver support for BCM63268
This driver can control up to 32 power domains.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
9a5cb22fda mips: bmips: add bcm6328-power-domain driver support for BCM6328
This driver can control up to 32 power domains.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
02bb1fa09e mips: bmips: add bcm6345-rst driver support for BCM63268
This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
78118211fb mips: bmips: add bcm6345-rst driver support for BCM6328
This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
efe8b9d012 mips: bmips: add bcm6345-rst driver support for BCM6358
This driver can control up to 32 resets.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
969ebdb930 mips: bmips: add bcm6345-clk driver support for BCM63268
This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
5b14e13c24 mips: bmips: add bcm6345-clk driver support for BCM6328
This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
70789bd2a5 mips: bmips: add bcm6345-clk driver support for BCM6358
This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
a186d2630b mips: bmips: add NeufBox 4 (Sercomm) board
This serves as an example for bcm6358-leds.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
4d6a519c68 mips: bmips: add bcm6358-led driver support for BCM6358
This driver can control up to 32 serial leds.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
09e2a57150 mips: bmips: add Comtrend VR-3032u bcm6328-leds
This board has several LEDs attached to its BCM6328 led controller.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
6def1b24d5 mips: bmips: add Comtrend AR-5387un bcm6328-leds
This board has several LEDs attached to its BCM6328 led controller.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
65a7c955fa mips: bmips: add bcm6328-led driver support for BCM63268
This driver can control up to 24 LEDs and supports HW blinking and serial leds.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
e0f1fd2b37 mips: bmips: add bcm6328-led driver support for BCM6328
This driver can control up to 24 LEDs and supports HW blinking and serial leds.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
2791f8db5e mips: bmips: add Huawei HG556a gpio-leds
This board has several LEDs attached to gpio0.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
c9c94d5d7e mips: bmips: add bcm6345-gpio driver support for BCM63268
This SoC has one gpio bank divided into two 32 bit registers, with a total of
52 GPIOs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
320186f476 mips: bmips: add bcm6345-gpio driver support for BCM6328
This SoC has one gpio bank with a total of 32 GPIOs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
2507f69c41 mips: bmips: add bcm6345-gpio driver support for BCM6358
This SoC has one gpio bank divided into two 32 bit registers, with a total of
40 GPIOs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
77ca99d1a0 MIPS: add BMIPS Comtrend VR-3032u board
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
6a235bb87b MIPS: add support for Broadcom MIPS BCM63268 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
0642f485dc MIPS: add BMIPS Comtrend AR-5387un board
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
6471a225e7 MIPS: add support for Broadcom MIPS BCM6328 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
4a2b2724a2 MIPS: add BMIPS Huawei HG556a board
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
e30d2bd40e MIPS: add support for Broadcom MIPS BCM6358 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
ee422142f4 MIPS: add initial infrastructure for Broadcom MIPS SoCs
CFE checks CPU Thread in a different way (using register $22):
mfc0	t1, C0_BCM_CONFIG, 3 # $22
li	t2, CP0_CMT_TPID # (1 << 31)
and	t1, t2
bnez	t1, 2f	# if we are running on thread 1, skip init
nop

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
5e36546c53 MIPS: allow using generic sysreset drivers
Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Daniel Schwierzeck
0d159d6852 MIPS: call debug_uart_init right before board_init_f
All MIPS boards that support debug uart are calling debug_uart_init right at
the beginning of board_early_init_f.
Instead of doing that, let's provide a generic call to debug_uart_init right
before the call to board_init_f if debug uart is enabled for boards without
stack in SRAM.
On the other hand, boards with stack in SRAM can call earlier (right before
low level init).

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10 16:16:09 +02:00
Álvaro Fernández Rojas
47cf465c25 MIPS: add support for generating u-boot.elf
Define PLATFORM_ELFFLAGS for MIPS in order to be able to generate u-boot.elf

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10 16:16:09 +02:00
Simon Glass
f1683aa73c board_f: Rename initdram() to dram_init()
This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-13 09:40:57 -04:00
Simon Glass
088454cde2 board_f: Drop return value from initdram()
At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05 13:59:20 -04:00
Simon Glass
52c411805c board_f: Drop board_type parameter from initdram()
It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-05 13:58:44 -04:00
Tom Rini
86f21c96f4 mips: Use common _AC macro now.
MIPS no longer needs to have its own version of this macro now.

Fixes: 2a6713b09b ("move UL() macro from armv8/mmu.h into common.h")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-10 08:19:26 -05:00
Masahiro Yamada
63c0941726 libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY
Commit e2f88dfd2d ("libfdt: Introduce new ARCH_FIXUP_FDT option")
allows us to skip memory setup of DTB, but a problem for ARM is that
spin_table_update_dt() and psci_update_dt() are skipped as well if
CONFIG_ARCH_FIXUP_FDT is disabled.

This commit allows us to skip only fdt_fixup_memory_banks() instead
of the whole of arch_fixup_fdt().  It will be useful when we want to
use a memory node from a kernel DTB as is, but need some fixups for
Spin-Table/PSCI.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for x86:
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-02 20:54:34 -07:00
Paul Burton
6fd596a1aa MIPS: Fix map_physmem for cached mappings
map_physmem should return a pointer that can be used by the CPU to
access the given memory - on MIPS simply returning the physical address
as it does prior to this patch doesn't achieve that. Instead return a
pointer to the memory within (c)kseg0, which matches up consistently
with the (c)kseg1 pointer that uncached mappings return via ioremap.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30 16:18:19 +01:00
Paul Burton
7a3e0f74a7 MIPS: Use ram_top, not bi_memsize, in arch_lmb_reserve
When calculating the region to reserve for the stack in
arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to
CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough
memory to reach the end of the address space.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30 16:15:51 +01:00
Marek Vasut
e7e0469c88 mips: Let cache.h be included from assembly source
Add ifdef __ASSEMBLY__ around the function prototype to let cache.h
be included from assembly code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2016-11-30 16:13:17 +01:00
Daniel Schwierzeck
6c59363004 MIPS: add handling for generic and EJTAG exceptions
Add exception handlers for generic and EJTAG exceptions. Most of
the assembly code is imported from Linux kernel and adapted to U-Boot.
The exception vector table will be reserved above the stack before
U-Boot is relocated. The exception handlers will be installed and
activated after relocation in the initr_traps hook function.

Generic exceptions are handled by showing a CPU register dump similar
to Linux kernel. For example:

malta # md 1
00000001:
Ooops:
$ 0   : 00000000 00000000 00000009 00000004
$ 4   : 8ff7e108 00000000 0000003a 00000000
$ 8   : 00000008 00000001 8ff7cd18 00000004
$12   : 00000002 00000000 00000005 0000003a
$16   : 00000004 00000040 00000001 00000001
$20   : 00000000 8fff53c0 00000008 00000004
$24   : ffffffff 8ffdea44
$28   : 90001650 8ff7cd00 00000004 8ffe6818
Hi    : 00000000
Lo    : 00000004
epc   : 8ffe6848 (text bfc28848)
ra    : 8ffe6818 (text bfc28818)
Status: 00000006
Cause : 00000410 (ExcCode 04)
BadVA : 8ff9e928
PrId  : 00019300
 ### ERROR ### Please RESET the board ###

EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler
if necessary. Otherwise the debug mode will simply be exited. The SDBBP
handler currently prints the contents of registers c0_depc and c0_debug.
This could be extended in the future to handle semi-hosting according to
the MIPS UHI specification.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Tested-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30 16:12:17 +01:00
Daniel Schwierzeck
bd60252811 MIPS: reserve space for exception vectors
In order to set own exception handlers, a table with the exception
vectors must be built in DRAM and the CPU EBase register must be
set to the base address of this table.

Reserve the space above the stack and use gd->irq_sp as storage
for the exception base address.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:11:46 +01:00
Daniel Schwierzeck
67588bdade MIPS: add asm-offsets for struct pt_regs
Import asm-offsets.c from kernel to generate offset for struct pt_regs
needed by exception handlers.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:11:46 +01:00
Daniel Schwierzeck
924ad86638 MIPS: add possibility to setup initial stack and global data in SRAM
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together with
CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be
set up in that SRAM. This can be used to provide a C environment
also for lowlevel_init().

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:11:46 +01:00
Daniel Schwierzeck
c3e72ab801 MIPS: factor out code for initial stack and global data
Move the code for setting up the initial stack and global data
to a macro to be able to use it more than once.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:11:46 +01:00
Daniel Schwierzeck
65d297af7c MIPS: fix iand optimize setup of CP0 registers
Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.

Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.

Initialize cp0 count as early as possible to get the most
accurate boot timing.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:11:46 +01:00
Daniel Schwierzeck
345490fcd6 MIPS: fix ROM exception vectors
When booting from ROM, early exceptions can't be handled
properly. Instead of busy-looping give the developer the
possibilty to examine the situation. Invoke an UHI
exception operation which can be read as unhandled exception
by a hardware debugger if one is attached. If the debugger
doesn't support UHI, the exception is read as unexpected
breakpoint.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:11:39 +01:00
Daniel Schwierzeck
af3971f81a MIPS: make inclusion of ROM exception vectors configurable
This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot entry point is equal to the CPU reset exception
vector address. For instance this is the case when U-Boot is
used as ROM in Qemu or booted from parallel NOR flash. When
U-Boot is booted from RAM (e.g. loaded there by SPL), the
exception vectors need to be setup dynamically, which is done
in follow-up commits.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:07:17 +01:00
Vagrant Cascadian
3450a8596d Fix spelling of "resetting".
Cover-Letter: Fixes several spelling errors for the words "resetting",
  "extended", "occur", and "multiple".

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-31 10:13:17 -04:00
Simon Glass
a0b49bc334 efi: Use asmlinkage for EFIAPI
This is required for x86 and is also correct for ARM (since it is empty).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-10-19 09:01:53 +02:00
Masahiro Yamada
4491327d59 Remove arch/${ARCH}/include/asm/errno.h
Unlike Linux, nothing about errno.h is arch-specific in U-Boot.
As you see, all of arch/${ARCH}/include/asm/errno.h is just a
wrapper of <asm-generic/errno.h>.  Actually, U-Boot does not
export headers to user-space, so we just have to care about the
consistency in the U-Boot tree.

Now all of include directives for <asm/errno.h> are gone.
Deprecate <asm/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-09-23 17:56:18 -04:00
Masahiro Yamada
1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Paul Burton
31d36f748c MIPS: Hang if run on a secondary CPU
Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.

Prevent this from happening by simply hanging with an infinite loop if
we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum
as appropriate, is non-zero.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 17:04:53 +02:00
Paul Burton
d263cda5ae MIPS: Fix cache maintenance in relocate_code & simplify
The relocate_code function was handling cache maintenance incorrectly.
It copied U-Boot to its new location, flushed the caches & then
proceeded to apply relocations & jump to the new code without flushing
the caches again. This is problematic as the instruction cache could
potentially have already fetched instructions that hadn't had relocs
applied.

Rework this to perform the flush_cache call using the code in the
original copy of U-Boot, after having applied relocations to the new
copy of U-Boot. The new U-Boot can then be jumped to safely once that
cache flush has been performed.

As part of this, since the old U-Boot is used up until after that cache
flush, complexity around loading values from the GOT using a jump & link
instruction & loads from a table is removed. Instead we can simply load
the needed values with PTR_LA fromt the original GOT.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 16:25:43 +02:00
Paul Burton
ad8783cb1c boston: Introduce support for the MIPS Boston development board
This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older MIPS Malta board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 16:24:36 +02:00
Paul Burton
639200f6a0 MIPS: Ensure cache ops complete in mips_cache_reset
Ensure that cache operations complete before returning from
mips_cache_reset by placing a completion barrier (sync instruction)
before the return. Without this there is no guarantee that the cache ops
will complete before any subsequent memory accesses, since they are
indexed cache ops & thus not implicitly ordered with memory accesses.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
d608254b0a MIPS: Clear hazard between TagLo writes & cache ops
Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
c5b8412d60 MIPS: Ensure Config.K0=2 applies before any memory accesses
During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
initialised. This write to the Config register introduces an execution
hazard between it & any following memory accesses (such as the load of
_gp), which we need to clear in order to ensure those memory accesses
are actually performed uncached. Clear this execution hazard with the
insertion of an ehb execution hazard barrier instruction.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
566ce04de4 MIPS: Malta: Enable CM & L2 support
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
7953354b07 MIPS: Join the coherent domain when a CM is present
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
4baa0ab67d MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.

If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
b2b135d980 MIPS: Map CM Global Control Registers
Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
5c72e5a62e MIPS: Define register names for cache init
Define names for registers holding cache sizes throughout
mips_cache_reset, in order to make the code easier to read & allow for
changing register assignments more easily.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
f8981277f5 MIPS: If we don't need DDR for cache init, init cache first
On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
4f9226b403 MIPS: Preserve Config implementation-defined bits
The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
33b5c9b209 MIPS: Enable use of the instruction cache earlier
Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
8cb4817d0f MIPS: Probe cache line sizes once during boot
Rather than probing the cache line sizes on every call of any cache
maintenance function, probe them once during boot & store the values in
the global data structure for later use. This will reduce the overhead
of the cache maintenance functions, which isn't a big deal yet but
becomes more important once L2 caches which may expose their properties
via coprocessor 2 or the CM are supported.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
0dfe04d6c8 MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init
In order to prepare for MIPS arch code making use of arch_cpu_init in a
later patch, stop using it from ath79 SoC code & instead use the new
mach_cpu_init which is provided for this purpose.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Zubair Lutfullah Kakakhel
ebf2b9e3df mips: Add MIPSfpga platform support
MIPSfpga is an FPGA based dev platform.

In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks

The FPGA dev board used is the Nexys4DDR board by Digilent.

For more information, check the Readme file in board/imgtec/xilfpga

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-21 14:55:14 +02:00
Zubair Lutfullah Kakakhel
d4e85377e7 mips: xilfpga: Add device tree files
Mostly the same as the Kernel upstream device tree file except for

- alias for the serial console node
- ethernet node as the ethernet stuff isn't upstream on kernel.org yet
- uart clock-frequency passed directly in the node

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-21 14:55:14 +02:00
Joe Hershberger
5a49f17481 net: mii: Use spatch to update miiphy_register
Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-15 15:26:33 -05:00
Michal Simek
e2f88dfd2d libfdt: Introduce new ARCH_FIXUP_FDT option
Add new Kconfig option to disable arch_fixup_fdt() calls for cases where
U-Boot shouldn't update memory setup in DTB file.
One example of usage of this option is to boot OS with different memory
setup than U-Boot use.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-31 19:37:08 -06:00
Stephen Warren
135aa95002 clk: convert API to match reset/mailbox style
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
  provider now implements a single set of clocks. This provides a simpler
  conceptual interface to clients, and better aligns with device tree
  clock bindings.
* Clocks are now identified with a single "struct clk", rather than
  requiring clients to store the clock provider device and clock identity
  values separately. For simple clock consumers, this isolates clients
  from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
  clk-uclass.h contains the provider API. This aligns with the recently
  added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
  can customize these operations if needed. This also aligns with the
  recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
  clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst
others).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-06-19 17:05:55 -06:00
Paul Burton
4b7b0a0f06 MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex
For consistency with the other cache-related Kconfig entries & the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 372286217f ("MIPS: Split I & D cache line size config")
2016-06-10 12:27:37 +02:00
Paul Burton
a95800e881 MIPS: Fix invalidate_dcache_range to operate on L1 Dcache
Commit fb64cda579 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: fb64cda579 ("MIPS: Abstract cache op loops with a macro")
2016-06-10 12:27:29 +02:00
Wills Wang
ca09e66b04 mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define
Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-31 10:17:54 +02:00
Wills Wang
cdeb68e292 mips: ath79: Add support for ungating USB and ethernet on qca953x
Add code to ungate USB and ethernet controller on qca953x

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-31 10:17:54 +02:00
Wills Wang
04583c686e mips: ath79: ap121: Enable ethernet
This patch enable network function for ap121 board.

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-05-31 10:17:54 +02:00
Wills Wang
375239174c mips: ath79: Rename get_bootstrap into ath79_get_bootstrap
Add a platform prefix for function name in order to make more readable,
and move it into ath79.h

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-05-31 10:17:54 +02:00
Paul Burton
fb64cda579 MIPS: Abstract cache op loops with a macro
The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code & will allow for not adding
further duplication when introducing L2 cache support.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:44:24 +02:00
Paul Burton
372286217f MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:44:24 +02:00
Paul Burton
ace3be4f15 MIPS: Move cache sizes to Kconfig
Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:44:24 +02:00
Daniel Schwierzeck
83b0face8c MIPS: remove dead code from asm/u-boot-mips.h
Those wrappers for linker symbols were once used in the MIPS
specific board.c implementation. Since the migration to generic
board.c, those wrappers are dead code and can be removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:38:11 +02:00
Daniel Schwierzeck
5f9cc363ed MIPS: add tune for MIPS 34kc
Add tune Kconfig option for MIPS 34kc.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:38:11 +02:00
Daniel Schwierzeck
07f5b966aa MIPS: provide a default u-boot-spl.lds
Provide a default linker script for SPL binaries. Start address
and size of text section and BSS section are configurable. All
sections are arranged in a way that only relevant sections are
kept in the code section for maximum size reduction. All other
sections are kept but moved outside the code section to help
with debugging.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-05-31 09:38:11 +02:00
Paul Burton
0f832b9cdc malta: Allow MIPS64 builds
Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:38:11 +02:00
Paul Burton
2e4cc1c5d4 MIPS: Use CPHYSADDR to implement mips32 virt_to_phys
Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.

This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:

    https://patchwork.linux-mips.org/patch/12564/

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:38:11 +02:00
Simon Glass
3e085c9946 mips: Drop unused code in u-boot.h
Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-27 15:39:53 -04:00
Wills Wang
4349b55b99 mips: ath79: ar933x: Avoid warning with gcc5
GCC 5.3 report a warning: 'upper' and 'lower' may be used
uninitialized in this function [-Wmaybe-uninitialized].
Compiler might need explicit initializer.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-26 01:34:14 +02:00
Wills Wang
42a3f3e6eb mips: ath79: ar933x: Fix ethernet PHY mismatch
We need reset the Ethernet Switch analog part before operation,
or the build-in Ethernet PHY don't work.

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-05-26 01:34:14 +02:00
Marek Vasut
1ad3a6fb5b mips: Drop JZ4740 remnants
Remove the remnants of JZ4740 support.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2016-05-26 01:34:14 +02:00
Marek Vasut
ecc9d26062 mips: Allow overriding start.S in SPL
Certain chips, like the JZ47xx, have extreme size constraints on the
SPL size and require custom start.S . Allow overriding the start.S
the same way ARM MXS does it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2016-05-26 01:34:14 +02:00
Paul Burton
6242aa1374 malta: Use device model & tree for UART
Make use of device model & device tree to probe the UART driver. This is
the initial step in bringing Malta up to date with driver model, and
allows for cleaner handling of the different I/O addresses for different
system controllers by specifying the ISA bus address instead of a
translated memory address.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-26 01:34:13 +02:00
Paul Burton
40ba13c986 malta: Support MIPS32r6 configurations
Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6
CPUs. Allow building U-Boot for such systems by selecting
CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-21 01:36:39 +02:00
Paul Burton
c52ebea1cc MIPS: Support for targetting MIPSr6
Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way
that we currently select release 1 or release 2 targets. MIPSr6 is not
entirely backwards compatible with earlier releases of the architecture.
Some instructions are encoded differently, some are removed, some are
reused, so it is not practical to run U-Boot built for earlier revisions
on a MIPSr6 system. Update their Kconfig help text to reflect that.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-21 01:36:39 +02:00
Paul Burton
20286cdff7 MIPS: Simplify CONFIG_SYS_CPU values
Rather than having the values for CONFIG_SYS_CPU depend upon each
architecture revision, have them depend upon the more general
CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the
architecture revisions.

This is done in preparation for adding MIPSr6 support, which would
otherwise need to introduce new cases here.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-21 01:36:39 +02:00
Paul Burton
9f8ac82452 MIPS: Use unchecked immediate addition/subtraction
In MIPS assembly there have historically been 2 variants of immediate
addition - the standard "addi" which traps if an overflow occurs, and
the unchecked "addiu" which does not trap on overflow. In release 6 of
the MIPS architecture the trapping variants of immediate addition &
subtraction have been removed. In preparation for supporting MIPSr6,
stop using the trapping instructions from assembly & switch to their
unchecked variants.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-21 01:36:39 +02:00
Marek Vasut
400df30998 mips: ath79: Add support for TPLink WDR4300
Add support for the TPLink WDR4300 router, which is based on the
AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported
on this system as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:39 +02:00
Marek Vasut
e08539b791 mips: ath79: Add AR934x support
Add support for the Atheros AR934x WiSoCs. This patchs adds complete
system init, including PLL and DRAM init, both of which happen from
full C environment, since the AR934x has proper SRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:39 +02:00
Marek Vasut
4771bbee5d mips: ath79: Add support for ungating ethernet on ar933x and ar934x
Add code to ungate the ethernet controller on ar933x and ar934x .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
2986a9d4bd mips: ath79: dts: Add ethernet MAC nodes for ar933x
Add node for both ethernet controllers in the ar933x.
The PHY is attached only to the first ethernet controller.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
6b699742d4 mips: ath79: Add support for ungating USB on ar933x and ar934x
Add code to ungate the USB controller on ar933x and ar934x .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
c31558780b mips: ath79: dts: Add generic-ehci node
Add generic EHCI node for the ChipIdea EHCI controller in the ath79.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
43a092ffdd mips: ath79: Fix compiler warning on const assignment
The assignment const T var; var = value; is illegal, since var is
constant. Drop the const to fix the compiler warning.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
0a6767efab mips: ath79: Fix ar71xx_regs.h indent
The indent in this file triggers my OCD, so fix it. Replace multiple
spaces with tabs and align the values in one column.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
0a0a958b68 mips: Add MIPS 74Kc tune
Add MIPS 74Kc tune Kconfig option.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
[added missing tune-y entry in arch/mips/Makefile]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
5760fc7850 mips: Fix compiler warning in cpu.c
There really is zero reason for including netdev.h in generic mips CPU code.
Removing the netdev.h from cpu.c also fixes the following compiler warning:

In file included from arch/mips/cpu/cpu.c:10:0:
include/netdev.h:204:41: warning: 'struct eth_device' declared inside parameter list [enabled by default]
 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
                                         ^
include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:36:38 +02:00
Wills Wang
59e4080c7e ath79: add readonly attribute for ath79_soc_desc
use 'const' keywork to qualify readonly attribute for lookup-table member

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Wills Wang
5691d10a01 ath79: ar933x: use BIT macro for bit shift operation
used a uniform BIT macro for register bit-field shift

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Wills Wang
a2277cc30c mips: ath79: add AP143 reference board
This patch add board-level code and base DT for AP143.

Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:25:50 +02:00
Wills Wang
6a7b52bc8d mips: ath79: add AP121 reference board
This patch add board-level code and base DT for AP121.

Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:25:50 +02:00
Wills Wang
9b03f802ae mips: ath79: add support for QCA953x SOCs
This patch enable work for qca953x SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:25:50 +02:00
Wills Wang
ee7bb5be35 mips: ath79: add support for AR933x SOCs
This patch enable work for ar933x SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:25:50 +02:00
Wills Wang
1d3d0f1f1c mips: add base support for QCA/Atheros ath79 SOCs
This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:25:50 +02:00
Robert P. J. Day
1cc0a9f496 Fix various typos, scattered over the code.
Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
2016-05-05 21:39:26 -04:00
Purna Chandra Mandal
fdff5b0598 MIPS: bootm: Add fixup of '/memory' node.
MIPS arch do not update 'reg' property of /memory node.
As a result Linux bootup will not work unless board.dts
file contains right /memory offset-size information or
board implements required memory fixup.
Fixing by renaming (unused) _arch_fixup_memory_node_ to
_arch_fixup_fdt_ in arch/mips/lib/bootm.c inline with ARM arch.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-04-19 13:21:48 +02:00
Purna Chandra Mandal
ac7eef716e board: pic32mzda: enable USB-host, USB-storage support.
Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-04-10 17:18:42 +02:00
Matthias Schiffer
499b847521 MIPS: fix mips_cache fallback without __builtin_mips_cache
The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.

Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-03-09 11:00:40 +01:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Purna Chandra Mandal
7d514a7407 board: Enable ethernet, tftpboot support to pic32mzdask board.
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01 22:14:02 +01:00
Purna Chandra Mandal
c76eb72c43 board: add SDHCI support for PIC32MZDASK board.
Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01 22:14:02 +01:00
Purna Chandra Mandal
44da3a176c board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
be961fa15b MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
Add Microchip PIC32MZ[DA] SoC family support.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
9ffa7a35ef drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
32c1a6eef8 MIPS: initial infrastructure for Microchip PIC32 architecture
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-01 22:14:00 +01:00
Paul Burton
05e342554e MIPS: Support dynamic I/O port base address
The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-02-01 22:13:25 +01:00
Paul Burton
8ac493cd65 MIPS: Remove SLOW_DOWN_IO
CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in
the SLOW_DOWN_IO macro. This is done in preparation for changes to
mips_io_port_base which can be avoided in this path by removing it
entirely.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-02-01 22:13:25 +01:00
Marek Vasut
fbb0de088b mips: cache: Bulletproof the code against cornercases
This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will do no operation, since the size is zero.

The current implementation though has a problem where such invocation will
result in a hard CPU hang. This is because under such conditions, where the
start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
will then try to iterate over the entire address space, which in itself is
wrong. But iterating over the entire address space might also hit some odd
address which will cause bus hang. The later happens on the Atheros MIPS.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
2016-02-01 22:13:24 +01:00
Daniel Schwierzeck
e26e8dc8f4 MIPS: start.S: fix and optimize instructions
Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as
32 Bit register. Use 64 Bit register access for clearing gd_data
and copying U-Boot.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:13:24 +01:00
Purna Chandra Mandal
a62790997f MIPS: initialize board_init_f() argument to zero.
Argument boot_flags of board_init_f() should be set to 0 as
$a0 may be utilized in lowlevel_init() or mips_cache_reset()
or previous stage boot-loader.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:13:24 +01:00
Tom Rini
d6ea6d8876 mips: asm/io.h: Add in <linux/bug.h>
As part of the bug.h / BUILD_BUG_* clean up, this file was missed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-25 18:52:23 -05:00
Daniel Schwierzeck
0e0efb40b8 MIPS: implement bit manipulating I/O accessors
Add support for functions clrbits_X(), setbits_X() and clrsetbits_X()
on MIPS.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
898582bdee MIPS: fix SPDX license identifier in remaining arch header files
Add a SPDX license identifier to MIPS header files where it is
still missing.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
a3ab2ae7f6 MIPS: sync processor and register definitions with linux-4.4
Update definitions for processor, registers as well as assemby
macros.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
23ff8633fd MIPS: sync I/O related header files with linux-4.4
Mainly sync asm/io.h to get a working ioremap() implementation
as well as the full set of I/O accessors. Pull in additional
header files to make this work.

Furthermore port over the directory 'arch/mips/include/asm/mach-generic/'
with contains default definitions for I/O and memory spaces and default
implementations for mapping those spaces. All files in that directory
can be overwritten by a SoC/machine.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
f53830e74e MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT
Add Kconfig symbol for L1 cache shift like the kernel does.
The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source
for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS.
If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the
cache sizes are automatically detected and ARCH_DMA_MINALIGN
would be set to 128 Bytes.

The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which
corresponds to 32 Bytes. All current MIPS boards already used
that value. While on it, fix the Malta board to use a value of 6
like the kernel port does.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
0315a28909 MIPS: Kconfig: optimize gcc -march and -mtune setup
Move setup of -march to arch/mips/Makefile and follow the design on ARM.
Also add a possibility to chose specific CPU tune options.

Signed-off-by: Wills Wang <wills.wang@live.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
76ada5f8b7 MIPS: au1x00: move SoC header files to arch/mips/mach-au1x00/include/mach/
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
6479b691d7 MIPS: Kconfig: refactor machine setup
Refactor machine setup like it is done on ARM. While on it,
also support "include <mach/file.h" for machine specific
header files.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
0fc13a9093 MIPS: add initial infrastructure for device-tree files
Prepare sub-folder for device-tree files. Make support for
device-tree on MIPS available in Kbuild/Kconfig.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-01-16 21:06:45 +01:00
Daniel Schwierzeck
e92d9124f8 MIPS: do not build position-independent executables for SPL
SPL binaries are usually linked to a fixed address in SRAM.
Furthermore SPL binaries do not need to relocate itself. Thus
do not build them as position-independent binaries which helps
to largely reduce the size of SPL binaries.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:45 +01:00
Daniel Schwierzeck
5b6f357fe7 MIPS: create .text sub-sections for assembler functions
Put all functions coded in assembly in sub-sections of
section .text. This allows the linker to garbage collect
unused assembly functions too.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:45 +01:00
Daniel Schwierzeck
113492988b MIPS: fix annotation of _start and relocate_code
Correctly annotate _start and relocate_code as functions to
produce more readable disassembly code generated by objdump.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:45 +01:00
Purna Chandra Mandal
1a96780016 MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.
With CONFIG_CMD_GPIO compilation reports error.
common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory
 #include <asm/gpio.h>
                      ^
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-16 21:06:45 +01:00
Ben Whitten
192bc6948b Fix GCC format-security errors and convert sprintfs.
With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.

Simple uses of sprintf are also converted to use strcpy.

Signed-off-by: Ben Whitten <ben.whitten@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 22:11:34 -05:00
Tom Rini
250ea267d8 Merge branch 'master' of git://git.denx.de/u-boot-mips 2015-11-06 09:17:17 -05:00
Daniel Schwierzeck
347ea94e2a MIPS: bootm: use CONFIG_IS_ENABLED() everywhere
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-06 13:27:28 +01:00
Daniel Schwierzeck
2bb5b63879 MIPS: bootm: rework and fix broken bootm code
The move to 'generic board' as well as changes in the generic
bootm code broke the boot of FIT uImage's. Especially uImage's
with additional initramfs images or FDT's do not work anymore.

Refactor the bootm code to work again with the generic bootm code.

Always relocate ramdisk and FDT in step 'bootm prep' because the
generic bootm code does this only for legacy uImage's.

Move the step 'bootm cmdline' to 'bootm prep' because the Linux
kernel parameters rd_start and rd_size have to be initialized after
the relocation of the ramdisk.

Furthermore support the step 'bootm fake'.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-06 13:27:28 +01:00
Fabio Estevam
b810aa1dd1 mips: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-11-05 10:52:26 -05:00
Govindraj Raja
4adcb2380c MIPS: fix syntax for fdt_chosen/initrd.
The syntax for the fdt_chosen/initrd
functions seem to deprecated in usage
from MIPS bootm implementation.

Third parameter is no more used in these api's
Refer to : include/fdt_support.h

Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
2015-08-21 15:22:41 +02:00
Chris Packham
73a4152b25 mips: Use unsigned int when reading c0 registers
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).

Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).

The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.

Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.

Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2015-08-21 15:22:41 +02:00
Daniel Schwierzeck
b11c5d1dc2 MIPS: change 'extern inline' to 'static inline'
The kernel changed it a long time ago. Also this is now broken
on gcc-5.x.

Reported-by: Andy Kennedy <andy.kennedy@adtran.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-07-02 11:29:33 +02:00
Tony Wu
49bbdae318 MIPS: fix missing semicolon in cacheops.h
Fix missing semicolon in cacheops.h introduced in commit
2b8bcc5a2 (MIPS: avoid .set ISA for cache operations)

Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2015-07-02 11:29:33 +02:00
Joe Hershberger
c9bb942e2f Move default y configs out of arch/board Kconfig
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.

Remove the configs that behave this way from the archs.

A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:

SPIFLASH
DISPLAY_BOARDINFO

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-06-25 22:17:55 -04:00
Joe Hershberger
a26cd04920 arch: Make board selection choices optional
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
2015-05-12 18:10:02 -04:00
Daniel Schwierzeck
90b1c9fad7 MIPS: implement device-tree handover to Linux kernel
Add device-tree handover to Linux kernel conforming with MIPS UHI [1].
Register $a0 will be set to the reserved value -2. The address of
the device-tree blob will be stored as KSEG0 address in $a1. $a2 and
$a3 are set to zero.

[1] http://prplfoundation.org/wiki/MIPS_documentation

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-04-24 12:15:34 +02:00
Joe Hershberger
1fd92db83d net: cosmetic: Fix var naming net <-> eth drivers
Update the naming convention used in the network stack functions and
variables that Ethernet drivers use to interact with it.

This cleans up the temporary hacks that were added to this interface
along with the DM support.

This patch has a few remaining checkpatch.pl failures that would be out
of the scope of this patch to fix (drivers that are in gross violation
of checkpatch.pl).

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:33 -06:00
Joe Hershberger
8b2c9a7157 net: Provide a function to get the current MAC address
The current implementation exposes the eth_device struct to code that
needs to access the MAC address.  Add a wrapper function for this to
abstract away the pointer for this operation.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:10 -06:00
Masahiro Yamada
0a12e6872e generic-board: move __HAVE_ARCH_GENERIC_BOARD to Kconfig
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-28 09:03:08 -04:00
Daniel Schwierzeck
eef88dfb3e MIPS: unify CPU code in arch/mips/cpu/
Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/.
The CPU specific config.mk files need to remain until
CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30 14:19:58 +01:00
Daniel Schwierzeck
d9a4a6223c MIPS: move au1x00 SoC code to arch/mips/mach-au1x00
Move all au1x00 code out of arch/mips/cpu/mips32 to allow
unification of CPU code in a later patch. The reorganization
of the SoC specific header files will be done in a later patch
series.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2015-01-30 14:19:58 +01:00
Paul Burton
f1c64a0810 MIPS: handle mips64 ST0_KX bit in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle setting the KX bit of the cop0 Status register when the
mips32 start.S is built for mips64.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30 14:19:58 +01:00
Paul Burton
ab0d002677 MIPS: handle mips64 relocs in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle mips64 relocations in the mips32 start.S when built for
mips64.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30 14:19:58 +01:00
Paul Burton
a39b1cb7f0 MIPS: use asm.h macros in mips32 start.S
Where the mips32 & mips64 implementations of start.S differ in terms of
access sizes & offsets, use the appropriate macros from asm.h to
abstract those differences away. This is in preparation for sharing a
single copy of start.S between mips32 & mips64.

The exception to this is loads of immediates to be written to the cop0
Config register, which is a 32bit register on mips64 and therefore
constants written to it can be loaded as such.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-30 14:19:57 +01:00
Paul Burton
ba21a453a5 malta: IDE support
This patch adds IDE support to the MIPS Malta board. The IDE controller
is enabled after probing the PCI bus and otherwise just makes use of
U-boot generic IDE support.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 13:11:02 +01:00
Paul Burton
8755d50706 MIPS: clear TagLo select 2 during cache init
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
Paul Burton
dd7c72006e MIPS: allow systems to skip loads during cache init
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
Paul Burton
ca4e833cd6 MIPS: inline mips_init_[id]cache functions
The mips_init_[id]cache functions are small & only called once from a
single callsite. Inlining them allows mips_cache_reset to avoid having
to bother moving arguments around & leaves it a leaf function which is
thus able to simply keep the return address live in the ra register
throughout, simplifying the code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
Paul Burton
ac22feca11 MIPS: refactor cache loops to a macro
Reduce duplication by performing loops through cache tags using an
assembler macro.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
Paul Burton
536cb7ce1a MIPS: refactor L1 cache config reads to a macro
Reduce duplication between reading the configuration of the L1 dcache &
icache by performing both using a macro which calculates the appropriate
line & cache sizes from the coprocessor 0 Config1 register.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
Paul Burton
4a5d8898bc MIPS: unify cache initialization code
The mips32 & mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in
order to reduce duplication. The temporary registers used are shuffled
slightly in order to work for both mips32 & mips64 builds. The RA
register is defined differently to suit mips32 & mips64, but will be
removed by a later commit in the series after further cleanup.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:01 +01:00
Paul Burton
30374f98d1 MIPS: unify cache maintenance functions
Move the more developed mips32 version of the cache maintenance
functions to a common arch/mips/lib/cache.c, in order to reduce
duplication between mips32 & mips64.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:00 +01:00
Paul Burton
2b8bcc5a2f MIPS: avoid .set ISA for cache operations
As a step towards unifying the cache maintenance code for mips32 &
mips64 CPUs, stop using ".set <ISA>" directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When not present, simply don't
bother with the .set directives since U-boot always builds with
-march=mips32 or higher anyway.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 12:55:00 +01:00
Daniel Schwierzeck
e520023882 MIPS: add support for pre-relocation malloc
Implement MIPS specific setup of the gd_t structure to support
pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified,
a memory area will be reserved after the initial stack area and
the gd->malloc_base pointer will be initialized.

After this patch the new driver model can be used on MIPS.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:07:23 +01:00
Daniel Schwierzeck
dd82128ef5 MIPS: add support for CONFIG_SYS_INIT_SP_ADDR
Support the existing config option CONFIG_SYS_INIT_SP_ADDR on
MIPS. This allows to move the initial stack to other places
than the beginning of RAM.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:07:16 +01:00
Daniel Schwierzeck
9d638eeab7 MIPS: add Kconfig option for CONFIG_SWAP_IO_SPACE
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:06:51 +01:00
Daniel Schwierzeck
c57dafb5b4 MIPS: replace $(CPU) with Kconfig symbols
Conditionally set head-y and lib-y with boolean Kconfig symbols
for selected CPU. This deprecates the usage of the $(CPU) variable.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:06:04 +01:00
Thomas Langer
a18a477147 MIPS: use common code from lib/time.c
The common code just needs the C0_COUNT as free running counter,
without the need of writing and checking C0_COMPARE.

The function get_tbclk() is still implemented here instead of changing
all places of CONFIG_SYS_MIPS_TIMER_FREQ to CONFIG_SYS_TIMER_RATE.

The change was tested on a MIPS32 system, but as the MIPS64 code
was/is the same, this should be no problem.

Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
2015-01-21 14:02:49 +01:00
Daniel Schwierzeck
e13a50b34b MIPS: bootm: add bootstage reporting
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:02:49 +01:00
Daniel Schwierzeck
5002d8cc54 MIPS: bootm: prepare a flattened device tree for the kernel
Add the initial code to prepare a flattened device tree for
the kernel like relocating the FDT blob and fixing up the
/chosen and /memory nodes.

The final hand over to the kernel is not yet implemented. After
the community agreed on the MIPS boot interface for device trees,
the corresponding code will be added.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:02:49 +01:00
Daniel Schwierzeck
8cec725ad5 MIPS: bootm: add mem, rd_start and rd_size to kernel command line
If the user wants to boot a kernel without legacy environment,
information like memory size, initrd address and size should be
handed over to the kernel in the command line.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:02:48 +01:00
Daniel Schwierzeck
ca65e5851f MIPS: bootm: refactor preparation of Linux kernel environment
Move preparation of Linux kernel environment in a separate
function and mark it as legacy. Add a Kconfig option to make
that legacy mode configurable.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:02:48 +01:00
Daniel Schwierzeck
25fc664f40 MIPS: bootm: refactor preparation of Linux kernel command line
Move preparation of Linux kernel command line in a separate
function and mark it as legacy. Add a Kconfig option to make
that legacy mode configurable.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-21 14:02:48 +01:00
Masahiro Yamada
afc366f01b Replace <compiler.h> with <linux/compiler.h>
Including <linux/compiler.h> is enough for general use.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:46 -05:00
Daniel Schwierzeck
e19db555b4 Kbuild: introduce Makefile in arch/$ARCH/
Introduce a Makefile under arch/$ARCH/ and include it in the
top Makefile (similar to Linux kernel). This allows further
refactoringi like moving architecture-specific code out of global
makefiles, deprecating config variables (CPU, CPUDIR, SOC) or
deprecating arch/$ARCH/config.mk.

In contrary to Linux kernel, U-Boot defines the ARCH variable by
Kconfig, thus the arch Makefile can only included conditionally
after the top config.mk.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:45 -05:00
Daniel Schwierzeck
6cec63d59d MIPS: bootm: remove unused or redundant header files
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27 16:20:37 +01:00
Daniel Schwierzeck
c9639421fd MIPS: bootm: add missing initramfs relocation
The initramfs is currently only relocated if the user calls
the bootm ramdisk subcommand. If bootm should be used without
subcommands, the arch-specific bootm code needs to implement
the relocation.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27 16:20:37 +01:00
Daniel Schwierzeck
426f87045c MIPS: remove board.c
After all MIPS boards are switched to generic-board, the
MIPS specific board.c can be removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27 16:20:37 +01:00
Daniel Schwierzeck
6d08e22aca MIPS: fix setup of initial stack frame
To get correct stack walking and backtrace functionality in gdb,
registers fp and ra should be initialized before calling board_init_f
or board_init_r. Thus allocating stack space and zeroing it as it is
currently done in board.c becomes obsolete.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-27 16:20:37 +01:00
Masahiro Yamada
56f31e872e kbuild: use SoC-specific CONFIG to descend into SoC directory
Use "obj-$(CONFIG_FOO) += foo/" where it is possible.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-23 06:49:02 -05:00
Masahiro Yamada
165ecd26f0 kbuild: Descend into SOC directory from CPU directory
Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-23 06:49:02 -05:00
Masahiro Yamada
cba1da495d include: move various macros to include/linux/kernel.h
U-Boot has imported various utility macros from Linux
scattering them to various places without consistency.

In include/common.h are min, max, min3, max3, ARRAY_SIZE, ALIGN,
container_of, DIV_ROUND_UP, etc.
In include/linux/compat.h are min_t, max_t, round_up, round_down,
etc.
We also have duplicated defines of min_t in some *.c files.

Moreover, we are suffering from too cluttered include/common.h.

This commit moves various macros that originate in
include/linux/kernel.h of Linux to their original position.

Note:
This commit simply moves the macros; the macros roundup,
min, max, min2, max3, ARRAY_SIZE are different
from those of Linux at this point.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-20 11:28:25 -05:00
Daniel Schwierzeck
265072ba75 MIPS: add .padding section to linker script
Commit 79fd7e649e

    MIPS: always keep all sections in u-boot ELF binary.

    Always keep all sections in u-boot ELF binary. Move all unneeded
    sections after _end to avoid allocating space in the final binary.
    Also remove .deadcode section which is now obsolete.

removed section .deadcode because the original symptoms were not
visible anymore. Unfortuneatly the binutils bug still exists.

The size of .rel.dyn section is often bigger than needed for all
entries. But objcopy only allocates space as much as required for all
reloc entries. Thus there is a gap between the last entry and
__rel_dyn_end in u-boot.bin. If u-boot is booted from RAM (e.g. in
SPL scenarios) that area could contain garbage data which could lead
to CPU exceptions during relocation.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-01 18:18:05 +01:00
Daniel Schwierzeck
837cad1e47 MIPS: refactor setting of compiler options
Refactor and unify all compiler settings in arch/mips/config.mk.
Also add tune flags for each supported CPU type.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-01 18:18:05 +01:00
Daniel Schwierzeck
aa45f75eaf MIPS: kconfig: merge targets qemu_mips and qemu_mips64
Now the user can separately select the CPU type. Thus the
targets qemu_mips and qemu_mips64 can be merged to a single
target.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-01 18:18:04 +01:00
Daniel Schwierzeck
b9863b6de2 MIPS: kconfig: globally define CONFIG_SYS_CPU for MIPS
Now the user can select the CPU type for each target. Thus
CONFIG_SYS_CPU could be set globally.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-01 18:18:04 +01:00
Daniel Schwierzeck
02611cbb7c MIPS: kconfig: add options for CPU type select
Add new Kconfig option to let the user select the targets
CPU type. Each target have to select SUPPORTS_CPU_MIPS[32,64]_R[1,2]
to indicate which CPU types are supported.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-01 18:18:03 +01:00
Daniel Schwierzeck
0e1dc3456f MIPS: kconfig: add options for endianess select
Add new Kconfig option to let the user select the targets
endianess. Each target have to select SUPPORTS_BIG_ENDIAN
and/or SUPPORTS_LITTLE_ENDIAN to indicate which endianess
is supported.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-01 18:17:22 +01:00
Masahiro Yamada
7bfd5ee117 mips: enable CONFIG_USE_PRIVATE_LIBGCC by default
Without the private libgcc, we need a full multilib toolchain with
different libgcc or multiple toolchains to build all BE/LE and
hard-float/soft-float variants of MIPS boards.  That is not feasible.

This commit allows us to build all the MIPS boards with a single
kernel.org toolchain:

https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_mips-linux.tar.xz

This change sounds reasonable for most users.  If necessary,
you can disable this option via "make menuconfig" or friends.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-10-23 13:19:15 -04:00
Masahiro Yamada
461be2f96e kconfig: remove redundant "string" type in arch and board Kconfigs
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.

We can delete the ones in arch and board Kconfig files.

This commit can be easily reproduced by the following command:

find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
    N
    s/\n[[:space:]]*string//
}
'

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-13 16:43:55 -04:00
Masahiro Yamada
90f984e397 kconfig: delete redundant CONFIG_${ARCH} definition
CONFIG_${ARCH} is defined by Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:02 -04:00
Masahiro Yamada
dd84058d24 kconfig: add board Kconfig and defconfig files
This commit adds:
 - arch/${ARCH}/Kconfig
    provide a menu to select target boards
 - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig
    set CONFIG macros to the appropriate values for each board
 - configs/${TARGET_BOARD}_defconfig
    default setting of each board

(This commit was automatically generated by a conversion script
based on boards.cfg)

In Linux Kernel, defconfig files are located under
arch/${ARCH}/configs/ directory.
It works in Linux Kernel since ARCH is always given from the
command line for cross compile.

But in U-Boot, ARCH is not given from the command line.
Which means we cannot know ARCH until the board configuration is done.
That is why all the "*_defconfig" files should be gathered into a
single directory ./configs/.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:01 -04:00
York Sun
2a1680e30e common/board_f: Initialized global data for generic board
Some platforms (tested on mpc85xx, mpc86xx) use global data before calling
function baord_inti_f(). The data should not be cleared later. Any arch
which uses global data in generic board board_init_f() should define
CONFIG_SYS_GENERIC_GLOBAL_DATA.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Simon Glass <sjg@chromium.org>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Simon Glass <sjg@chromium.org>
2014-05-12 15:20:05 -04:00
Masahiro Yamada
8e2615752e bd_info: remove bi_barudrate member from struct bd_info
gd->bd->bi_baudrate is a copy of gd->baudrate.

Since baudrate is a common feature for all architectures,
keep gd->baudrate only.

It is true that bi_baudrate was passed to the kernel in that structure
but it was a long time ago.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
2014-05-12 15:19:45 -04:00
Daniel Schwierzeck
538cf92c8c MIPS: drop incaip board
This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
2014-04-20 13:16:43 +02:00
Paul Burton
9f0868fffb MIPS: allow use of generic board
This patch allows MIPS boards to make use of generic board, replacing
arch/mips/lib/board.c with common/board_{f,r}.c and struct bd_info with
the asm-generic version.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-04-20 13:16:43 +02:00
Paul Burton
a0af08b9db MIPS: define __init_end in u-boot.lds
The generic board code uses the __init_end symbol to calculate
monitor_flash_len. Define said symbol for MIPS, equivalent to
__image_copy_end which is used for the same purpose in
arch/mips/lib/board.c.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-04-20 13:16:43 +02:00
Paul Burton
11a932fb18 MIPS: move mips_io_port_base out of board.c
Move the definition of this variable out of arch/mips/lib/board.c in
preparation for allowing use of generic board on MIPS, which will lead
to this file not being compiled.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-04-20 13:16:42 +02:00
Paul Burton
186d8159f6 MIPS: stub interrupt_init function
interrupt_init is called unconditionally by the generic board code.
Define a stub for it on MIPS like the enable & disable functions.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-04-20 13:16:42 +02:00
Masahiro Yamada
7e3d473b5e mips: xburst: remove remainders of dead board
Commit 54e458de deleted qi_lb60 board support
because of the incompatible license issue.

There is no board with XBurst CPU.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-04-20 13:16:42 +02:00
Daniel Schwierzeck
79fd7e649e MIPS: always keep all sections in u-boot ELF binary.
Always keep all sections in u-boot ELF binary. Move all unneeded
sections after _end to avoid allocating space in the final binary.
Also remove .deadcode section which is now obsolete.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-04-20 13:16:42 +02:00
Stephen Warren
eb838e7d84 usb: create common header virtual root hub descriptors
Many USB host controller drivers contain almost identical copies of the
same virtual root hub descriptors. Put these into a common file to avoid
duplication.

Note that there were some very minor differences between the descriptors
in the various files, such as:

- USB 1.0 vs. USB 1.1
- Manufacturer/Device ID
- Max packet size
- String content

I assume these aren't relevant.

Cc: Thomas Lange <thomas@corelatus.se>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Eric Millbrandt <emillbrandt@coldhaus.com>
Cc: Pierre Aubert <p.aubert@staubli.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Rodolfo Giometti <giometti@linux.it>
Cc: Zhang Wei <wei.zhang@freescale.com>
Cc: Mateusz Zalega <m.zalega@samsung.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Markus Klotzbuecher <mk@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: C Nauman <cnauman@diagraph.com>
Cc: David Müller <d.mueller@elsoft.ch>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Thomas Abraham <t-abraham@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Andrew Murray <amurray@embedded-bits.co.uk>
Cc: Matej Frančeškin <matej.franceskin@comtrade.com>
Cc: Cliff Cai <cliff.cai@analog.com>
Cc: Bryan Wu <cooloney@gmail.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-03-10 18:53:36 +01:00
Masahiro Yamada
cfda6bd2d8 mips: move CONFIG_MIPS{32, 64} definition to config.mk
All mips32 boards define CONFIG_MIPS32 in config headers
except malta boards which define it in boards.cfg.
We can consolidate them by defining it in
arch/mips/cpu/mips32/config.mk.

CONFIG_MIPS64 definition can be moved to
arch/mips/cpu/mips64/config.mk as well.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-03-07 10:59:06 -05:00
Masahiro Yamada
a0a15b441c config.mk: specify the exact path to standalone linker script
We want to change the build system to include config.mk
only from ./Makefile and spl/Makefile.
We must prepare for that in this commit.

$(src) is a moving target and not handy for our purpose.
We must replace it with a fixed path.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-03-07 10:59:06 -05:00
Masahiro Yamada
cd2e46cb38 kbuild: add CONFIG_ prefix to USE_PRIVATE_LIBGCC
Before this commit, USE_PRIVATE_LIBGCC was defined in
arch-specific config.mk and referenced in
arch/$(ARCH)/lib/Makefile.

We are not happy about parsing config.mk again and again.
We have to keep the same behavior with a different way.

By adding "CONFIG_" prefix, this macro appears
in include/autoconf.mk, include/spl-autoconf.mk.
(And treating USE_PRIVATE_LIBGCC as CONFIG macro
is reasonable enough.)

Tegra SoC family defined USE_PRIVATE_LIBGCC as "yes"
in arch/arm/cpu/arm720t/tegra*/config.mk,
whereas did not define it in arch/arm/cpu/armv7/tegra*/config.mk.

It means Tegra enables PRIVATE_LIBGCC only for SPL.
We can describe the same behavior by adding

  #ifdef CONFIG_SPL_BUILD
  # define CONFIG_USE_PRIVATE_LIBGCC
  #endif

to include/configs/tegra-common.h.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-03-07 10:59:06 -05:00
Tom Rini
32907339c2 Merge branch 'master' of git://git.denx.de/u-boot-mips 2014-03-04 18:13:06 -05:00
Daniel Schwierzeck
37f93f7b79 MIPS: fix types u64 and __u64 to unsigned long long
Linux MIPS uses asm-generic/int-ll64.h in asm/types.h.
Thus u64 and __u64 are defined as unsigned long long. Port this
over to U-Boot.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-03-04 23:18:00 +01:00
Masahiro Yamada
9b6e2c363f kbuild: fix CROSS_COMPILE settings in config.mk
The syntax
  CROSS_COMIPLE ?= <cross_compiler_prefix>
does not work because config.mk is parsed after
exporting CROSS_COMPILE.

Like Linux Kernel's arch/$(ARCH)/Makefile,
we must write as follows:

  ifeq ($(CROSS_COMPILE),)
  CROSS_COMPILE := <cross_compiler_prefix>
  endif

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-03-04 12:15:30 -05:00
Masahiro Yamada
95ddcd68ab kbuild: rename OBJCFLAGS to OBJCOPYFLAGS
Rename OBJCFLAGS to OBJCOPYFLAGS beforehand to use
"cmd_objcopy" in scripts/Makefile.lib in an upcoming commit.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-02-25 11:01:28 -05:00
Masahiro Yamada
9e4140329e kbuild: change out-of-tree build
This commit changes the working directory
where the build process occurs.

Before this commit, build process occurred under the source
tree for both in-tree and out-of-tree build.

That's why we needed to add $(obj) prefix to all generated
files in makefiles like follows:
  $(obj)u-boot.bin:  $(obj)u-boot

Here, $(obj) is empty for in-tree build, whereas it points
to the output directory for out-of-tree build.

And our old build system changes the current working directory
with "make -C <sub-dir>" syntax when descending into the
sub-directories.

On the other hand, Kbuild uses a different idea
to handle out-of-tree build and directory descending.

The build process of Kbuild always occurs under the output tree.
When "O=dir/to/store/output/files" is given, the build system
changes the current working directory to that directory and
restarts the make.

Kbuild uses "make -f $(srctree)/scripts/Makefile.build obj=<sub-dir>"
syntax for descending into sub-directories.
(We can write it like "make $(obj)=<sub-dir>" with a shorthand.)
This means the current working directory is always the top
of the output directory.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Gerhard Sittig <gsi@denx.de>
2014-02-19 11:07:50 -05:00
Paul Burton
bea12b7823 malta: enable PIIX4 SERIRQ
Whilst U-boot does not require this itself, Linux currently relies upon
it having been muxed and enabled by the bootloader. Thus in order to
preserve compatibility with current kernels before a fix is merged in
Linux we will enable the SERIRQ interrupt and mux it to its pin.

Without doing this current kernels will never receive serial port
interrupts and the end result is typically that userland appears to
hang.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-26 21:49:34 +01:00
Paul Burton
d18d49d7ad mips: don't hardcode Malta env baudrate
The baudrate passed to Linux in the environment was hardcoded at 38400.
Instead pass the correct baudrate from global data, allowing Linux to
correctly inherit the baudrate used by U-boot when console setup is not
explicitly specified.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-26 21:49:17 +01:00
Gabor Juhos
10473d0490 malta: use unmapped flash base address
The physical base address of the NOR flash is 0x1e000000
on the Malta boards. The hardware also maps the first 4MiB
of the flash into the 0x1fc00000-0x1fffffff range.

Currently, U-Boot uses the mapped address to access the
flash, which does not work in recent qemu versions.

Since commit a427338b222b43197c2776cbc996936df0302f51
(mips_malta: correct reading MIPS revision at 0x1fc00010)
writing to the mapped address space causes a CPU exception.
Due to the exception, U-Boot hangs during boot when it tries
to detect the CFI flash chip.

Use the correct physical address for the MALTA_FLASH_BASE
constant to fix the problem. In order to avoid relocation
problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE
constants.

The change makes it possible to start U-Boot on a Malta
board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also
works on older versions (tested with 1.1.1, 1.2.2, 1.4.2,
1.5.3).

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2013-11-15 11:16:59 +01:00
Paul Burton
a3e80904fb malta: arch/mips/include/asm/malta.h SPDX license tag
This patch replaces the GPL-2.0 text with a GPL-2.0
SPDX-License-Identifier tag, and adds Imagination Technologies copyright
following my recent changes.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-11 12:32:58 +01:00
Paul Burton
81f98bbd62 malta: setup PIIX4 interrupt route
Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will
be left disabled. Linux does not set up this routing but relies upon it
having been set up by the bootloader, reading back the IRQ lines which
the PIRQ[A:D] signals have been routed to.

This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11.
This matches the setup used by YAMON.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:02 +01:00
Paul Burton
e0ada6319b malta: display "U-boot" on the LCD screen
Displaying a message on the LCD screen is a simple yet effective way to
show the user that the board has booted successfully.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:01 +01:00
Paul Burton
baf37f06c5 malta: support for coreFPGA6 boards
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.

Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.

Tested on:
  - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
    with and without an L2 cache.
  - QEMU.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:01 +01:00
Paul Burton
7a9d109b00 qemu-malta: rename to just "malta"
This is in preparation for adapting this board to function correctly on
a physical MIPS Malta board. The board is moved into an "imgtec" vendor
directory at the same time in order to ready us for any other boards
supported by Imagination in the future.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:01 +01:00
Paul Burton
fa476f75bf mips32: detect L1 cache sizes if they're not defined
For boards such as the MIPS Malta with an FPGA core card it is desirable
to be able to detect the L1 cache sizes at runtime, since they are not
dependant upon the board but on the FPGA bitstream in use. This patch
performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are
not defined by the board configuration. In cases where the sizes are
detected this patch also removes the restriction that the I-cache &
D-cache line sizes must be the same, as this is not necessarily true.

If the cache sizes are defined by a configuration then they will be
hardcoded as before, so this patch will not add overhead to such
boards.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2013-11-09 17:21:01 +01:00
Masahiro Yamada
643aae1406 include: delete include/linux/config.h
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 15:25:13 -05:00
Masahiro Yamada
0f0f75774e cosmetic: remove empty lines at the top of file
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 09:41:37 -05:00
Masahiro Yamada
f6e2c0f3e3 mips: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-10-31 13:26:45 -04:00
Troy Kisky
06d513ecb6 usb: add enum usb_init_type parameter to usb_lowlevel_init
This parameter will later be used to verify OTG ports.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-10-20 23:45:26 +02:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Daniel Schwierzeck
4b17645d5d MIPS: bootm: drop obsolete Qemu specific bootm implementation
The Qemu specific bootm implementation was intended for a special
Qemu target in Linux kernel. But this target has been dropped in
v2.6.25-rc1 by commit 302922e5f6901eb6f29c58539631f71b3d9746b8

    Author: Ralf Baechle <ralf@linux-mips.org>
    Date:   Tue Jan 29 10:15:02 2008 +0000

    [MIPS] Qemu: Remove platform.

    The Qemu platform was originally implemented to have an easily supportable
    platform until Qemu reaches a state where it emulates a real world system.
    Since the latest release Qemu is capable of emulating the MIPSsim and
    Malta platforms, so this goal has been reached.  The Qemu plaform is also
    rather underfeatured so less useful than a Malta emulation.

Thus the special bootm implementation is obsolete by now and can be
dropped. The Qemu support in U-Boot is going to be replaced by MIPS Malta
board support.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
b87493f49a MIPS: bootm: add YAMON style Linux preparation/jump code for Qemu Malta
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
6c154552b0 MIPS: bootm: add support for generic relocation of init ramdisks
All linux kernels after v2.6 require a page-aligned location of
an external init ramdisk. Enable CONFIG_SYS_BOOT_RAMDISK_HIGH to
support this with the generic U-Boot relocation code.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
15f8aa9093 MIPS: bootm: refactor initialisation of kernel environment
Move initialisation of Linux environment to separate functions.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
59e8cbdb15 MIPS: bootm: refactor initialisation of kernel cmdline
Move initialisation of Linux command line to separate functions.
Also add support for bootm subcommand 'cmdline'.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
f66cc1e348 MIPS: bootm: add support for LMB
This is required for init ramdisk relocation and device tree
support.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
c4b37847d3 MIPS: bootm: optimize kernel entry call
Fix signature of kernel entry function. Mark the kernel entry
with __noreturn for better code optimisation.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Daniel Schwierzeck
45bde489e3 MIPS: bootm: fix checkpatch.pl warnings
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-08-13 11:58:48 +02:00
Gabor Juhos
db2c86d7d7 MIPS: mips32/cache.S: use v1 register for indirect function calls
Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:07 -04:00
Gabor Juhos
ee8b1e2959 MIPS: mips32/cache.S: store cache line size in t8 register
Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:07 -04:00
Gabor Juhos
c325916563 MIPS: mips32/cache.S: save return address in t9 register
Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
d707e5b713 MIPS: xburst/start.S: rework relocation info check
Make it similar to the code in mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
e5c868a208 MIPS: xburst/start.S: use t8 register for dynamic relocation
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
f01d693535 MIPS: xburst/start.S: save gd in s0 register
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
ba9cf07122 MIPS: xburst/start.S: save relocation offset in s1 register
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:06 -04:00
Gabor Juhos
9a28e0d177 MIPS: xburst/start.S: save relocation address in s2 register
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:05 -04:00
Gabor Juhos
691995f9ab MIPS: mips32/start.S: rework relocation info check
Make it similar to the code in mips64/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-07-24 09:51:05 -04:00