mirror of
https://github.com/AsahiLinux/u-boot
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MIPS: drop incaip board
This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
parent
5f978d7efe
commit
538cf92c8c
23 changed files with 1 additions and 5201 deletions
4
MAKEALL
4
MAKEALL
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@ -419,10 +419,6 @@ LIST_arm="$(targets_by_arch arm | \
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#########################################################################
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LIST_mips4kc=" \
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incaip \
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incaip_100MHz \
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incaip_133MHz \
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incaip_150MHz \
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qemu_mips \
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vct_platinum \
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vct_platinum_small \
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2011
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = incaip_wdt.o
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obj-y += incaip_clock.o asc_serial.o
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@ -1,300 +0,0 @@
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/*
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* (INCA) ASC UART support
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/inca-ip.h>
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#include <serial.h>
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#include <linux/compiler.h>
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#include "asc_serial.h"
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#define SET_BIT(reg, mask) reg |= (mask)
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#define CLEAR_BIT(reg, mask) reg &= (~mask)
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#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
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#define SET_BITS(reg, mask) SET_BIT(reg, mask)
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#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
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extern uint incaip_get_fpiclk(void);
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static int serial_setopt (void);
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/* pointer to ASC register base address */
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static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
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/******************************************************************************
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*
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* serial_init - initialize a INCAASC channel
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*
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* This routine initializes the number of data bits, parity
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* and set the selected baud rate. Interrupts are disabled.
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* Set the modem control signals if the option is selected.
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*
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* RETURNS: N/A
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*/
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static int asc_serial_init(void)
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{
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/* we have to set PMU.EN13 bit to enable an ASC device*/
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INCAASC_PMU_ENABLE(13);
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/* and we have to set CLC register*/
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CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
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SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
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/* initialy we are in async mode */
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pAsc->asc_con = ASCCON_M_8ASYNC;
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/* select input port */
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pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
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/* TXFIFO's filling level */
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SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
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ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
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/* enable TXFIFO */
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SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
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/* RXFIFO's filling level */
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SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
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ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
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/* enable RXFIFO */
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SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
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/* enable error signals */
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SET_BIT(pAsc->asc_con, ASCCON_FEN);
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SET_BIT(pAsc->asc_con, ASCCON_OEN);
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/* acknowledge ASC interrupts */
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ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
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/* disable ASC interrupts */
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ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
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/* set FIFOs into the transparent mode */
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SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
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SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
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/* set baud rate */
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serial_setbrg();
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/* set the options */
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serial_setopt();
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return 0;
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}
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static void asc_serial_setbrg(void)
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{
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ulong uiReloadValue, fdv;
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ulong f_ASC;
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f_ASC = incaip_get_fpiclk();
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#ifndef INCAASC_USE_FDV
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fdv = 2;
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uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
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#else
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fdv = INCAASC_FDV_HIGH_BAUDRATE;
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uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
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#endif /* INCAASC_USE_FDV */
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if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
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{
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#ifndef INCAASC_USE_FDV
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fdv = 3;
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uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
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#else
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fdv = INCAASC_FDV_LOW_BAUDRATE;
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uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
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#endif /* INCAASC_USE_FDV */
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if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
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{
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return; /* can't impossibly generate that baud rate */
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}
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}
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/* Disable Baud Rate Generator; BG should only be written when R=0 */
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CLEAR_BIT(pAsc->asc_con, ASCCON_R);
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#ifndef INCAASC_USE_FDV
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/*
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* Disable Fractional Divider (FDE)
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* Divide clock by reload-value + constant (BRS)
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*/
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/* FDE = 0 */
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CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
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if ( fdv == 2 )
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CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
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else
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SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
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#else /* INCAASC_USE_FDV */
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/* Enable Fractional Divider */
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SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
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/* Set fractional divider value */
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pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
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#endif /* INCAASC_USE_FDV */
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/* Set reload value in BG */
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pAsc->asc_bg = uiReloadValue;
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/* Enable Baud Rate Generator */
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SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
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}
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/*******************************************************************************
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*
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* serial_setopt - set the serial options
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*
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* Set the channel operating mode to that specified. Following options
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* are supported: CREAD, CSIZE, PARENB, and PARODD.
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*
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* Note, this routine disables the transmitter. The calling routine
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* may have to re-enable it.
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*
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* RETURNS:
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* Returns 0 to indicate success, otherwise -1 is returned
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*/
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static int serial_setopt (void)
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{
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ulong con;
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switch ( ASC_OPTIONS & ASCOPT_CSIZE )
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{
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/* 7-bit-data */
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case ASCOPT_CS7:
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con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
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break;
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/* 8-bit-data */
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case ASCOPT_CS8:
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if ( ASC_OPTIONS & ASCOPT_PARENB )
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con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
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else
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con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
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break;
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/*
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* only 7 and 8-bit frames are supported
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* if we don't use IOCTL extensions
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*/
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default:
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return -1;
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}
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if ( ASC_OPTIONS & ASCOPT_STOPB )
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SET_BIT(con, ASCCON_STP); /* 2 stop bits */
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else
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CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
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if ( ASC_OPTIONS & ASCOPT_PARENB )
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SET_BIT(con, ASCCON_PEN); /* enable parity checking */
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else
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CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
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if ( ASC_OPTIONS & ASCOPT_PARODD )
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SET_BIT(con, ASCCON_ODD); /* odd parity */
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else
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CLEAR_BIT(con, ASCCON_ODD); /* even parity */
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if ( ASC_OPTIONS & ASCOPT_CREAD )
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
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pAsc->asc_con |= con;
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return 0;
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}
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static void asc_serial_putc(const char c)
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{
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uint txFl = 0;
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if (c == '\n') serial_putc ('\r');
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/* check do we have a free space in the TX FIFO */
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/* get current filling level */
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do
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{
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txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
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}
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while ( txFl == INCAASC_TXFIFO_FULL );
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pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
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/* check for errors */
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if ( pAsc->asc_con & ASCCON_OE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
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return;
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}
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}
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static int asc_serial_getc(void)
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{
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ulong symbol_mask;
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char c;
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while (!serial_tstc());
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symbol_mask =
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((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
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c = (char)(pAsc->asc_rbuf & symbol_mask);
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return c;
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}
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static int asc_serial_tstc(void)
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{
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int res = 1;
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if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
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{
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res = 0;
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}
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else if ( pAsc->asc_con & ASCCON_FE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
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res = 0;
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}
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else if ( pAsc->asc_con & ASCCON_PE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
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res = 0;
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}
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else if ( pAsc->asc_con & ASCCON_OE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
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res = 0;
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}
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return res;
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}
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static struct serial_device asc_serial_drv = {
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.name = "asc_serial",
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.start = asc_serial_init,
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.stop = NULL,
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.setbrg = asc_serial_setbrg,
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.putc = asc_serial_putc,
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.puts = default_serial_puts,
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.getc = asc_serial_getc,
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.tstc = asc_serial_tstc,
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};
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void asc_serial_initialize(void)
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{
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serial_register(&asc_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &asc_serial_drv;
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}
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@ -1,177 +0,0 @@
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/* incaAscSio.h - (INCA) ASC UART tty driver header */
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#ifndef __INCincaAscSioh
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#define __INCincaAscSioh
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#include <asm/inca-ip.h>
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/* channel operating modes */
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#define ASCOPT_CSIZE 0x00000003
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#define ASCOPT_CS7 0x00000001
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#define ASCOPT_CS8 0x00000002
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#define ASCOPT_PARENB 0x00000004
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#define ASCOPT_STOPB 0x00000008
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#define ASCOPT_PARODD 0x00000010
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#define ASCOPT_CREAD 0x00000020
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#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
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/* ASC input select (0 or 1) */
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#define CONSOLE_TTY 0
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/* use fractional divider for baudrate settings */
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#define INCAASC_USE_FDV
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#ifdef INCAASC_USE_FDV
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#define INCAASC_FDV_LOW_BAUDRATE 71
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#define INCAASC_FDV_HIGH_BAUDRATE 453
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#endif /*INCAASC_USE_FDV*/
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#define INCAASC_TXFIFO_FL 1
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#define INCAASC_RXFIFO_FL 1
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#define INCAASC_TXFIFO_FULL 16
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/* interrupt lines masks for the ASC device interrupts*/
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/* change these macroses if it's necessary */
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#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
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#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
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#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
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#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
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#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
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/* interrupt controller access macros */
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#define ASC_INTERRUPTS_ENABLE(X) \
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*((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
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#define ASC_INTERRUPTS_DISABLE(X) \
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*((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
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#define ASC_INTERRUPTS_CLEAR(X) \
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*((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
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/* CLC register's bits and bitfields */
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#define ASCCLC_DISR 0x00000001
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#define ASCCLC_DISS 0x00000002
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#define ASCCLC_RMCMASK 0x0000FF00
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#define ASCCLC_RMCOFFSET 8
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/* CON register's bits and bitfields */
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#define ASCCON_MODEMASK 0x0007
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#define ASCCON_M_8SYNC 0x0
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#define ASCCON_M_8ASYNC 0x1
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#define ASCCON_M_8IRDAASYNC 0x2
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#define ASCCON_M_7ASYNCPAR 0x3
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#define ASCCON_M_9ASYNC 0x4
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#define ASCCON_M_8WAKEUPASYNC 0x5
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#define ASCCON_M_8ASYNCPAR 0x7
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#define ASCCON_STP 0x0008
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#define ASCCON_REN 0x0010
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#define ASCCON_PEN 0x0020
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#define ASCCON_FEN 0x0040
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#define ASCCON_OEN 0x0080
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#define ASCCON_PE 0x0100
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#define ASCCON_FE 0x0200
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#define ASCCON_OE 0x0400
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#define ASCCON_FDE 0x0800
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#define ASCCON_ODD 0x1000
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#define ASCCON_BRS 0x2000
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#define ASCCON_LB 0x4000
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#define ASCCON_R 0x8000
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/* WHBCON register's bits and bitfields */
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#define ASCWHBCON_CLRREN 0x0010
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#define ASCWHBCON_SETREN 0x0020
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#define ASCWHBCON_CLRPE 0x0100
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#define ASCWHBCON_CLRFE 0x0200
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#define ASCWHBCON_CLROE 0x0400
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#define ASCWHBCON_SETPE 0x0800
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#define ASCWHBCON_SETFE 0x1000
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#define ASCWHBCON_SETOE 0x2000
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/* ABCON register's bits and bitfields */
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#define ASCABCON_ABEN 0x0001
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#define ASCABCON_AUREN 0x0002
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#define ASCABCON_ABSTEN 0x0004
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#define ASCABCON_ABDETEN 0x0008
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#define ASCABCON_FCDETEN 0x0010
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#define ASCABCON_EMMASK 0x0300
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#define ASCABCON_EMOFF 8
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#define ASCABCON_EM_DISAB 0x0
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#define ASCABCON_EM_DURAB 0x1
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#define ASCABCON_EM_ALWAYS 0x2
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#define ASCABCON_TXINV 0x0400
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#define ASCABCON_RXINV 0x0800
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/* FDV register mask, offset and bitfields*/
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#define ASCFDV_VALUE_MASK 0x000001FF
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/* WHBABCON register's bits and bitfields */
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#define ASCWHBABCON_SETABEN 0x0001
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#define ASCWHBABCON_CLRABEN 0x0002
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/* ABSTAT register's bits and bitfields */
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#define ASCABSTAT_FCSDET 0x0001
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#define ASCABSTAT_FCCDET 0x0002
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#define ASCABSTAT_SCSDET 0x0004
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#define ASCABSTAT_SCCDET 0x0008
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#define ASCABSTAT_DETWAIT 0x0010
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/* WHBABSTAT register's bits and bitfields */
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#define ASCWHBABSTAT_CLRFCSDET 0x0001
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#define ASCWHBABSTAT_SETFCSDET 0x0002
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#define ASCWHBABSTAT_CLRFCCDET 0x0004
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#define ASCWHBABSTAT_SETFCCDET 0x0008
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#define ASCWHBABSTAT_CLRSCSDET 0x0010
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#define ASCWHBABSTAT_SETSCSDET 0x0020
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#define ASCWHBABSTAT_SETSCCDET 0x0040
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#define ASCWHBABSTAT_CLRSCCDET 0x0080
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#define ASCWHBABSTAT_CLRDETWAIT 0x0100
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#define ASCWHBABSTAT_SETDETWAIT 0x0200
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/* TXFCON register's bits and bitfields */
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#define ASCTXFCON_TXFEN 0x0001
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#define ASCTXFCON_TXFFLU 0x0002
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#define ASCTXFCON_TXTMEN 0x0004
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
|
||||
/* RXFCON register's bits and bitfields */
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXTMEN 0x0004
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
|
||||
/* FSTAT register's bits and bitfields */
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
|
||||
|
||||
typedef struct /* incaAsc_t */
|
||||
{
|
||||
volatile unsigned long asc_clc; /*0x0000*/
|
||||
volatile unsigned long asc_pisel; /*0x0004*/
|
||||
volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/
|
||||
volatile unsigned long asc_con; /*0x0010*/
|
||||
volatile unsigned long asc_bg; /*0x0014*/
|
||||
volatile unsigned long asc_fdv; /*0x0018*/
|
||||
volatile unsigned long asc_pmw; /* not used */ /*0x001C*/
|
||||
volatile unsigned long asc_tbuf; /*0x0020*/
|
||||
volatile unsigned long asc_rbuf; /*0x0024*/
|
||||
volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/
|
||||
volatile unsigned long asc_abcon; /*0x0030*/
|
||||
volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
|
||||
volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/
|
||||
volatile unsigned long asc_rxfcon; /*0x0040*/
|
||||
volatile unsigned long asc_txfcon; /*0x0044*/
|
||||
volatile unsigned long asc_fstat; /*0x0048*/
|
||||
volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/
|
||||
volatile unsigned long asc_whbcon; /*0x0050*/
|
||||
volatile unsigned long asc_whbabcon; /*0x0054*/
|
||||
volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/
|
||||
|
||||
} incaAsc_t;
|
||||
|
||||
#endif /* __INCincaAscSioh */
|
|
@ -1,8 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2011
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -mtune=4kc
|
|
@ -1,100 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/inca-ip.h>
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* get_cpuclk - returns the frequency of the CPU.
|
||||
*
|
||||
* Gets the value directly from the INCA-IP hardware.
|
||||
*
|
||||
* RETURNS:
|
||||
* 150.000.000 for 150 MHz
|
||||
* 133.333.333 for 133 MHz (= 400MHz/3)
|
||||
* 100.000.000 for 100 MHz (= 400MHz/4)
|
||||
* NOTE:
|
||||
* This functions should be used by the hardware driver to get the correct
|
||||
* frequency of the CPU. Don't use the macros, which are set to init the CPU
|
||||
* frequency in the ROM code.
|
||||
*/
|
||||
uint incaip_get_cpuclk (void)
|
||||
{
|
||||
/*-------------------------------------------------------------------------*/
|
||||
/* CPU Clock Input Multiplexer (MUX I) */
|
||||
/* Multiplexer MUX I selects the maximum input clock to the CPU. */
|
||||
/*-------------------------------------------------------------------------*/
|
||||
if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) &
|
||||
INCA_IP_CGU_CGU_MUXCR_MUXI) {
|
||||
/* MUX I set to 150 MHz clock */
|
||||
return 150000000;
|
||||
} else {
|
||||
/* MUX I set to 100/133 MHz clock */
|
||||
if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) {
|
||||
/* Division value is 1/3, maximum CPU operating */
|
||||
/* frequency is 133.3 MHz */
|
||||
return 133333333;
|
||||
} else {
|
||||
/* Division value is 1/4, maximum CPU operating */
|
||||
/* frequency is 100 MHz */
|
||||
return 100000000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* get_fpiclk - returns the frequency of the FPI bus.
|
||||
*
|
||||
* Gets the value directly from the INCA-IP hardware.
|
||||
*
|
||||
* RETURNS: Frquency in Hz
|
||||
*
|
||||
* NOTE:
|
||||
* This functions should be used by the hardware driver to get the correct
|
||||
* frequency of the CPU. Don't use the macros, which are set to init the CPU
|
||||
* frequency in the ROM code.
|
||||
* The calculation for the
|
||||
*/
|
||||
uint incaip_get_fpiclk (void)
|
||||
{
|
||||
uint clkCPU;
|
||||
|
||||
clkCPU = incaip_get_cpuclk ();
|
||||
|
||||
switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) {
|
||||
case 0x4:
|
||||
return clkCPU >> 1; /* devided by 2 */
|
||||
break;
|
||||
case 0x8:
|
||||
return clkCPU >> 2; /* devided by 4 */
|
||||
break;
|
||||
default:
|
||||
return clkCPU;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int incaip_set_cpuclk (void)
|
||||
{
|
||||
extern void ebu_init(long);
|
||||
extern void cgu_init(long);
|
||||
extern void sdram_init(long);
|
||||
char tmp[64];
|
||||
ulong cpuclk;
|
||||
|
||||
if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) {
|
||||
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
|
||||
cgu_init (cpuclk);
|
||||
ebu_init (cpuclk);
|
||||
sdram_init (cpuclk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -1,55 +0,0 @@
|
|||
/*
|
||||
* INCA-IP Watchdog timer management code.
|
||||
*
|
||||
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
|
||||
#define WD_BASE 0xb8000000
|
||||
#define WD_CON0(value) 0x0020(value)
|
||||
#define WD_CON1(value) 0x0024(value)
|
||||
#define WD_DISABLE 0x00000008
|
||||
#define WD_ENABLE 0x00000000
|
||||
#define WD_WRITE_PW 0xFFFC00F8
|
||||
#define WD_WRITE_ENDINIT 0xFFFC00F3
|
||||
#define WD_WRITE_INIT 0xFFFC00F2
|
||||
|
||||
|
||||
.globl disable_incaip_wdt
|
||||
disable_incaip_wdt:
|
||||
li t0, WD_BASE
|
||||
|
||||
/* Calculate password.
|
||||
*/
|
||||
lw t2, WD_CON1(t0)
|
||||
and t2, 0xC
|
||||
|
||||
lw t3, WD_CON0(t0)
|
||||
and t3, 0xFFFFFF01
|
||||
|
||||
or t3, t2
|
||||
or t3, 0xF0
|
||||
|
||||
sw t3, WD_CON0(t0) /* write password */
|
||||
|
||||
/* Clear ENDINIT.
|
||||
*/
|
||||
li t1, WD_WRITE_INIT
|
||||
sw t1, WD_CON0(t0)
|
||||
|
||||
|
||||
li t1, WD_DISABLE
|
||||
sw t1, WD_CON1(t0) /* disable watchdog */
|
||||
li t1, WD_WRITE_PW
|
||||
sw t1, WD_CON0(t0) /* write password */
|
||||
li t1, WD_WRITE_ENDINIT
|
||||
sw t1, WD_CON0(t0) /* end command */
|
||||
|
||||
jr ra
|
||||
nop
|
File diff suppressed because it is too large
Load diff
|
@ -21,5 +21,3 @@ static inline unsigned long image_copy_end(void)
|
|||
extern char __image_copy_end[];
|
||||
return (unsigned long) &__image_copy_end;
|
||||
}
|
||||
|
||||
extern int incaip_set_cpuclk(void);
|
||||
|
|
|
@ -103,9 +103,6 @@ init_fnc_t *init_sequence[] = {
|
|||
board_early_init_f,
|
||||
timer_init,
|
||||
env_init, /* initialize environment */
|
||||
#ifdef CONFIG_INCA_IP
|
||||
incaip_set_cpuclk, /* set cpu clock according to env. variable */
|
||||
#endif
|
||||
init_baudrate, /* initialize baudrate settings */
|
||||
serial_init, /* serial communications setup */
|
||||
console_init_f,
|
||||
|
|
|
@ -1,9 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2003-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = incaip.o flash.o
|
||||
obj-y += lowlevel_init.o
|
|
@ -1,57 +0,0 @@
|
|||
|
||||
Flash programming on the INCA-IP board is complicated because of the
|
||||
EBU swapping unit. A BDI2000 can be used for flash programming only
|
||||
if the EBU swapping unit is enabled; otherwise it will not detect the
|
||||
flash memory. But the EBU swapping unit is disadbled after reset, so
|
||||
if you program some code to flash with the swapping unit on, it will
|
||||
not be runnable with the swapping unit off.
|
||||
|
||||
The consequence is that you have to write a pre-swapped image to
|
||||
flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is
|
||||
provided in the "tools/" directory. Use it as follows:
|
||||
|
||||
bash$ ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp
|
||||
|
||||
Note that the current BDI config file _disables_ the EBU swapping
|
||||
unit for the flash bank 0. To enable it, (this is required for the
|
||||
BDI flash commands to work) uncomment the following line in the
|
||||
config file:
|
||||
|
||||
;WM32 0xb8000260 0x404161ff ; Swapping unit enabled
|
||||
|
||||
and comment out
|
||||
|
||||
WM32 0xb8000260 0x004161ff ; Swapping unit disabled
|
||||
|
||||
Alternatively, you can use "mm 0xb8000260 <value>" commands to
|
||||
enable/disable the swapping unit manually.
|
||||
|
||||
Just for reference, here is the complete sequence of actions we took
|
||||
to install a U-Boot image into flash.
|
||||
|
||||
1. ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp
|
||||
|
||||
2. From BDI:
|
||||
|
||||
mm 0xb8000260 0x404161ff
|
||||
erase 0xb0000000
|
||||
erase 0xb0010000
|
||||
prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin
|
||||
mm 0xb8000260 0x004161ff
|
||||
go 0xb0000000
|
||||
|
||||
|
||||
Ethernet autonegotiation needs some time to complete. Instead of
|
||||
delaying the boot process in all cases, we just start the
|
||||
autonegotiation process when U-Boot comes up and that is all. Most
|
||||
likely, it will complete by the time the network transfer is
|
||||
attempted for the first time. In the worst case, if a transfer is
|
||||
attempted before the autonegotiation is complete, just a single
|
||||
packet would be lost resulting in a single timeout error, and then
|
||||
the transfer would proceed normally. So the time that we would have
|
||||
lost unconditionally waiting for the autonegotiation to complete, we
|
||||
have to wait only if the file transfer is started immediately after
|
||||
reset. We've verified that this works for all the clock
|
||||
configurations.
|
||||
|
||||
(C) 2003 Wolfgang Denk
|
|
@ -1,16 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
#
|
||||
# INCA-IP board with MIPS 4Kc CPU core
|
||||
#
|
||||
|
||||
# ROM version
|
||||
CONFIG_SYS_TEXT_BASE = 0xB0000000
|
||||
|
||||
# RAM version
|
||||
#CONFIG_SYS_TEXT_BASE = 0x80100000
|
|
@ -1,655 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/inca-ip.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
|
||||
* has nothing to do with the flash chip being 8-bit or 16-bit.
|
||||
*/
|
||||
#ifdef CONFIG_FLASH_16BIT
|
||||
typedef unsigned short FLASH_PORT_WIDTH;
|
||||
typedef volatile unsigned short FLASH_PORT_WIDTHV;
|
||||
#define FLASH_ID_MASK 0xFFFF
|
||||
#else
|
||||
typedef unsigned long FLASH_PORT_WIDTH;
|
||||
typedef volatile unsigned long FLASH_PORT_WIDTHV;
|
||||
#define FLASH_ID_MASK 0xFFFFFFFF
|
||||
#endif
|
||||
|
||||
#define FPW FLASH_PORT_WIDTH
|
||||
#define FPWV FLASH_PORT_WIDTHV
|
||||
|
||||
#define ORMASK(size) ((-size) & OR_AM_MSK)
|
||||
|
||||
#if 0
|
||||
#define FLASH_CYCLE1 0x0555
|
||||
#define FLASH_CYCLE2 0x02aa
|
||||
#else
|
||||
#define FLASH_CYCLE1 0x0554
|
||||
#define FLASH_CYCLE2 0x02ab
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
|
||||
static void flash_reset(flash_info_t *info);
|
||||
static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
|
||||
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
|
||||
static void flash_get_offsets(ulong base, flash_info_t *info);
|
||||
static flash_info_t *flash_get_info(ulong base);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* flash_init()
|
||||
*
|
||||
* sets up flash_info and returns size of FLASH (bytes)
|
||||
*/
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size = 0;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
|
||||
ulong * buscon = (ulong *)
|
||||
((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2);
|
||||
|
||||
/* Disable write protection */
|
||||
*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
|
||||
|
||||
#if 1
|
||||
memset(&flash_info[i], 0, sizeof(flash_info_t));
|
||||
#endif
|
||||
|
||||
flash_info[i].size =
|
||||
flash_get_size((FPW *)flashbase, &flash_info[i]);
|
||||
|
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
|
||||
i, flash_info[i].size);
|
||||
}
|
||||
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
|
||||
/* monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_MONITOR_BASE,
|
||||
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
|
||||
flash_get_info(CONFIG_SYS_MONITOR_BASE));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
/* ENV protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
|
||||
flash_get_info(CONFIG_ENV_ADDR));
|
||||
#endif
|
||||
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_reset(flash_info_t *info)
|
||||
{
|
||||
FPWV *base = (FPWV *)(info->start[0]);
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
|
||||
*base = (FPW)0x00FF00FF; /* Intel Read Mode */
|
||||
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
|
||||
*base = (FPW)0x00F000F0; /* AMD Read Mode */
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* set up sector start address table */
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
|
||||
&& (info->flash_id & FLASH_BTYPE)) {
|
||||
int bootsect_size; /* number of bytes/boot sector */
|
||||
int sect_size; /* number of bytes/regular sector */
|
||||
|
||||
bootsect_size = 0x00002000 * (sizeof(FPW)/2);
|
||||
sect_size = 0x00010000 * (sizeof(FPW)/2);
|
||||
|
||||
/* set sector offsets for bottom boot block type */
|
||||
for (i = 0; i < 8; ++i) {
|
||||
info->start[i] = base + (i * bootsect_size);
|
||||
}
|
||||
for (i = 8; i < info->sector_count; i++) {
|
||||
info->start[i] = base + ((i - 7) * sect_size);
|
||||
}
|
||||
}
|
||||
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
|
||||
&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
|
||||
|
||||
int sect_size; /* number of bytes/sector */
|
||||
|
||||
sect_size = 0x00010000 * (sizeof(FPW)/2);
|
||||
|
||||
/* set up sector start address table (uniform sector type) */
|
||||
for( i = 0; i < info->sector_count; i++ )
|
||||
info->start[i] = base + (i * sect_size);
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
static flash_info_t *flash_get_info(ulong base)
|
||||
{
|
||||
int i;
|
||||
flash_info_t * info;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
|
||||
info = & flash_info[i];
|
||||
if (info->start[0] <= base && base < info->start[0] + info->size)
|
||||
break;
|
||||
}
|
||||
|
||||
return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
uchar *boottype;
|
||||
uchar *bootletter;
|
||||
char *fmt;
|
||||
uchar botbootletter[] = "B";
|
||||
uchar topbootletter[] = "T";
|
||||
uchar botboottype[] = "bottom boot sector";
|
||||
uchar topboottype[] = "top boot sector";
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
|
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
case FLASH_MAN_SST: printf ("SST "); break;
|
||||
case FLASH_MAN_STM: printf ("STM "); break;
|
||||
case FLASH_MAN_INTEL: printf ("INTEL "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
/* check for top or bottom boot, if it applies */
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
boottype = botboottype;
|
||||
bootletter = botbootletter;
|
||||
}
|
||||
else {
|
||||
boottype = topboottype;
|
||||
bootletter = topbootletter;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM640U:
|
||||
fmt = "29LV641D (64 Mbit, uniform sectors)\n";
|
||||
break;
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F800C3T:
|
||||
fmt = "28F800C3%s (8 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL800B:
|
||||
case FLASH_INTEL800T:
|
||||
fmt = "28F800B3%s (8 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F160C3T:
|
||||
fmt = "28F160C3%s (16 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL160B:
|
||||
case FLASH_INTEL160T:
|
||||
fmt = "28F160B3%s (16 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F320C3T:
|
||||
fmt = "28F320C3%s (32 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL320B:
|
||||
case FLASH_INTEL320T:
|
||||
fmt = "28F320B3%s (32 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_28F640C3T:
|
||||
fmt = "28F640C3%s (64 Mbit, %s)\n";
|
||||
break;
|
||||
case FLASH_INTEL640B:
|
||||
case FLASH_INTEL640T:
|
||||
fmt = "28F640B3%s (64 Mbit, %s)\n";
|
||||
break;
|
||||
default:
|
||||
fmt = "Unknown Chip Type\n";
|
||||
break;
|
||||
}
|
||||
|
||||
printf (fmt, bootletter, boottype);
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20,
|
||||
info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
ulong flash_get_size (FPWV *addr, flash_info_t *info)
|
||||
{
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
|
||||
/* Write auto select command sequence and test FLASH answer */
|
||||
addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
|
||||
addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
|
||||
addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
|
||||
|
||||
/* The manufacturer codes are only 1 byte, so just use 1 byte.
|
||||
* This works for any bus width and any FLASH device width.
|
||||
*/
|
||||
switch (addr[1] & 0xff) {
|
||||
|
||||
case (uchar)AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
|
||||
case (uchar)INTEL_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_INTEL;
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
|
||||
if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
|
||||
|
||||
case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
|
||||
info->flash_id += FLASH_AM640U;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x00800000 * (sizeof(FPW)/2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
case (FPW)INTEL_ID_28F800C3B:
|
||||
info->flash_id += FLASH_28F800C3B;
|
||||
info->sector_count = 23;
|
||||
info->size = 0x00100000 * (sizeof(FPW)/2);
|
||||
break; /* => 1 or 2 MB */
|
||||
|
||||
case (FPW)INTEL_ID_28F800B3B:
|
||||
info->flash_id += FLASH_INTEL800B;
|
||||
info->sector_count = 23;
|
||||
info->size = 0x00100000 * (sizeof(FPW)/2);
|
||||
break; /* => 1 or 2 MB */
|
||||
|
||||
case (FPW)INTEL_ID_28F160C3B:
|
||||
info->flash_id += FLASH_28F160C3B;
|
||||
info->sector_count = 39;
|
||||
info->size = 0x00200000 * (sizeof(FPW)/2);
|
||||
break; /* => 2 or 4 MB */
|
||||
|
||||
case (FPW)INTEL_ID_28F160B3B:
|
||||
info->flash_id += FLASH_INTEL160B;
|
||||
info->sector_count = 39;
|
||||
info->size = 0x00200000 * (sizeof(FPW)/2);
|
||||
break; /* => 2 or 4 MB */
|
||||
|
||||
case (FPW)INTEL_ID_28F320C3B:
|
||||
info->flash_id += FLASH_28F320C3B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000 * (sizeof(FPW)/2);
|
||||
break; /* => 4 or 8 MB */
|
||||
|
||||
case (FPW)INTEL_ID_28F320B3B:
|
||||
info->flash_id += FLASH_INTEL320B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000 * (sizeof(FPW)/2);
|
||||
break; /* => 4 or 8 MB */
|
||||
|
||||
case (FPW)INTEL_ID_28F640C3B:
|
||||
info->flash_id += FLASH_28F640C3B;
|
||||
info->sector_count = 135;
|
||||
info->size = 0x00800000 * (sizeof(FPW)/2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
case (FPW)INTEL_ID_28F640B3B:
|
||||
info->flash_id += FLASH_INTEL640B;
|
||||
info->sector_count = 135;
|
||||
info->size = 0x00800000 * (sizeof(FPW)/2);
|
||||
break; /* => 8 or 16 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* => no or unknown flash */
|
||||
}
|
||||
|
||||
flash_get_offsets((ulong)addr, info);
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
flash_reset(info);
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
FPWV *addr;
|
||||
int flag, prot, sect;
|
||||
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
|
||||
ulong start, now, last;
|
||||
int rcode = 0;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_INTEL800B:
|
||||
case FLASH_INTEL160B:
|
||||
case FLASH_INTEL320B:
|
||||
case FLASH_INTEL640B:
|
||||
case FLASH_28F800C3B:
|
||||
case FLASH_28F160C3B:
|
||||
case FLASH_28F320C3B:
|
||||
case FLASH_28F640C3B:
|
||||
case FLASH_AM640U:
|
||||
break;
|
||||
case FLASH_UNKNOWN:
|
||||
default:
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
last = get_timer(0);
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
|
||||
|
||||
if (info->protect[sect] != 0) /* protected, skip it */
|
||||
continue;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr = (FPWV *)(info->start[sect]);
|
||||
if (intel) {
|
||||
*addr = (FPW)0x00500050; /* clear status register */
|
||||
*addr = (FPW)0x00200020; /* erase setup */
|
||||
*addr = (FPW)0x00D000D0; /* erase confirm */
|
||||
}
|
||||
else {
|
||||
/* must be AMD style if not Intel */
|
||||
FPWV *base; /* first address in bank */
|
||||
|
||||
base = (FPWV *)(info->start[0]);
|
||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
|
||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
|
||||
base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
|
||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
|
||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
|
||||
*addr = (FPW)0x00300030; /* erase sector */
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer(0);
|
||||
|
||||
/* wait at least 50us for AMD, 80us for Intel.
|
||||
* Let's wait 1 ms.
|
||||
*/
|
||||
udelay (1000);
|
||||
|
||||
while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
|
||||
if (intel) {
|
||||
/* suspend erase */
|
||||
*addr = (FPW)0x00B000B0;
|
||||
}
|
||||
|
||||
flash_reset(info); /* reset to read mode */
|
||||
rcode = 1; /* failed */
|
||||
break;
|
||||
}
|
||||
|
||||
/* show that we're waiting */
|
||||
if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
|
||||
putc ('.');
|
||||
last = get_timer(0);
|
||||
}
|
||||
}
|
||||
|
||||
/* show that we're waiting */
|
||||
if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
|
||||
putc ('.');
|
||||
last = get_timer(0);
|
||||
}
|
||||
|
||||
flash_reset(info); /* reset to read mode */
|
||||
}
|
||||
|
||||
printf (" done\n");
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
|
||||
int bytes; /* number of bytes to program in current word */
|
||||
int left; /* number of bytes left to program */
|
||||
int i, res;
|
||||
|
||||
for (left = cnt, res = 0;
|
||||
left > 0 && res == 0;
|
||||
addr += sizeof(data), left -= sizeof(data) - bytes) {
|
||||
|
||||
bytes = addr & (sizeof(data) - 1);
|
||||
addr &= ~(sizeof(data) - 1);
|
||||
|
||||
/* combine source and destination data so can program
|
||||
* an entire word of 16 or 32 bits
|
||||
*/
|
||||
for (i = 0; i < sizeof(data); i++) {
|
||||
data <<= 8;
|
||||
if (i < bytes || i - bytes >= left )
|
||||
data += *((uchar *)addr + i);
|
||||
else
|
||||
data += *src++;
|
||||
}
|
||||
|
||||
/* write one word to the flash */
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD:
|
||||
res = write_word_amd(info, (FPWV *)addr, data);
|
||||
break;
|
||||
case FLASH_MAN_INTEL:
|
||||
res = write_word_intel(info, (FPWV *)addr, data);
|
||||
break;
|
||||
default:
|
||||
/* unknown flash type, error! */
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
res = 1; /* not really a timeout, but gives error */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for AMD FLASH
|
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
||||
* (not an individual chip) is.
|
||||
*
|
||||
* returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
|
||||
{
|
||||
ulong start;
|
||||
int flag;
|
||||
int res = 0; /* result, assume success */
|
||||
FPWV *base; /* first address in flash bank */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
|
||||
base = (FPWV *)(info->start[0]);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
|
||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
|
||||
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
|
||||
|
||||
*dest = data; /* start programming the data */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer (0);
|
||||
|
||||
/* data polling for D7 */
|
||||
while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
*dest = (FPW)0x00F000F0; /* reset bank */
|
||||
res = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for Intel FLASH
|
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
||||
* (not an individual chip) is.
|
||||
*
|
||||
* returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
|
||||
{
|
||||
ulong start;
|
||||
int flag;
|
||||
int res = 0; /* result, assume success */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
*dest = (FPW)0x00500050; /* clear status register */
|
||||
*dest = (FPW)0x00FF00FF; /* make sure in read mode */
|
||||
*dest = (FPW)0x00400040; /* program setup */
|
||||
|
||||
*dest = data; /* start programming the data */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer (0);
|
||||
|
||||
while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
*dest = (FPW)0x00B000B0; /* Suspend program */
|
||||
res = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (res == 0 && (*dest & (FPW)0x00100010))
|
||||
res = 1; /* write failed, time out error is close enough */
|
||||
|
||||
*dest = (FPW)0x00500050; /* clear status register */
|
||||
*dest = (FPW)0x00FF00FF; /* make sure in read mode */
|
||||
|
||||
return (res);
|
||||
}
|
|
@ -1,110 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/inca-ip.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/reboot.h>
|
||||
|
||||
extern uint incaip_get_cpuclk(void);
|
||||
|
||||
void _machine_restart(void)
|
||||
{
|
||||
*INCA_IP_WDT_RST_REQ = 0x3f;
|
||||
}
|
||||
|
||||
static ulong max_sdram_size(void)
|
||||
{
|
||||
/* The only supported SDRAM data width is 16bit.
|
||||
*/
|
||||
#define CONFIG_SYS_DW 2
|
||||
|
||||
/* The only supported number of SDRAM banks is 4.
|
||||
*/
|
||||
#define CONFIG_SYS_NB 4
|
||||
|
||||
ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
|
||||
int cols = cfgpb0 & 0xF;
|
||||
int rows = (cfgpb0 & 0xF0) >> 4;
|
||||
ulong size = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB;
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
|
||||
ulong size, max_size = 0;
|
||||
ulong our_address;
|
||||
|
||||
asm volatile ("move %0, $25" : "=r" (our_address) :);
|
||||
|
||||
/* Can't probe for RAM size unless we are running from Flash.
|
||||
*/
|
||||
if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
|
||||
{
|
||||
return max_sdram_size();
|
||||
}
|
||||
|
||||
for (cols = 0x8; cols <= 0xC; cols++)
|
||||
{
|
||||
for (rows = 0xB; rows <= 0xD; rows++)
|
||||
{
|
||||
*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
|
||||
(rows << 4) | cols;
|
||||
size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
|
||||
max_sdram_size());
|
||||
|
||||
if (size > max_size)
|
||||
{
|
||||
best_val = *INCA_IP_SDRAM_MC_CFGPB0;
|
||||
max_size = size;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
*INCA_IP_SDRAM_MC_CFGPB0 = best_val;
|
||||
return max_size;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
unsigned long chipid = *INCA_IP_WDT_CHIPID;
|
||||
int part_num;
|
||||
|
||||
puts ("Board: INCA-IP ");
|
||||
part_num = (chipid >> 12) & 0xffff;
|
||||
switch (part_num) {
|
||||
case 0xc0:
|
||||
printf ("Standard Version, ");
|
||||
break;
|
||||
case 0xc1:
|
||||
printf ("Basic Version, ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Part Number 0x%x ", part_num);
|
||||
break;
|
||||
}
|
||||
|
||||
printf ("Chip V1.%ld, ", (chipid >> 28));
|
||||
|
||||
printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
|
||||
|
||||
set_io_port_base(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_INCA_IP_SWITCH)
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return inca_switch_initialize(bis);
|
||||
}
|
||||
#endif
|
|
@ -1,287 +0,0 @@
|
|||
/*
|
||||
* Memory sub-system initialization code for INCA-IP development board.
|
||||
*
|
||||
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
|
||||
#define EBU_MODUL_BASE 0xB8000200
|
||||
#define EBU_CLC(value) 0x0000(value)
|
||||
#define EBU_CON(value) 0x0010(value)
|
||||
#define EBU_ADDSEL0(value) 0x0020(value)
|
||||
#define EBU_ADDSEL1(value) 0x0024(value)
|
||||
#define EBU_ADDSEL2(value) 0x0028(value)
|
||||
#define EBU_BUSCON0(value) 0x0060(value)
|
||||
#define EBU_BUSCON1(value) 0x0064(value)
|
||||
#define EBU_BUSCON2(value) 0x0068(value)
|
||||
|
||||
#define MC_MODUL_BASE 0xBF800000
|
||||
#define MC_ERRCAUSE(value) 0x0100(value)
|
||||
#define MC_ERRADDR(value) 0x0108(value)
|
||||
#define MC_IOGP(value) 0x0800(value)
|
||||
#define MC_SELFRFSH(value) 0x0A00(value)
|
||||
#define MC_CTRLENA(value) 0x1000(value)
|
||||
#define MC_MRSCODE(value) 0x1008(value)
|
||||
#define MC_CFGDW(value) 0x1010(value)
|
||||
#define MC_CFGPB0(value) 0x1018(value)
|
||||
#define MC_LATENCY(value) 0x1038(value)
|
||||
#define MC_TREFRESH(value) 0x1040(value)
|
||||
|
||||
#define CGU_MODUL_BASE 0xBF107000
|
||||
#define CGU_PLL1CR(value) 0x0008(value)
|
||||
#define CGU_DIVCR(value) 0x0010(value)
|
||||
#define CGU_MUXCR(value) 0x0014(value)
|
||||
#define CGU_PLL1SR(value) 0x000C(value)
|
||||
|
||||
.set noreorder
|
||||
|
||||
|
||||
/*
|
||||
* void ebu_init(long)
|
||||
*
|
||||
* a0 has the clock value we are going to run at
|
||||
*/
|
||||
.globl ebu_init
|
||||
.ent ebu_init
|
||||
ebu_init:
|
||||
__ebu_init:
|
||||
|
||||
li t1, EBU_MODUL_BASE
|
||||
li t2, 0xA0000041
|
||||
sw t2, EBU_ADDSEL0(t1)
|
||||
li t2, 0xA0800041
|
||||
sw t2, EBU_ADDSEL2(t1)
|
||||
li t2, 0xBE0000F1
|
||||
sw t2, EBU_ADDSEL1(t1)
|
||||
|
||||
li t3, 100000000
|
||||
beq a0, t3, 1f
|
||||
nop
|
||||
li t3, 133000000
|
||||
beq a0, t3, 2f
|
||||
nop
|
||||
li t3, 150000000
|
||||
beq a0, t3, 2f
|
||||
nop
|
||||
b 3f
|
||||
nop
|
||||
|
||||
/* 100 MHz */
|
||||
1:
|
||||
li t2, 0x8841417D
|
||||
sw t2, EBU_BUSCON0(t1)
|
||||
sw t2, EBU_BUSCON2(t1)
|
||||
li t2, 0x684142BD
|
||||
b 3f
|
||||
sw t2, EBU_BUSCON1(t1) /* delay slot */
|
||||
|
||||
/* 133 or 150 MHz */
|
||||
2:
|
||||
li t2, 0x8841417E
|
||||
sw t2, EBU_BUSCON0(t1)
|
||||
sw t2, EBU_BUSCON2(t1)
|
||||
li t2, 0x684143FD
|
||||
sw t2, EBU_BUSCON1(t1)
|
||||
3:
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.end ebu_init
|
||||
|
||||
|
||||
/*
|
||||
* void cgu_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl cgu_init
|
||||
.ent cgu_init
|
||||
cgu_init:
|
||||
__cgu_init:
|
||||
|
||||
li t1, CGU_MODUL_BASE
|
||||
|
||||
li t3, 100000000
|
||||
beq a0, t3, 1f
|
||||
nop
|
||||
li t3, 133000000
|
||||
beq a0, t3, 2f
|
||||
nop
|
||||
li t3, 150000000
|
||||
beq a0, t3, 3f
|
||||
nop
|
||||
b 5f
|
||||
nop
|
||||
|
||||
/* 100 MHz clock */
|
||||
1:
|
||||
li t2, 0x80000014
|
||||
sw t2, CGU_DIVCR(t1)
|
||||
li t2, 0x80000000
|
||||
sw t2, CGU_MUXCR(t1)
|
||||
li t2, 0x800B0001
|
||||
b 5f
|
||||
sw t2, CGU_PLL1CR(t1) /* delay slot */
|
||||
|
||||
/* 133 MHz clock */
|
||||
2:
|
||||
li t2, 0x80000054
|
||||
sw t2, CGU_DIVCR(t1)
|
||||
li t2, 0x80000000
|
||||
sw t2, CGU_MUXCR(t1)
|
||||
li t2, 0x800B0001
|
||||
b 5f
|
||||
sw t2, CGU_PLL1CR(t1) /* delay slot */
|
||||
|
||||
/* 150 MHz clock */
|
||||
3:
|
||||
li t2, 0x80000017
|
||||
sw t2, CGU_DIVCR(t1)
|
||||
li t2, 0xC00B0001
|
||||
sw t2, CGU_PLL1CR(t1)
|
||||
li t3, 0x80000000
|
||||
4:
|
||||
lw t2, CGU_PLL1SR(t1)
|
||||
and t2, t2, t3
|
||||
beq t2, zero, 4b
|
||||
nop
|
||||
li t2, 0x80000001
|
||||
sw t2, CGU_MUXCR(t1)
|
||||
5:
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.end cgu_init
|
||||
|
||||
|
||||
/*
|
||||
* void sdram_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl sdram_init
|
||||
.ent sdram_init
|
||||
sdram_init:
|
||||
__sdram_init:
|
||||
|
||||
li t1, MC_MODUL_BASE
|
||||
|
||||
#if 0
|
||||
/* Disable memory controller before changing any of its registers */
|
||||
sw zero, MC_CTRLENA(t1)
|
||||
#endif
|
||||
|
||||
li t2, 100000000
|
||||
beq a0, t2, 1f
|
||||
nop
|
||||
li t2, 133000000
|
||||
beq a0, t2, 2f
|
||||
nop
|
||||
li t2, 150000000
|
||||
beq a0, t2, 3f
|
||||
nop
|
||||
b 5f
|
||||
nop
|
||||
|
||||
/* 100 MHz clock */
|
||||
1:
|
||||
/* Set clock ratio (clkrat=1:1, rddel=3) */
|
||||
li t2, 0x00000003
|
||||
sw t2, MC_IOGP(t1)
|
||||
|
||||
/* Set sdram refresh rate (4K/64ms @ 100MHz) */
|
||||
li t2, 0x0000061A
|
||||
b 4f
|
||||
sw t2, MC_TREFRESH(t1)
|
||||
|
||||
/* 133 MHz clock */
|
||||
2:
|
||||
/* Set clock ratio (clkrat=1:1, rddel=3) */
|
||||
li t2, 0x00000003
|
||||
sw t2, MC_IOGP(t1)
|
||||
|
||||
/* Set sdram refresh rate (4K/64ms @ 133MHz) */
|
||||
li t2, 0x00000822
|
||||
b 4f
|
||||
sw t2, MC_TREFRESH(t1)
|
||||
|
||||
/* 150 MHz clock */
|
||||
3:
|
||||
/* Set clock ratio (clkrat=3:2, rddel=4) */
|
||||
li t2, 0x00000014
|
||||
sw t2, MC_IOGP(t1)
|
||||
|
||||
/* Set sdram refresh rate (4K/64ms @ 150MHz) */
|
||||
li t2, 0x00000927
|
||||
sw t2, MC_TREFRESH(t1)
|
||||
|
||||
4:
|
||||
/* Clear Error log registers */
|
||||
sw zero, MC_ERRCAUSE(t1)
|
||||
sw zero, MC_ERRADDR(t1)
|
||||
|
||||
/* Clear Power-down registers */
|
||||
sw zero, MC_SELFRFSH(t1)
|
||||
|
||||
/* Set CAS Latency */
|
||||
li t2, 0x00000020 /* CL = 2 */
|
||||
sw t2, MC_MRSCODE(t1)
|
||||
|
||||
/* Set word width to 16 bit */
|
||||
li t2, 0x2
|
||||
sw t2, MC_CFGDW(t1)
|
||||
|
||||
/* Set CS0 to SDRAM parameters */
|
||||
li t2, 0x000014C9
|
||||
sw t2, MC_CFGPB0(t1)
|
||||
|
||||
/* Set SDRAM latency parameters */
|
||||
li t2, 0x00026325 /* BC PC100 */
|
||||
sw t2, MC_LATENCY(t1)
|
||||
|
||||
5:
|
||||
/* Finally enable the controller */
|
||||
li t2, 0x00000001
|
||||
sw t2, MC_CTRLENA(t1)
|
||||
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.end sdram_init
|
||||
|
||||
|
||||
.globl lowlevel_init
|
||||
.ent lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
/* Disable Watchdog.
|
||||
*/
|
||||
la t9, disable_incaip_wdt
|
||||
jalr t9
|
||||
nop
|
||||
|
||||
/* EBU, CGU and SDRAM Initialization.
|
||||
*/
|
||||
li a0, CONFIG_CPU_CLOCK_RATE
|
||||
move t0, ra
|
||||
|
||||
/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
|
||||
* modify t0 and a0.
|
||||
*/
|
||||
bal __cgu_init
|
||||
nop
|
||||
bal __ebu_init
|
||||
nop
|
||||
bal __sdram_init
|
||||
nop
|
||||
move ra, t0
|
||||
|
||||
jr ra
|
||||
nop
|
||||
|
||||
.end lowlevel_init
|
|
@ -519,10 +519,6 @@ Active mips mips32 au1x00 - dbau1x00
|
|||
Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
|
||||
Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
|
||||
Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
|
||||
Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
|
||||
Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
|
||||
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
|
||||
|
|
|
@ -125,3 +125,4 @@ MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwar
|
|||
adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi <adrian.filipi@eurotech.com>
|
||||
R5200 ColdFire - 48ead7a 2008-03-31 Zachary P. Landau <zachary.landau@labxtechnologies.com>
|
||||
CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
|
||||
incaip mips mips32 - 2014-04-17 Wolfgang Denk <wd@denx.de>
|
||||
|
|
|
@ -29,7 +29,6 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o
|
|||
obj-$(CONFIG_FTMAC110) += ftmac110.o
|
||||
obj-$(CONFIG_FTMAC100) += ftmac100.o
|
||||
obj-$(CONFIG_GRETH) += greth.o
|
||||
obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
|
||||
obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
|
||||
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
|
||||
obj-$(CONFIG_LAN91C96) += lan91c96.o
|
||||
|
|
|
@ -1,793 +0,0 @@
|
|||
/*
|
||||
* INCA-IP internal switch ethernet driver.
|
||||
*
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <malloc.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/inca-ip.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
|
||||
#define NUM_RX_DESC PKTBUFSRX
|
||||
#define NUM_TX_DESC 3
|
||||
#define TOUT_LOOP 1000000
|
||||
|
||||
|
||||
#define DELAY udelay(10000)
|
||||
/* Sometimes the store word instruction hangs while writing to one
|
||||
* of the Switch registers. Moving the instruction into a separate
|
||||
* function somehow makes the problem go away.
|
||||
*/
|
||||
static void SWORD(volatile u32 * reg, u32 value)
|
||||
{
|
||||
*reg = value;
|
||||
}
|
||||
|
||||
#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
|
||||
#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
|
||||
#define SW_WRITE_REG(reg, value) \
|
||||
SWORD(reg, value);\
|
||||
DELAY;\
|
||||
SWORD(reg, value);
|
||||
|
||||
#define SW_READ_REG(reg, value) \
|
||||
value = (u32)*((volatile u32*)reg);\
|
||||
DELAY;\
|
||||
value = (u32)*((volatile u32*)reg);
|
||||
|
||||
#define INCA_DMA_TX_POLLING_TIME 0x07
|
||||
#define INCA_DMA_RX_POLLING_TIME 0x07
|
||||
|
||||
#define INCA_DMA_TX_HOLD 0x80000000
|
||||
#define INCA_DMA_TX_EOP 0x40000000
|
||||
#define INCA_DMA_TX_SOP 0x20000000
|
||||
#define INCA_DMA_TX_ICPT 0x10000000
|
||||
#define INCA_DMA_TX_IEOP 0x08000000
|
||||
|
||||
#define INCA_DMA_RX_C 0x80000000
|
||||
#define INCA_DMA_RX_SOP 0x40000000
|
||||
#define INCA_DMA_RX_EOP 0x20000000
|
||||
|
||||
#define INCA_SWITCH_PHY_SPEED_10H 0x1
|
||||
#define INCA_SWITCH_PHY_SPEED_10F 0x5
|
||||
#define INCA_SWITCH_PHY_SPEED_100H 0x2
|
||||
#define INCA_SWITCH_PHY_SPEED_100F 0x6
|
||||
|
||||
/************************ Auto MDIX settings ************************/
|
||||
#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
|
||||
#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
|
||||
#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
|
||||
#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
|
||||
|
||||
#define WAIT_SIGNAL_RETRIES 100
|
||||
#define WAIT_LINK_RETRIES 100
|
||||
#define LINK_RETRY_DELAY 2000 /* ms */
|
||||
/********************************************************************/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
struct {
|
||||
volatile u32 HOLD :1;
|
||||
volatile u32 ICpt :1;
|
||||
volatile u32 IEop :1;
|
||||
volatile u32 offset :3;
|
||||
volatile u32 reserved0 :4;
|
||||
volatile u32 NFB :22;
|
||||
}field;
|
||||
|
||||
volatile u32 word;
|
||||
}params;
|
||||
|
||||
volatile u32 nextRxDescPtr;
|
||||
|
||||
volatile u32 RxDataPtr;
|
||||
|
||||
union {
|
||||
struct {
|
||||
volatile u32 C :1;
|
||||
volatile u32 Sop :1;
|
||||
volatile u32 Eop :1;
|
||||
volatile u32 reserved3 :12;
|
||||
volatile u32 NBT :17;
|
||||
}field;
|
||||
|
||||
volatile u32 word;
|
||||
}status;
|
||||
|
||||
} inca_rx_descriptor_t;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
struct {
|
||||
volatile u32 HOLD :1;
|
||||
volatile u32 Eop :1;
|
||||
volatile u32 Sop :1;
|
||||
volatile u32 ICpt :1;
|
||||
volatile u32 IEop :1;
|
||||
volatile u32 reserved0 :5;
|
||||
volatile u32 NBA :22;
|
||||
}field;
|
||||
|
||||
volatile u32 word;
|
||||
}params;
|
||||
|
||||
volatile u32 nextTxDescPtr;
|
||||
|
||||
volatile u32 TxDataPtr;
|
||||
|
||||
volatile u32 C :1;
|
||||
volatile u32 reserved3 :31;
|
||||
|
||||
} inca_tx_descriptor_t;
|
||||
|
||||
|
||||
static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
|
||||
static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
|
||||
|
||||
static int tx_new, rx_new, tx_hold, rx_hold;
|
||||
static int tx_old_hold = -1;
|
||||
static int initialized = 0;
|
||||
|
||||
|
||||
static int inca_switch_init(struct eth_device *dev, bd_t * bis);
|
||||
static int inca_switch_send(struct eth_device *dev, void *packet, int length);
|
||||
static int inca_switch_recv(struct eth_device *dev);
|
||||
static void inca_switch_halt(struct eth_device *dev);
|
||||
static void inca_init_switch_chip(void);
|
||||
static void inca_dma_init(void);
|
||||
static int inca_amdix(void);
|
||||
|
||||
|
||||
int inca_switch_initialize(bd_t * bis)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
|
||||
#if 0
|
||||
printf("Entered inca_switch_initialize()\n");
|
||||
#endif
|
||||
|
||||
if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
|
||||
printf("Failed to allocate memory\n");
|
||||
return 0;
|
||||
}
|
||||
memset(dev, 0, sizeof(*dev));
|
||||
|
||||
inca_dma_init();
|
||||
|
||||
inca_init_switch_chip();
|
||||
|
||||
#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
|
||||
inca_amdix();
|
||||
#endif
|
||||
|
||||
sprintf(dev->name, "INCA-IP Switch");
|
||||
dev->init = inca_switch_init;
|
||||
dev->halt = inca_switch_halt;
|
||||
dev->send = inca_switch_send;
|
||||
dev->recv = inca_switch_recv;
|
||||
|
||||
eth_register(dev);
|
||||
|
||||
#if 0
|
||||
printf("Leaving inca_switch_initialize()\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int inca_switch_init(struct eth_device *dev, bd_t * bis)
|
||||
{
|
||||
int i;
|
||||
u32 v, regValue;
|
||||
u16 wTmp;
|
||||
|
||||
#if 0
|
||||
printf("Entering inca_switch_init()\n");
|
||||
#endif
|
||||
|
||||
/* Set MAC address.
|
||||
*/
|
||||
wTmp = (u16)dev->enetaddr[0];
|
||||
regValue = (wTmp << 8) | dev->enetaddr[1];
|
||||
|
||||
SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
|
||||
|
||||
wTmp = (u16)dev->enetaddr[2];
|
||||
regValue = (wTmp << 8) | dev->enetaddr[3];
|
||||
regValue = regValue << 16;
|
||||
wTmp = (u16)dev->enetaddr[4];
|
||||
regValue |= (wTmp<<8) | dev->enetaddr[5];
|
||||
|
||||
SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
|
||||
|
||||
/* Initialize the descriptor rings.
|
||||
*/
|
||||
for (i = 0; i < NUM_RX_DESC; i++) {
|
||||
inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
|
||||
memset(rx_desc, 0, sizeof(rx_ring[i]));
|
||||
|
||||
/* Set maximum size of receive buffer.
|
||||
*/
|
||||
rx_desc->params.field.NFB = PKTSIZE_ALIGN;
|
||||
|
||||
/* Set the offset of the receive buffer. Zero means
|
||||
* that the offset mechanism is not used.
|
||||
*/
|
||||
rx_desc->params.field.offset = 0;
|
||||
|
||||
/* Check if it is the last descriptor.
|
||||
*/
|
||||
if (i == (NUM_RX_DESC - 1)) {
|
||||
/* Let the last descriptor point to the first
|
||||
* one.
|
||||
*/
|
||||
rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
|
||||
} else {
|
||||
/* Set the address of the next descriptor.
|
||||
*/
|
||||
rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
|
||||
}
|
||||
|
||||
rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
|
||||
}
|
||||
|
||||
#if 0
|
||||
printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
|
||||
printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
|
||||
#endif
|
||||
|
||||
for (i = 0; i < NUM_TX_DESC; i++) {
|
||||
inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
|
||||
|
||||
memset(tx_desc, 0, sizeof(tx_ring[i]));
|
||||
|
||||
tx_desc->params.word = 0;
|
||||
tx_desc->params.field.HOLD = 1;
|
||||
tx_desc->C = 1;
|
||||
|
||||
/* Check if it is the last descriptor.
|
||||
*/
|
||||
if (i == (NUM_TX_DESC - 1)) {
|
||||
/* Let the last descriptor point to the
|
||||
* first one.
|
||||
*/
|
||||
tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
|
||||
} else {
|
||||
/* Set the address of the next descriptor.
|
||||
*/
|
||||
tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize RxDMA.
|
||||
*/
|
||||
DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
|
||||
debug("RX status = 0x%08X\n", v);
|
||||
|
||||
/* Writing to the FRDA of CHANNEL.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
|
||||
|
||||
/* Writing to the COMMAND REG.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
|
||||
|
||||
/* Initialize TxDMA.
|
||||
*/
|
||||
DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
|
||||
debug("TX status = 0x%08X\n", v);
|
||||
|
||||
/* Writing to the FRDA of CHANNEL.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
|
||||
|
||||
tx_new = rx_new = 0;
|
||||
|
||||
tx_hold = NUM_TX_DESC - 1;
|
||||
rx_hold = NUM_RX_DESC - 1;
|
||||
|
||||
#if 0
|
||||
rx_ring[rx_hold].params.field.HOLD = 1;
|
||||
#endif
|
||||
/* enable spanning tree forwarding, enable the CPU port */
|
||||
/* ST_PT:
|
||||
* CPS (CPU port status) 0x3 (forwarding)
|
||||
* LPS (LAN port status) 0x3 (forwarding)
|
||||
* PPS (PC port status) 0x3 (forwarding)
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
|
||||
|
||||
#if 0
|
||||
printf("Leaving inca_switch_init()\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int inca_switch_send(struct eth_device *dev, void *packet, int length)
|
||||
{
|
||||
int i;
|
||||
int res = -1;
|
||||
u32 command;
|
||||
u32 regValue;
|
||||
inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
|
||||
|
||||
#if 0
|
||||
printf("Entered inca_switch_send()\n");
|
||||
#endif
|
||||
|
||||
if (length <= 0) {
|
||||
printf ("%s: bad packet size: %d\n", dev->name, length);
|
||||
goto Done;
|
||||
}
|
||||
|
||||
for(i = 0; tx_desc->C == 0; i++) {
|
||||
if (i >= TOUT_LOOP) {
|
||||
printf("%s: tx error buffer not ready\n", dev->name);
|
||||
goto Done;
|
||||
}
|
||||
}
|
||||
|
||||
if (tx_old_hold >= 0) {
|
||||
((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
|
||||
}
|
||||
tx_old_hold = tx_hold;
|
||||
|
||||
tx_desc->params.word =
|
||||
(INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
|
||||
|
||||
tx_desc->C = 0;
|
||||
tx_desc->TxDataPtr = (u32)packet;
|
||||
tx_desc->params.field.NBA = length;
|
||||
|
||||
((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
|
||||
|
||||
tx_hold = tx_new;
|
||||
tx_new = (tx_new + 1) % NUM_TX_DESC;
|
||||
|
||||
|
||||
if (! initialized) {
|
||||
command = INCA_IP_DMA_DMA_TXCCR0_INIT;
|
||||
initialized = 1;
|
||||
} else {
|
||||
command = INCA_IP_DMA_DMA_TXCCR0_HR;
|
||||
}
|
||||
|
||||
DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
|
||||
regValue |= command;
|
||||
#if 0
|
||||
printf("regValue = 0x%x\n", regValue);
|
||||
#endif
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
|
||||
|
||||
#if 1
|
||||
for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
|
||||
if (i >= TOUT_LOOP) {
|
||||
printf("%s: tx buffer not ready\n", dev->name);
|
||||
goto Done;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
res = length;
|
||||
Done:
|
||||
#if 0
|
||||
printf("Leaving inca_switch_send()\n");
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
|
||||
static int inca_switch_recv(struct eth_device *dev)
|
||||
{
|
||||
int length = 0;
|
||||
inca_rx_descriptor_t * rx_desc;
|
||||
|
||||
#if 0
|
||||
printf("Entered inca_switch_recv()\n");
|
||||
#endif
|
||||
|
||||
for (;;) {
|
||||
rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
|
||||
|
||||
if (rx_desc->status.field.C == 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
#if 0
|
||||
rx_ring[rx_new].params.field.HOLD = 1;
|
||||
#endif
|
||||
|
||||
if (! rx_desc->status.field.Eop) {
|
||||
printf("Partly received packet!!!\n");
|
||||
break;
|
||||
}
|
||||
|
||||
length = rx_desc->status.field.NBT;
|
||||
rx_desc->status.word &=
|
||||
~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
|
||||
#if 0
|
||||
{
|
||||
int i;
|
||||
for (i=0;i<length - 4;i++) {
|
||||
if (i % 16 == 0) printf("\n%04x: ", i);
|
||||
printf("%02X ", NetRxPackets[rx_new][i]);
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
if (length) {
|
||||
#if 0
|
||||
printf("Received %d bytes\n", length);
|
||||
#endif
|
||||
NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
|
||||
} else {
|
||||
#if 1
|
||||
printf("Zero length!!!\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
|
||||
|
||||
rx_hold = rx_new;
|
||||
|
||||
rx_new = (rx_new + 1) % NUM_RX_DESC;
|
||||
}
|
||||
|
||||
#if 0
|
||||
printf("Leaving inca_switch_recv()\n");
|
||||
#endif
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
|
||||
static void inca_switch_halt(struct eth_device *dev)
|
||||
{
|
||||
#if 0
|
||||
printf("Entered inca_switch_halt()\n");
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
initialized = 0;
|
||||
#endif
|
||||
#if 1
|
||||
/* Disable forwarding to the CPU port.
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
|
||||
|
||||
/* Close RxDMA channel.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
|
||||
|
||||
/* Close TxDMA channel.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
|
||||
|
||||
|
||||
#endif
|
||||
#if 0
|
||||
printf("Leaving inca_switch_halt()\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void inca_init_switch_chip(void)
|
||||
{
|
||||
u32 regValue;
|
||||
|
||||
/* To workaround a problem with collision counter
|
||||
* (see Errata sheet).
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
|
||||
SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
|
||||
|
||||
#if 1
|
||||
/* init MDIO configuration:
|
||||
* MDS (Poll speed): 0x01 (4ms)
|
||||
* PHY_LAN_ADDR: 0x06
|
||||
* PHY_PC_ADDR: 0x05
|
||||
* UEP (Use External PHY): 0x00 (Internal PHY is used)
|
||||
* PS (Port Select): 0x00 (PT/UMM for LAN)
|
||||
* PT (PHY Test): 0x00 (no test mode)
|
||||
* UMM (Use MDIO Mode): 0x00 (state machine is disabled)
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
|
||||
|
||||
/* init PHY:
|
||||
* SL (Auto Neg. Speed for LAN)
|
||||
* SP (Auto Neg. Speed for PC)
|
||||
* LL (Link Status for LAN)
|
||||
* LP (Link Status for PC)
|
||||
* DL (Duplex Status for LAN)
|
||||
* DP (Duplex Status for PC)
|
||||
* PL (Auto Neg. Pause Status for LAN)
|
||||
* PP (Auto Neg. Pause Status for PC)
|
||||
*/
|
||||
SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
|
||||
|
||||
/* MDIO_ACC:
|
||||
* RA (Request/Ack) 0x01 (Request)
|
||||
* RW (Read/Write) 0x01 (Write)
|
||||
* PHY_ADDR 0x05 (PC)
|
||||
* REG_ADDR 0x00 (PHY_BCR: basic control register)
|
||||
* PHY_DATA 0x8000
|
||||
* Reset - software reset
|
||||
* LB (loop back) - normal
|
||||
* SS (speed select) - 10 Mbit/s
|
||||
* ANE (auto neg. enable) - enable
|
||||
* PD (power down) - normal
|
||||
* ISO (isolate) - normal
|
||||
* RAN (restart auto neg.) - normal
|
||||
* DM (duplex mode) - half duplex
|
||||
* CT (collision test) - enable
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
|
||||
|
||||
/* MDIO_ACC:
|
||||
* RA (Request/Ack) 0x01 (Request)
|
||||
* RW (Read/Write) 0x01 (Write)
|
||||
* PHY_ADDR 0x06 (LAN)
|
||||
* REG_ADDR 0x00 (PHY_BCR: basic control register)
|
||||
* PHY_DATA 0x8000
|
||||
* Reset - software reset
|
||||
* LB (loop back) - normal
|
||||
* SS (speed select) - 10 Mbit/s
|
||||
* ANE (auto neg. enable) - enable
|
||||
* PD (power down) - normal
|
||||
* ISO (isolate) - normal
|
||||
* RAN (restart auto neg.) - normal
|
||||
* DM (duplex mode) - half duplex
|
||||
* CT (collision test) - enable
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
|
||||
|
||||
#endif
|
||||
|
||||
/* Make sure the CPU port is disabled for now. We
|
||||
* don't want packets to get stacked for us until
|
||||
* we enable DMA and are prepared to receive them.
|
||||
*/
|
||||
SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
|
||||
|
||||
SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
|
||||
|
||||
/* CRC GEN is enabled.
|
||||
*/
|
||||
regValue |= 0x00000200;
|
||||
SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
|
||||
|
||||
/* ADD TAG is disabled.
|
||||
*/
|
||||
SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
|
||||
regValue &= ~0x00000002;
|
||||
SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
|
||||
}
|
||||
|
||||
|
||||
static void inca_dma_init(void)
|
||||
{
|
||||
/* Switch off all DMA channels.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
|
||||
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
|
||||
|
||||
/* Setup TX channel polling time.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
|
||||
|
||||
/* Setup RX channel polling time.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
|
||||
|
||||
/* ERRATA: write reset value into the DMA RX IMR register.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
|
||||
|
||||
/* Just in case: disable all transmit interrupts also.
|
||||
*/
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
|
||||
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
|
||||
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
|
||||
static int inca_amdix(void)
|
||||
{
|
||||
u32 phyReg1 = 0;
|
||||
u32 phyReg4 = 0;
|
||||
u32 phyReg5 = 0;
|
||||
u32 phyReg6 = 0;
|
||||
u32 phyReg31 = 0;
|
||||
u32 regEphy = 0;
|
||||
int mdi_flag;
|
||||
int retries;
|
||||
|
||||
/* Setup GPIO pins.
|
||||
*/
|
||||
*INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
||||
*INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
||||
|
||||
#if 0
|
||||
/* Wait for signal.
|
||||
*/
|
||||
retries = WAIT_SIGNAL_RETRIES;
|
||||
while (--retries) {
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
||||
(0x1 << 31) | /* RA */
|
||||
(0x0 << 30) | /* Read */
|
||||
(0x6 << 21) | /* LAN */
|
||||
(17 << 16)); /* PHY_MCSR */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
|
||||
} while (phyReg1 & (1 << 31));
|
||||
|
||||
if (phyReg1 & (1 << 1)) {
|
||||
/* Signal detected */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!retries)
|
||||
goto Fail;
|
||||
#endif
|
||||
|
||||
/* Set MDI mode.
|
||||
*/
|
||||
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
||||
mdi_flag = 1;
|
||||
|
||||
/* Wait for link.
|
||||
*/
|
||||
retries = WAIT_LINK_RETRIES;
|
||||
while (--retries) {
|
||||
udelay(LINK_RETRY_DELAY * 1000);
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
||||
(0x1 << 31) | /* RA */
|
||||
(0x0 << 30) | /* Read */
|
||||
(0x6 << 21) | /* LAN */
|
||||
(1 << 16)); /* PHY_BSR */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
|
||||
} while (phyReg1 & (1 << 31));
|
||||
|
||||
if (phyReg1 & (1 << 2)) {
|
||||
/* Link is up */
|
||||
break;
|
||||
} else if (mdi_flag) {
|
||||
/* Set MDIX mode */
|
||||
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
||||
mdi_flag = 0;
|
||||
} else {
|
||||
/* Set MDI mode */
|
||||
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
|
||||
mdi_flag = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (!retries) {
|
||||
goto Fail;
|
||||
} else {
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
||||
(0x1 << 31) | /* RA */
|
||||
(0x0 << 30) | /* Read */
|
||||
(0x6 << 21) | /* LAN */
|
||||
(1 << 16)); /* PHY_BSR */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
|
||||
} while (phyReg1 & (1 << 31));
|
||||
|
||||
/* Auto-negotiation / Parallel detection complete
|
||||
*/
|
||||
if (phyReg1 & (1 << 5)) {
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
||||
(0x1 << 31) | /* RA */
|
||||
(0x0 << 30) | /* Read */
|
||||
(0x6 << 21) | /* LAN */
|
||||
(31 << 16)); /* PHY_SCSR */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
|
||||
} while (phyReg31 & (1 << 31));
|
||||
|
||||
switch ((phyReg31 >> 2) & 0x7) {
|
||||
case INCA_SWITCH_PHY_SPEED_10H:
|
||||
/* 10Base-T Half-duplex */
|
||||
regEphy = 0;
|
||||
break;
|
||||
case INCA_SWITCH_PHY_SPEED_10F:
|
||||
/* 10Base-T Full-duplex */
|
||||
regEphy = INCA_IP_Switch_EPHY_DL;
|
||||
break;
|
||||
case INCA_SWITCH_PHY_SPEED_100H:
|
||||
/* 100Base-TX Half-duplex */
|
||||
regEphy = INCA_IP_Switch_EPHY_SL;
|
||||
break;
|
||||
case INCA_SWITCH_PHY_SPEED_100F:
|
||||
/* 100Base-TX Full-duplex */
|
||||
regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* In case of Auto-negotiation,
|
||||
* update the negotiated PAUSE support status
|
||||
*/
|
||||
if (phyReg1 & (1 << 3)) {
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
||||
(0x1 << 31) | /* RA */
|
||||
(0x0 << 30) | /* Read */
|
||||
(0x6 << 21) | /* LAN */
|
||||
(6 << 16)); /* MII_EXPANSION */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
|
||||
} while (phyReg6 & (1 << 31));
|
||||
|
||||
/* We are Autoneg-able.
|
||||
* Is Link partner also able to autoneg?
|
||||
*/
|
||||
if (phyReg6 & (1 << 0)) {
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
||||
(0x1 << 31) | /* RA */
|
||||
(0x0 << 30) | /* Read */
|
||||
(0x6 << 21) | /* LAN */
|
||||
(4 << 16)); /* MII_ADVERTISE */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
|
||||
} while (phyReg4 & (1 << 31));
|
||||
|
||||
/* We advertise PAUSE capab.
|
||||
* Does link partner also advertise it?
|
||||
*/
|
||||
if (phyReg4 & (1 << 10)) {
|
||||
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
|
||||
(0x1 << 31) | /* RA */
|
||||
(0x0 << 30) | /* Read */
|
||||
(0x6 << 21) | /* LAN */
|
||||
(5 << 16)); /* MII_LPA */
|
||||
do {
|
||||
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
|
||||
} while (phyReg5 & (1 << 31));
|
||||
|
||||
/* Link partner is PAUSE capab.
|
||||
*/
|
||||
if (phyReg5 & (1 << 10)) {
|
||||
regEphy |= INCA_IP_Switch_EPHY_PL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Link is up */
|
||||
regEphy |= INCA_IP_Switch_EPHY_LL;
|
||||
|
||||
SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
Fail:
|
||||
printf("No Link on LAN port\n");
|
||||
return -1;
|
||||
}
|
||||
#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */
|
|
@ -681,9 +681,6 @@ ulong get_UCLK (void);
|
|||
#if defined(CONFIG_LH7A40X)
|
||||
ulong get_PLLCLK (void);
|
||||
#endif
|
||||
#if defined CONFIG_INCA_IP
|
||||
uint incaip_get_cpuclk (void);
|
||||
#endif
|
||||
#if defined(CONFIG_IMX)
|
||||
ulong get_systemPLLCLK(void);
|
||||
ulong get_FCLK(void);
|
||||
|
|
|
@ -1,177 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the INCA-IP board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
|
||||
|
||||
#define CONFIG_XWAY_SWAP_BYTES
|
||||
|
||||
/*
|
||||
* Clock for the MIPS core (MHz)
|
||||
* allowed values: 100000000, 133000000, and 150000000 (default)
|
||||
*/
|
||||
#ifndef CONFIG_CPU_CLOCK_RATE
|
||||
#define CONFIG_CPU_CLOCK_RATE 150000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} " \
|
||||
"console=ttyS0,${baudrate} " \
|
||||
"ethaddr=${ethaddr} " \
|
||||
"panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 80500000 ${bootfile};" \
|
||||
"run nfsargs addip addmisc;bootm\0" \
|
||||
"rootpath=/opt/eldk/mips_4KC\0" \
|
||||
"bootfile=/tftpboot/INCA/uImage\0" \
|
||||
"kernel_addr=B0040000\0" \
|
||||
"ramdisk_addr=B0100000\0" \
|
||||
"u-boot=/tftpboot/INCA/u-boot.bin\0" \
|
||||
"load=tftp 80500000 ${u-boot}\0" \
|
||||
"update=protect off 1:0-2;era 1:0-2;" \
|
||||
"cp.b 80500000 B0000000 ${filesize}\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "INCA-IP # " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN 128*1024
|
||||
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
|
||||
|
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80100000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x80800000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */
|
||||
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
/* Address and size of Primary Environment Sector */
|
||||
#define CONFIG_ENV_ADDR 0xB0030000
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
|
||||
#define CONFIG_FLASH_16BIT
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
#define CONFIG_INCA_IP_SWITCH
|
||||
#define CONFIG_INCA_IP_SWITCH_AMDIX
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*/
|
||||
/* No command line, one static partition, use all space on the device */
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor1"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
|
||||
/* mtdparts command line support */
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=INCA-IP Bank 0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=INCA-IP Bank 0:192k(uboot)," \
|
||||
"64k(env)," \
|
||||
"768k(linux)," \
|
||||
"1m@3m(rootfs)," \
|
||||
"768k(linux2)," \
|
||||
"3m@5m(rootfs2)"
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_SIZE 4096
|
||||
#define CONFIG_SYS_ICACHE_SIZE 4096
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -54,7 +54,6 @@ int ftmac100_initialize(bd_t *bits);
|
|||
int ftmac110_initialize(bd_t *bits);
|
||||
int greth_initialize(bd_t *bis);
|
||||
void gt6426x_eth_initialize(bd_t *bis);
|
||||
int inca_switch_initialize(bd_t *bis);
|
||||
int ks8695_eth_initialize(void);
|
||||
int ks8851_mll_initialize(u8 dev_num, int base_addr);
|
||||
int lan91c96_initialize(u8 dev_num, int base_addr);
|
||||
|
|
Loading…
Reference in a new issue