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MIPS: Move cache sizes to Kconfig

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Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Paul Burton 2016-05-27 14:28:04 +01:00 committed by Daniel Schwierzeck
parent 83b0face8c
commit ace3be4f15
18 changed files with 95 additions and 53 deletions
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28
arch/mips/Kconfig
View file

@ -246,6 +246,34 @@ config SWAP_IO_SPACE
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
config SYS_DCACHE_SIZE
int
default 0
help
The total size of the L1 Dcache, if known at compile time.
config SYS_ICACHE_SIZE
int
default 0
help
The total size of the L1 ICache, if known at compile time.
config SYS_CACHELINE_SIZE
int
default 0
help
The size of L1 cache lines, if known at compile time.
config SYS_CACHE_SIZE_AUTO
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
SYS_CACHELINE_SIZE = 0
help
Select this (or let it be auto-selected by not defining any cache
sizes) in order to allow U-Boot to automatically detect the sizes
of caches at runtime. This has a small cost in code size & runtime
so if you know the cache configuration for your system at compile
time it would be beneficial to configure it.
config MIPS_L1_CACHE_SHIFT_4
bool

2
arch/mips/lib/cache.c
View file

@ -9,7 +9,7 @@
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#ifdef CONFIG_SYS_CACHELINE_SIZE
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
static inline unsigned long icache_line_size(void)
{

6
arch/mips/lib/cache_init.S
View file

@ -99,14 +99,14 @@
*
*/
LEAF(mips_cache_reset)
#ifdef CONFIG_SYS_ICACHE_SIZE
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
#else
l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
#ifdef CONFIG_SYS_DCACHE_SIZE
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE
#else
@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Determine the largest L1 cache size */
#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
li v0, CONFIG_SYS_ICACHE_SIZE
#else

9
board/dbau1x00/Kconfig
View file

@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0xbfc00000
config SYS_DCACHE_SIZE
default 16384
config SYS_ICACHE_SIZE
default 16384
config SYS_CACHELINE_SIZE
default 32
menu "dbau1x00 board options"
choice

9
board/micronas/vct/Kconfig
View file

@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x87000000
config SYS_DCACHE_SIZE
default 16384
config SYS_ICACHE_SIZE
default 16384
config SYS_CACHELINE_SIZE
default 32
menu "vct board options"
choice

9
board/pb1x00/Kconfig
View file

@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x83800000
config SYS_DCACHE_SIZE
default 16384
config SYS_ICACHE_SIZE
default 16384
config SYS_CACHELINE_SIZE
default 32
endif

9
board/qca/ap121/Kconfig
View file

@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x9f000000
config SYS_DCACHE_SIZE
default 32768
config SYS_ICACHE_SIZE
default 65536
config SYS_CACHELINE_SIZE
default 32
endif

9
board/qca/ap143/Kconfig
View file

@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x9f000000
config SYS_DCACHE_SIZE
default 32768
config SYS_ICACHE_SIZE
default 65536
config SYS_CACHELINE_SIZE
default 32
endif

9
board/qemu-mips/Kconfig
View file

@ -11,4 +11,13 @@ config SYS_TEXT_BASE
default 0xbfc00000 if 32BIT
default 0xffffffffbfc00000 if 64BIT
config SYS_DCACHE_SIZE
default 16384
config SYS_ICACHE_SIZE
default 16384
config SYS_CACHELINE_SIZE
default 32
endif

9
board/tplink/wdr4300/Kconfig
View file

@ -15,4 +15,13 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0xa1000000
config SYS_DCACHE_SIZE
default 32768
config SYS_ICACHE_SIZE
default 65536
config SYS_CACHELINE_SIZE
default 32
endif

5
include/configs/ap121.h
View file

@ -15,11 +15,6 @@
#define CONFIG_SYS_MHZ 200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE 0x8000
#define CONFIG_SYS_ICACHE_SIZE 0x10000
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000

5
include/configs/ap143.h
View file

@ -15,11 +15,6 @@
#define CONFIG_SYS_MHZ 325
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE 0x8000
#define CONFIG_SYS_ICACHE_SIZE 0x10000
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000

7
include/configs/dbau1x00.h
View file

@ -202,11 +202,4 @@
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
#endif /* CONFIG_DBAU1550 */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif /* __CONFIG_H */

6
include/configs/pb1x00.h
View file

@ -144,12 +144,6 @@
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* BOOTP options

7
include/configs/qemu-mips.h
View file

@ -132,11 +132,4 @@
#define CONFIG_LZMA
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif /* __CONFIG_H */

7
include/configs/qemu-mips64.h
View file

@ -132,11 +132,4 @@
#define CONFIG_LZMA
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif /* __CONFIG_H */

5
include/configs/tplink_wdr4300.h
View file

@ -15,11 +15,6 @@
#define CONFIG_SYS_MHZ 280
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE 0x8000
#define CONFIG_SYS_ICACHE_SIZE 0x10000
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000

7
include/configs/vct.h
View file

@ -203,13 +203,6 @@
#define CONFIG_ENV_SIZE (128 << 10) /* erase size */
#endif /* CONFIG_VCT_ONENAND */
/*
* Cache Configuration
*/
#define CONFIG_SYS_DCACHE_SIZE 16384
#define CONFIG_SYS_ICACHE_SIZE 16384
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* I2C/EEPROM
*/