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https://github.com/AsahiLinux/u-boot
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MIPS: add handling for generic and EJTAG exceptions
Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Daniel Schwierzeck
parent
bd60252811
commit
6c59363004
5 changed files with 344 additions and 0 deletions
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@ -262,4 +262,12 @@ extern void __die_if_kernel(const char *, struct pt_regs *, const char *where,
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#define die_if_kernel(msg, regs) \
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__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
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static inline void execution_hazard_barrier(void)
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{
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__asm__ __volatile__(
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".set noreorder\n"
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"ehb\n"
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".set reorder");
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}
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#endif /* _ASM_SYSTEM_H */
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@ -5,4 +5,8 @@
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#ifndef _U_BOOT_MIPS_H_
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#define _U_BOOT_MIPS_H_
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void exc_handler(void);
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void except_vec3_generic(void);
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void except_vec_ejtag_debug(void);
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#endif /* _U_BOOT_MIPS_H_ */
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@ -7,7 +7,9 @@
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obj-y += cache.o
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obj-y += cache_init.o
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obj-y += genex.o
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obj-y += stack.o
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obj-y += traps.o
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obj-$(CONFIG_CMD_BOOTM) += bootm.o
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224
arch/mips/lib/genex.S
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224
arch/mips/lib/genex.S
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@ -0,0 +1,224 @@
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/*
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* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2002, 2007 Maciej W. Rozycki
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* Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#define STATMASK 0x1f
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.set noreorder
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/*
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* Macros copied and adapted from Linux MIPS
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*/
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.macro SAVE_AT
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.set push
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.set noat
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LONG_S $1, PT_R1(sp)
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.set pop
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.endm
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.macro SAVE_TEMP
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#if __mips_isa_rev < 6
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mfhi v1
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#endif
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#ifdef CONFIG_32BIT
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LONG_S $8, PT_R8(sp)
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LONG_S $9, PT_R9(sp)
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#endif
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LONG_S $10, PT_R10(sp)
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LONG_S $11, PT_R11(sp)
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LONG_S $12, PT_R12(sp)
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#if __mips_isa_rev < 6
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LONG_S v1, PT_HI(sp)
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mflo v1
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#endif
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LONG_S $13, PT_R13(sp)
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LONG_S $14, PT_R14(sp)
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LONG_S $15, PT_R15(sp)
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LONG_S $24, PT_R24(sp)
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#if __mips_isa_rev < 6
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LONG_S v1, PT_LO(sp)
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#endif
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.endm
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.macro SAVE_STATIC
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LONG_S $16, PT_R16(sp)
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LONG_S $17, PT_R17(sp)
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LONG_S $18, PT_R18(sp)
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LONG_S $19, PT_R19(sp)
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LONG_S $20, PT_R20(sp)
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LONG_S $21, PT_R21(sp)
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LONG_S $22, PT_R22(sp)
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LONG_S $23, PT_R23(sp)
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LONG_S $30, PT_R30(sp)
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.endm
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.macro SAVE_SOME
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.set push
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.set noat
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PTR_SUBU k1, sp, PT_SIZE
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LONG_S sp, PT_R29(k1)
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move sp, k1
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LONG_S $3, PT_R3(sp)
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LONG_S $0, PT_R0(sp)
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mfc0 v1, CP0_STATUS
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LONG_S $2, PT_R2(sp)
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LONG_S v1, PT_STATUS(sp)
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LONG_S $4, PT_R4(sp)
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mfc0 v1, CP0_CAUSE
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LONG_S $5, PT_R5(sp)
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LONG_S v1, PT_CAUSE(sp)
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LONG_S $6, PT_R6(sp)
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MFC0 v1, CP0_EPC
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LONG_S $7, PT_R7(sp)
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#ifdef CONFIG_64BIT
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LONG_S $8, PT_R8(sp)
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LONG_S $9, PT_R9(sp)
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#endif
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LONG_S v1, PT_EPC(sp)
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LONG_S $25, PT_R25(sp)
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LONG_S $28, PT_R28(sp)
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LONG_S $31, PT_R31(sp)
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.set pop
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.endm
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.macro RESTORE_AT
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.set push
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.set noat
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LONG_L $1, PT_R1(sp)
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.set pop
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.endm
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.macro RESTORE_TEMP
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#if __mips_isa_rev < 6
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LONG_L $24, PT_LO(sp)
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mtlo $24
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LONG_L $24, PT_HI(sp)
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mthi $24
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#endif
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#ifdef CONFIG_32BIT
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LONG_L $8, PT_R8(sp)
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LONG_L $9, PT_R9(sp)
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#endif
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LONG_L $10, PT_R10(sp)
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LONG_L $11, PT_R11(sp)
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LONG_L $12, PT_R12(sp)
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LONG_L $13, PT_R13(sp)
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LONG_L $14, PT_R14(sp)
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LONG_L $15, PT_R15(sp)
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LONG_L $24, PT_R24(sp)
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.endm
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.macro RESTORE_STATIC
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LONG_L $16, PT_R16(sp)
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LONG_L $17, PT_R17(sp)
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LONG_L $18, PT_R18(sp)
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LONG_L $19, PT_R19(sp)
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LONG_L $20, PT_R20(sp)
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LONG_L $21, PT_R21(sp)
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LONG_L $22, PT_R22(sp)
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LONG_L $23, PT_R23(sp)
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LONG_L $30, PT_R30(sp)
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.endm
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.macro RESTORE_SOME
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.set push
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.set reorder
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.set noat
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mfc0 a0, CP0_STATUS
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ori a0, STATMASK
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xori a0, STATMASK
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mtc0 a0, CP0_STATUS
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li v1, ST0_CU1 | ST0_FR | ST0_IM
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and a0, v1
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LONG_L v0, PT_STATUS(sp)
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nor v1, $0, v1
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and v0, v1
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or v0, a0
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mtc0 v0, CP0_STATUS
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LONG_L v1, PT_EPC(sp)
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MTC0 v1, CP0_EPC
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LONG_L $31, PT_R31(sp)
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LONG_L $28, PT_R28(sp)
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LONG_L $25, PT_R25(sp)
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#ifdef CONFIG_64BIT
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LONG_L $8, PT_R8(sp)
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LONG_L $9, PT_R9(sp)
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#endif
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LONG_L $7, PT_R7(sp)
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LONG_L $6, PT_R6(sp)
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LONG_L $5, PT_R5(sp)
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LONG_L $4, PT_R4(sp)
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LONG_L $3, PT_R3(sp)
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LONG_L $2, PT_R2(sp)
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.set pop
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.endm
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.macro RESTORE_SP
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LONG_L sp, PT_R29(sp)
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.endm
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NESTED(except_vec3_generic, 0, sp)
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PTR_LA k1, handle_reserved
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jr k1
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nop
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END(except_vec3_generic)
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NESTED(except_vec_ejtag_debug, 0, sp)
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PTR_LA k1, handle_ejtag_debug
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jr k1
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nop
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END(except_vec_ejtag_debug)
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NESTED(handle_reserved, PT_SIZE, sp)
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SAVE_SOME
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SAVE_AT
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SAVE_TEMP
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SAVE_STATIC
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PTR_LA t9, do_reserved
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jr t9
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move a0, sp
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END(handle_reserved)
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NESTED(handle_ejtag_debug, PT_SIZE, sp)
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.set push
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.set noat
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MTC0 k1, CP0_DESAVE
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/* Check for SDBBP */
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MFC0 k1, CP0_DEBUG
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sll k1, k1, 30
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bgez k1, ejtag_return
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nop
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SAVE_SOME
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SAVE_AT
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SAVE_TEMP
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SAVE_STATIC
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PTR_LA t9, do_ejtag_debug
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jalr t9
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move a0, sp
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RESTORE_TEMP
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RESTORE_STATIC
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RESTORE_AT
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RESTORE_SOME
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RESTORE_SP
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ejtag_return:
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MFC0 k1, CP0_DESAVE
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deret
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.set pop
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END(handle_ejtag_debug)
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106
arch/mips/lib/traps.c
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106
arch/mips/lib/traps.c
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@ -0,0 +1,106 @@
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/*
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* Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
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* Copyright (C) 1995, 1996 Paul M. Antoine
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* Copyright (C) 1998 Ulf Carlsson
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
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* Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2014, Imagination Technologies Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void show_regs(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned int cause = regs->cp0_cause;
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unsigned int exccode;
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int i;
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/*
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* Saved main processor registers
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*/
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for (i = 0; i < 32; ) {
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if ((i % 4) == 0)
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printf("$%2d :", i);
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if (i == 0)
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printf(" %0*lx", field, 0UL);
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else if (i == 26 || i == 27)
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printf(" %*s", field, "");
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else
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printf(" %0*lx", field, regs->regs[i]);
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i++;
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if ((i % 4) == 0)
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puts("\n");
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}
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printf("Hi : %0*lx\n", field, regs->hi);
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printf("Lo : %0*lx\n", field, regs->lo);
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/*
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* Saved cp0 registers
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*/
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printf("epc : %0*lx (text %0*lx)\n", field, regs->cp0_epc,
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field, regs->cp0_epc - gd->reloc_off);
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printf("ra : %0*lx (text %0*lx)\n", field, regs->regs[31],
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field, regs->regs[31] - gd->reloc_off);
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printf("Status: %08x\n", (uint32_t) regs->cp0_status);
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exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
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printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
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if (1 <= exccode && exccode <= 5)
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printf("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
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printf("PrId : %08x\n", read_c0_prid());
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}
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void do_reserved(const struct pt_regs *regs)
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{
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puts("\nOoops:\n");
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show_regs(regs);
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hang();
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}
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void do_ejtag_debug(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned long depc;
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unsigned int debug;
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depc = read_c0_depc();
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debug = read_c0_debug();
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printf("SDBBP EJTAG debug exception: c0_depc = %0*lx, DEBUG = %08x\n",
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field, depc, debug);
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}
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static void set_handler(unsigned long offset, void *addr, unsigned long size)
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{
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unsigned long ebase = gd->irq_sp;
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memcpy((void *)(ebase + offset), addr, size);
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flush_cache(ebase + offset, size);
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}
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void trap_init(ulong reloc_addr)
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{
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unsigned long ebase = gd->irq_sp;
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set_handler(0x180, &except_vec3_generic, 0x80);
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set_handler(0x280, &except_vec_ejtag_debug, 0x80);
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write_c0_ebase(ebase);
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clear_c0_status(ST0_BEV);
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execution_hazard_barrier();
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}
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