Paul Burton 4baa0ab67d MIPS: L2 cache support ... This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.burton@imgtec.com>		2016-09-21 15:04:04 +02:00
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cpu	MIPS: Map CM Global Control Registers	2016-09-21 15:04:04 +02:00
dts	mips: xilfpga: Add device tree files	2016-09-21 14:55:14 +02:00
include/asm	MIPS: L2 cache support	2016-09-21 15:04:04 +02:00
lib	MIPS: L2 cache support	2016-09-21 15:04:04 +02:00
mach-ath79	MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init	2016-09-21 15:04:04 +02:00
mach-au1x00	net: mii: Use spatch to update miiphy_register	2016-08-15 15:26:33 -05:00
mach-pic32	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
config.mk	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
Kconfig	MIPS: L2 cache support	2016-09-21 15:04:04 +02:00
Makefile	MIPS: add tune for MIPS 34kc	2016-05-31 09:38:11 +02:00