Commit graph

7889 commits

Author SHA1 Message Date
Michal Simek
6a1d91be31 arm64: zynqmp: Do not map unused OCM/TCM region
When OCM or TCM is protected this mapping still exist and it is causing access
violation.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:40:58 +02:00
Michal Simek
b0259c840e arm64: zynqmp: Add comment about level shifter mode v1
Silicon v1 didn't support SD boot mode with level shifter.
Because system can't boot any error message is not shown
that's why comment is just a record if someone tries to debug it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:40:58 +02:00
Jean-Francois Dagenais
8bf62ae7da arm64: zynqmp: spl: use given boot_device instead of fetching it again
The boot_device argument to spl_boot_mode was massively added without
actually modifying the existing functions.

This commit actually makes use of the handed value, which is the same.

Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-19 16:53:10 +02:00
Jean-Francois Dagenais
e3fdf5d056 arm64: zynqmp: spl: fix dual SD controller support
When enabling both SDHCI controllers, spl_mmc.c would actually choose
device sdhci0 even if booted from sdhci1 (boot_device). This is because
spl_mmc_get_device_index(boot_device) expects BOOT_DEVICE_MMC2[_2] in
order to return index 1 instead of 0.

The #if defined(...) statement is copied from board/xilinx/zynqmp/zynqmp.c

So the key to properly enabling both controllers as boot sources is
defining both CONFIG_ZYNQ_SDHCI0 and CONFIG_ZYNQ_SDHCI1 in your board's
include/configs/*.h.

Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-19 16:53:09 +02:00
Michal Simek
bd89fba202 arm64: zynqmp: Wire SD1 level shifter mode to SPL
Add missing SD boot mode to SPL. zcu102-rev1.0 is supporting
this boot mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-19 16:53:09 +02:00
Tom Rini
ebba9d1daf Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-06-19 08:08:40 -04:00
Andrew F. Davis
88024dc5ac arm: mach-omap2: Generate MLO file from SD boot capable targets
Secure boot targets that can be loaded from an SD card FAT partition
need to be called "MLO" on the filesystem, make a copy with this name
to clarify the correct image for SD card booting.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-06-16 10:11:42 -04:00
Tom Rini
11b66916e0 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2017-06-14 18:52:49 -04:00
Jagan Teki
2b1a33213e sun50i: h5: Add initial NanoPi NEO2 support
NanoPi NEO2 is designed and developed by FriendlyElec
using the Allwinner 64-bit H5 SOC.

NanoPi Neo2 key features
- Allwinner H5, Quad-core 64-bit Cortex-A53
- 512MB DDR3 RAM
- microSD slot
- 10/100/1000M Ethernet
- Serial Debug Port
- 5V 2A DC MicroUSB power-supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-14 20:25:56 +05:30
Tom Rini
83ebd4a6b1 Revert "ARM: fixed relocation using proper alignment"
It turns out this change was not intended to be merged and as such,
revert it.

This reverts commit cdde7de036.

Reported-by: Manfred Schlaegl <manfred.schlaegl@ginzinger.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-14 09:13:21 -04:00
Jagan Teki
bdf9577355 sun50i: a64: Add initial Orangepi Win/WinPlus support
Orangepi Win/WinPlus is an open-source single-board computer
using the Allwinner A64 SOC.

A64 Orangepi Win/WinPlus has
- A64 Quad-core Cortex-A53 64bit
- 1GB(Win)/2GB(Win Plus) DDR3 SDRAM
- Debug TTL UART
- Four USB 2.0
- HDMI
- LCD
- Audio and MIC
- Wifi + BT
- IR receiver
- 5V DC power supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-14 15:58:39 +05:30
Jagan Teki
d6b1d7d81b sun50i: h5: Add initial Orangepi Zero Plus 2 support
Orangepi Zero Plus 2 is an open-source single-board computer
using the Allwinner h5 SOC.

H5 Orangepi Zero Plus 2 has
- Quad-core Cortex-A53
- 512MB DDR3
- micrSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG+power supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-14 15:52:19 +05:30
Stephen Warren
2eb3e28b2c ARM: tegra: remove Whistler support
Whistler is an ancient Tegra 2 reference board. I may have been the only
person who ever used it with upstream software, and I've just recycled
the board hardware. Hence, it makes sense to remove support from software.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2017-06-12 13:03:50 -07:00
Cooper Jr., Franklin
f8dbc0734d ARM: dts: keystone-k2hk-evm: Add U-boot specific dtsi file
With Davinci I2C switching to device model, K2HK requires U-boot specific
device tree entries. This is only required for I2C 1 which is needed
extremely early during the boot process.

Fixes: 1743d040b1 ("ARM: keystone: Enable DM_I2C by default")
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
2017-06-12 08:38:44 -04:00
Lothar Waßmann
69c5d76f2f ARM: provide a valid exception stack address for startup code
Create exception stack in IRAM if available to facilitate debugging of
pre-relocation code by catching exceptions rather than stopping dead.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
2017-06-12 08:38:40 -04:00
Lothar Waßmann
c88823612d arm: adjust PC displayed in exception handlers to point to the failing instruction
Adjust the program counter register to point to the failing
instruction depending on the exeption type.
This makes it easier to localize the offending instruction leading to
a fatal exception.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
2017-06-12 08:38:39 -04:00
Lothar Waßmann
53d4ed704b ARM: remove bogus cp_delay() function
The cp_delay() function was introduced because of a missing 'volatile'
attribute to the 'asm' statement in get_cr() which led to the 'mrc'
instruction in get_cr() being optimised out eventually.
This has been fixed in commit 53fd4b8c22 ("arm: mmu: Add missing volatile for reading SCTLR register")
but the bogus cp_delay() function which was introduced as a workaround
for the malfunctioning get_cr() was never removed.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
2017-06-12 08:38:39 -04:00
Patrice Chotard
1113ad49dc serial: stm32x7: align compatible with kernel one
stm32x7.c driver is dedicated for STM32F7.
In kernel, "st,stm32-usart" and "st,stm32-uart" compatible
strings are dedicated for STM32F4.

To keep U-boot and kernel aligned, replace the serial compatible
string from "st,stm32-usart", "st,stm32-uart" to
"st,stm32f7-usart", "st,stm32f7-uart" specific for STM32F7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-06-12 08:38:13 -04:00
Semen Protsenko
fa24eca1f2 omap: Add routine for setting fastboot variables
This patch reuses new option, which allows us to expose variables
from environment to "fastboot getvar" command. Those variables must be
of "fastboot.%s" format.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2017-06-12 08:36:21 -04:00
Manfred Schlaegl
cdde7de036 ARM: fixed relocation using proper alignment
Using u-boot-2017.05 on i.MX6UL we ran into following problem:
Initially U-Boot could be started normally.
If we added one random command in configuration, the newly generated
image hung at startup (last output was DRAM:  256 MiB).

We tracked this down to a data abort within relocation (relocated_code).

relocated_code in arch/arm/lib/relocate.S copies 8 bytes per loop
iteration until the source pointer is equal to __image_copy_end.
In a good case __image_copy_end was aligned to 8 bytes, so the loop
stopped as suggested, but in an errornous case __image_copy_end was
not aligned to 8 bytes, so the loop ran out of bounds and caused a
data abort exception.

This patches solves the issue by aligning __image_copy_end to 8 byte
using the linker script related to arm.

I don't know if it's the correct way to solve this, so some review would
be very appreciated.
2017-06-12 08:36:18 -04:00
Chen-Yu Tsai
3474827294 sunxi: psci: Move entry address setting to separate function
Currently we set the entry address in the psci_cpu_on function.
However R40 has a different register for this. This resulted in
an #ifdef / #else block in psci_cpu_on, which we avoided having
in the first place.

Move this part into a separate function, defined differently for
the R40 as opposed to the other single cluster platforms.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-12 15:41:02 +05:30
Tom Rini
8cb3ce64f9 Merge git://git.denx.de/u-boot-dm 2017-06-10 18:01:22 -04:00
Tom Rini
d2e1ee686a Merge branch 'master' of git://git.denx.de/u-boot-video 2017-06-10 09:48:09 -04:00
Tom Rini
75fd49c836 Merge branch 'master' of git://git.denx.de/u-boot-mmc 2017-06-10 09:47:57 -04:00
tnishinaga.dev@gmail.com
8f079cccb3 armv7m: Disable D-cache when booting nommu(ARMv7M) Linux kernel
Disable D-Cache is required when booting nommu Linux kernel.
(please see Linux kernel source "arch/arm/kernel/head-nommu.S")

U-Boot is enabled D-cache and I-Cache at startup.
However, it does not disable D-Cache before
booting nommu Linux kernel.
Therefore, I call dcache_disable()
when the CPU is ARMv7M to fix this problem.

Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
2017-06-09 20:34:54 -04:00
Semen Protsenko
00bbe96eba arm: omap: Unify get_device_type() function
Refactor OMAP3/4/5 code so that we have only one get_device_type()
function for all platforms.

Details:
 - Add ctrl variable for AM33xx and OMAP3 platforms (like it's done for
   OMAP4/5), so we can obtain status register in common way
 - For now ctrl structure for AM33xx/OMAP3 contains only status register
   address
 - Run hw_data_init() in order to assign ctrl to proper structure
 - Remove DEVICE_MASK and DEVICE_GP definitions as they are not used
   (DEVICE_TYPE_MASK and GP_DEVICE are used instead)
 - Guard structs in omap_common.h with #ifdefs, because otherwise
   including omap_common.h on non-omap4/5 board files breaks compilation

Buildman script was run for all OMAP boards. Result output:
    arm: (for 38/616 boards)
        all +352.5
        bss -1.4
        data +3.5
        rodata +300.0
        spl/u-boot-spl:all +284.7
        spl/u-boot-spl:data +2.2
        spl/u-boot-spl:rodata +252.0
        spl/u-boot-spl:text +30.5
        text +50.4
    (no errors to report)

Tested on AM57x EVM and BeagleBoard xM.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Rework the guards as to not break TI81xx]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-09 20:34:53 -04:00
Tom Rini
f2d78c1ced am33xx: Finish migration of CONFIG_AM33XX/AM43XX
Almost all users of CONFIG_AM33XX/AM43XX have been migrated.  Finish
moving the last few over to Kconfig, and put all of the boards under the
appropriate Kconfig chocie now.  This board choice is non-optional, so
remove that keyword on am33xx.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-09 20:34:09 -04:00
Simon Glass
fe97471632 rockchip: rk3288: Allow setting up clocks in U-Boot proper
If U-Boot is chain-loaded from a previous boot loader we must set up the
clocks the way U-Boot wants them. Add code for this. It will do nothing if
SPL has already done the job.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:45:34 -06:00
Simon Glass
b223c1aead rockchip: rk3288: Convert clock driver to use shifted masks
Shifted masks are the standard approach with rockchip since it allows
use of the mask without shifting it each time. Update the definitions and
the driver to match.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:45:33 -06:00
Simon Glass
6f06ef57bb rockchip: rk3288: Add error debugging to veyron_init()
Add a debug() statement so we can see when something goes wrong with the
regulator.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:34 -06:00
Simon Glass
3238474b8f rockchip: Fix regualtor typo in veyron
This typo doesn't actually cause any problems, but is wrong. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:34 -06:00
Simon Glass
1c6c7b6bd8 tegra: clock: Avoid a divide-by-zero error
The clock fix-up for tegra is still present in the code. It causes a
divide-by-zero bug after relocation when chain-loading U-Boot from
coreboot. Fix this by adding a check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks)
2017-06-09 13:39:33 -06:00
Simon Glass
c415dda8df tegra: dts: Add cros-ec SPI settings
At present the interrupt does not work and the SPI bus runs much less
quickly than it should. Add settings to fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:32 -06:00
Simon Glass
46864cc8e8 tegra: Init clocks even when SPL did not run
At present early clock init happens in SPL. If SPL did not run (because
for example U-Boot is chain-loaded from another boot loader) then the
clocks are not set as U-Boot expects.

Add a function to detect this and call the early clock init in U-Boot
proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:32 -06:00
Simon Glass
50a4886b3b arm: Disable LPAE if not enabled
If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does enable LPAE.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:32 -06:00
Simon Glass
10d602ac8b arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T
At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
has an ARMv4T boot CPU. Add a check for the architecture version to allow
the code to be built. It will not actually be executed by the boot CPU,
but needs to compile.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:32 -06:00
Simon Glass
579dfca2ef arm: Rename HCTR to HTCR
This appears to be a typo. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:31 -06:00
Simon Glass
1c2d2727d1 arm: arm720t: Support CONFIG_SKIP_LOWLEVEL_INIT_ONLY
This option allows skipping the call to lowlevel() while still performing
CP15 init. Support this on ARM720T so it can be used with Tegra.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:31 -06:00
Vikas Manocha
1a73bd842e spl: stm32f7: configure for xip booting
With xip booting configuration, we don't need to copy the next image
(U-Boot or linux xipimage) from flash to sdram area.

Flash memory organization is like this:
	spl-U-Boot:	u-boot-spl.bin 	: 0x0800_0000
	U-Boot :	u-boot-dtb.bin	: 0x0800_8000
	linux :		xipImage	: 0x0800_8000

It is also possible to have U-Boot binary & linux binaries configured at
different addresses of flash memory like U-Boot at 0x0800_8000 & linux
xipImage at 0x0800_4000. But in any case, spl-U-Boot needs to be compiled for
U-Boot as next binary with SPL_OS_BOOT option disabled.
By default, spl is configured to boot linux xipImage.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-09 11:24:00 -04:00
Vikas Manocha
55a3ef714f spl: stm32f7: add kernel boot support
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-09 11:24:00 -04:00
Vikas Manocha
c6d9e9dbc3 SPL: Add XIP booting support
Enable support for XIP (execute in place) of U-Boot or kernel image. There is
no need to copy image from flash to ram if flash supports execute in place.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com>
2017-06-09 11:23:59 -04:00
Vikas Manocha
b97476965b stm32: stm32f7: add spl build support
This commit supports booting from stm32 internal nor flash. spl U-Boot
initializes the sdram memory, copies next image (e.g. standard U-Boot)
to sdram & then jumps to entry point.

Here are the flash memory addresses for U-Boot-spl & standard U-Boot:
	- spl U-Boot		: 0x0800_0000
	- standard U-Boot	: 0x0800_8000

To compile u-boot without spl: Remove SUPPORT_SPL configuration
(arch/arm/mach-stm32/Kconfig)

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Rework Kconfig logic a bit]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-09 11:23:55 -04:00
Jernej Skrabec
b98efa1db3 sunxi: video: Add support for CSC and TVE to DE2 driver
Extend DE2 driver with support for TVE driver, which will be added in
next commit. TVE unit expects data to be in YUV format, so CSC support
is also added here.

Note that HDMI driver has higher priority, so TV out is not probed if
HDMI monitor is detected.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 15:30:47 +02:00
Jernej Skrabec
a8191dfec0 sunxi: Add base address for TV encoder
This commit adds TVE base address for Allwinner H3 and H5 SoCs.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-09 15:30:28 +02:00
Kouei Abe
91a16c3b2f mmc: sh_sdhi: Add MMC version 5.0 support
Renesas SDHI SD/MMC driver did not support MMC version 5.0 devices.
This adds MMC version 5.0 device support.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-06-09 20:25:16 +09:00
Kouei Abe
5eada1dbd0 mmc: sh_sdhi: Add 64-bit access to sd_buf support
Renesas SDHI SD/MMC driver has 16-bit width bus access to SD_BUF.
This adds 64-bit width bus access to SD_BUF.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-06-09 20:25:16 +09:00
Icenowy Zheng
ec4670a137 sunxi: add LPDDR3 timing from stock boot0
As we added LPDDR3 support in the former patch, we need a set of timing
info to really enable it.

Add the timing info used by stock boot0.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
72cc987002 sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller
Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.

Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.

Real LPDDR3 chips' support is not added yet in this commit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
7d06e59f73 sunxi: enable DRAM initialization and SPL for V3s SoC
As we have already support for the DesignWare DRAM controller and the
integrated DDR2 chip of V3s, let's enable the SPL support for V3s.

This patch also contains the default DRAM configuration for V3s.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
3ec0698b8a sunxi: add support for V3s DRAM controller
Allwinner V3s features a DRAM controller like the on in H3, but with a
DDR2 DRAM.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
67337e68a5 sunxi: add support for the DDR2 in V3s SoC
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
176868bc65 sunxi: enable dual rank detection in DesignWare-like DRAM code
The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second rank.

Set the default value to dual rank, thus the rank detection code can
work and finally the rank setting will be the correct value.

Currently we know little about the dual-rank on R40, and the usage
of A15 address line seems to be breaking dual-rank support. The only R40
board currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather
than dual-rank, thus we cannot do research for it. So dual rank detection
is temporarily disabled on R40.

This change is tested on a Orange Pi One (H3, single rank), a Pine64+
2GiB version (A64, single rank) , a Pinebook early prototype with DDR3
(A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins
on one chip).

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
f6457ce578 sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs.

Add options to select a timing set.

Currently only DDR3-1333 (the original set) is added into it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
66b12526f0 sunxi: add bank detection code to H3 DRAM initialization code
Some DDR2 DRAM have only four banks, not eight.

Add code to detect this situation.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
87098d701d sunxi: add option for 16-bit DW DRAM controller
Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.

Add support for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
f43a009959 sunxi: Rename bus-width related macros in H3 DRAM code
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.

As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit and 16-bit.

Rename the bit's macro, and also rename the variable name in
dram_sun8i_h3.c.

This commit do not add 16-bit DRAM controller support, but the support
will be introduced in next commit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
9934aba427 sunxi: makes an invisible option for H3-like DRAM controllers
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.

Add a invisible option for easier DRAM initialization code reuse.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Jagan Teki
b0174c39b3 sun8i: h3: Add initial NanoPi M1 Plus support
NanoPi M1 Plus is designed and developed by FriendlyElec
for professionals, enterprise users, makers and hobbyists
using the Allwinner H3 SOC.

NanoPi M1 Plus key features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 1GB DDR3 RAM
- 8GB eMMC
- microSD slot
- 10/100/1000M Ethernet
- Serial Debug Port
- 5V 2A DC power-supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 21:48:23 +05:30
Philipp Tomsich
ca562b630e rockchip: video: rk3399: add HDMI TX support on the RK3399
This commit enables the RK3399 HDMI TX, which is very similar to the
one found on the RK3288.  As requested by Simon, this splits the HDMI
driver into a SOC-specific portion (rk3399_hdmi.c, rk3288_hdmi.c) and
a common portion (rk_hdmi.c).

Note that the I2C communication for reading the EDID works well with
the default settings, but does not with the alternate settings used on
the RK3288... this configuration aspect is reflected by the driverdata
for the RK3399 driver.

Having some sort of DTS-based configuration for the regulator
dependencies would be nice for the future, but for now we simply use
lists of regulator names (also via driverdata) that we probe.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:50 -06:00
Philipp Tomsich
cc75afc5d7 rockchip: video: rk3399: enable HDMI output (from the rk_vop) for the RK3399
This commit adds a driver for the RK3399 VOPs capable and all the
necessary plumbing to feed the HDMI encoder. For the VOP-big, this
correctly tracks the ability to feed 10bit RGB data to the encoder.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:49 -06:00
Philipp Tomsich
d46d40474a rockchip: video: refactor rk_vop and split RK3288-specific code off
To prepare for adding the RK3399 VOP driver (which shares most of its
registers and config logic with the RK3228 VOP), this change refactors
the driver and splits the RK3288-specific driver off.

The changes in detail are:
- introduces a data-structure for chip-specific drivers to register
  features/callbacks with the common driver: at this time, this is
  limited to a callback for setting the pin polarities (between the
  VOP and the encoder modules) and a flag to signal 10bit RGB
  capability
- refactors the probing of regulators into a helper function that
  can take a list of regulator names to probe and autoset
- moves the priv data-structure into a (common) header file to be
  used by the chip-specific drivers to provide base addresses to
  the common driver
- uses a callback into the chip-specific driver to set pin polarities
  (replacing the direct register accesses previously used)
- splits enabling the output (towards an encoder) into a separate
  help function withint the common driver

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:49 -06:00
Romain Perier
fefe9d06bd rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE
RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit
0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and
introduces random delays and data lose.

This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE
with the right shift.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
cf35242a3e rockchip: dts: rk3399-puma: add DTS for the DDR3-1866 timing
This adds the DDR3-1866 timing via its own DTS and wires it up.  This
(currently) is not the default timing for the RK3399-Q7 and should be
selected explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
6608cf0fbe rockchip: dts: rk3399-puma: add DTS for the DDR3-1333 timing
This adds the DDR3-1333 timing via its own DTS and wires it up.  This
is not the default timing for the RK3399-Q7 and should be selected
explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
3a29ae8e6f rockchip: dts: rk3399-puma: refactor and rename (default) DDR3-1600 DTS
To better support different RAM timings (DDR3-1333 and DDR3-1866 are
assembly options for the RK3399-Q7), this refactors the DTS support
and renames the default DTS variant from rk3399-puma to
rk3399-puma-ddr1600:
- changes the rk3399-puma DTS into a board-specific DTSI by removing
  the inclusion of the DRAM timings
- adds a new rk3399-puma-ddr1600.dts, which includes the (new) common
  board DTSI and the DDR3-1600 timing DTSI
- wires this up from arch/arm/dts/Makefile and configs/puma-rk3399_defconfig

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
f592edd920 rockchip: dts: rk3399-puma: sync DTS with Linux tree
The Linux DTS for the RK3399-Q7 has moved with the times... resync
against it to ensure a consistent configuration.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Philipp Tomsich
876c1d0fb1 rockchip: dts: rk3399: enable HDMI output in the DTS
This commit enables HDMI output in the DTS by adding the necessary
nodes to vopl/vopb and by adding the HDMI node.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 21:30:48 -06:00
Andy Yan
2d1951fec6 rockchip: Add basic support for evb-rv1108 board
Add basic support for rv1108 evb, whith this patch we
can boot into u-boot console.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Andy Yan
2c1e11dd52 rockchip: Add core Soc start-up code for rv1108
RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core
from Rockchip. It is designed for varies application scenario such
as car DVR, sports DV, secure camera and UAV camera.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Andy Yan
bae2f282a9 rockchip: clk: Add rv1108 clock driver
Add clock driver support for Rockchip rv1108 soc

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Andy Yan
09aa7c468c rockchip: pinctrl: Add rv1108 pinctrl driver
Add pinctrl support for Rockchip rv1108 soc

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:24 -06:00
Klaus Goger
a4264b4d14 rockchip: dts: rk3399-puma: set spl-payload-offset
defines the spl-payload to 256k (0x40000)

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
2dd2c011e8 rockchip: dts: rk3399-puma: release reset of on-module USB3 hub via vbus-gpio
On the RK3399-Q7, the on-module USB3 hub is held in reset at boot-up
to save power and needs to be woken up using GPIO4A3.

Note that this is not a negated reset-signal (due to a level shifter
being needed for this signal anyway), but a negated enable-signal:
to enable, we need to output LOW (i.e. 0)... so we mark this as an
ACTIVE_LOW signal.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
4411cd054b rockchip: dts: rk3399-puma: make the debug serial dm-pre-reloc
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
3b89461b40 rockchip: dts: rk3399-puma: Add DDR3-1866 timings
With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we
can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built
with the DDR3-1866 option.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
fcb2158516 rockchip: arm64: rk3399: support DDR3-1866 (i.e. 933MHz clock)
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866),
if the PCB layout permits and appropriate memory timings are used.

This changes the sanity checks to allow a DTS to request DDR3-1866
operation.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2017-06-07 07:29:23 -06:00
Philipp Tomsich
fbecb94e4b rockchip: arm64: rk3399: revise timeout-handling for DRAM PHY lock
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to
clearly state a timeout in milliseconds and use get_timer (based on
the ARMv8 architected timer) to detect a timeout.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:23 -06:00
Meng Dongyang
75ff918f83 rockchip: dts: rk3328: support and enable xhci
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:22 -06:00
Meng Dongyang
ef82a0db5a rockchip: dts: rk3328: add ehci and ohci node and enable host0 port
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:21 -06:00
Kever Yang
077eb31514 rockchip: pinctrl: rk3328: do not set io routing
In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.

We should not decide which group to use in pinctrl driver,
for it may be different in different board, it should goes to board
file, and the pinctrl file should setting correct iomux depends on
the com_iomux value.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:21 -06:00
Kever Yang
6f0c123713 rockchip: pinctrl: move rk3328 grf reg definition in header file
Move GRF register bit definition into GRF header file, remove
'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:21 -06:00
Kever Yang
3c421f6fa9 rockchip: rk3036: clean mask definition for grf reg
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
definition in grf header file and pinctrl driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:21 -06:00
Kever Yang
1960b01034 rockchip: clock: rk3036: some fix according TRM
- hclk/pclk_div range should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
Kever Yang
37943aaeea rockchip: rk3036: clean mask definition for cru reg
Embeded the shift in mask MACRO definition in cru header file
and clock driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
Andy Yan
9d7ed33926 rockchip: rk3368: Add PX5 Evaluation board
PX5 EVB is designed by Rockchip for automotive field
with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
HDMI video input/output interface, audio codec ES8396,
WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity
sensor STK3410.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
Andreas Färber
54c57ae051 rockchip: rk3368: Add initial support for RK3368 based GeekBox
The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
The module can be used with base boards such as the GeekBox Landingship.
This adds basic support to chain-load U-Boot from Rockchip's miniloader.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
Andy Yan
e2901ab8f6 rockchip: rk3368: add Sheep board
Sheep board is designed by Rockchip as a EVB for rk3368.
Currently it is able to boot a linux kernel and system
to console with the miniloader run as fist level loader.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2017-06-07 07:29:20 -06:00
Andreas Färber
37a0c60085 rockchip: rk3368: Add core start-up code for RK3368
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:19 -06:00
Andy Yan
27600a5837 rockchip: rk3368: Add pinctrl driver
Add driver to support iomux setup for the most commonly
used peripherals on rk3368.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:19 -06:00
Andy Yan
d1dcf8527e rockchip: rk3368: Add clock driver
Add driver to setup the various PLLs and peripheral
clocks on the RK3368.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:19 -06:00
Kever Yang
c4a921513a rockchip; rk3399: disable SRAM security region
Some host like SD and eMMC may use DMA to transter data to SRAM,
set memory to non-secure to make sure the address can be accessed.

The security of SRAM in OS suppose to initialized in ATF bl31, and
the SPL is before the bl31.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-06-07 06:57:49 -06:00
Phil Edworthy
71d2cf2359 armv7m: Fix larger builds
The branch instruction only has an 11-bit relative target address, which
is sometimes not enough.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
2017-06-05 14:13:14 -04:00
Phil Edworthy
111a6af97a arm: Add Kconfig symbols used for Linux asm compatibility
Rather than change asm files that come from Linux, add the symbols
to Kconfig. Since one of the symbols is for thumb2 builds, make
CPU_V7M always select them.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
2017-06-05 14:13:13 -04:00
Michal Simek
439edf6120 arm64: Add NOLOAD attribute NOLOAD to .bss sections
Mark explicitly bss sections to not be loaded at
run time.
The similar patch was done in past by:
"Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections"
(sha1: 64134f0112)

The problem is related to latest toolchain added to Xilinx
v2017.1 design tools where jtag loader is trying to access
ununitialized memory.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-05 14:13:12 -04:00
Michal Simek
3c85417f45 ARMv8: Add support for poweroff via PSCI
Add support for calling poweroff in case of psci is wired.
Based on the same solution as is used for reset.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Move all logic in to fwcall.c as other ARMs implement poweroff
via PMIC]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05 14:13:12 -04:00
Pantelis Antoniou
54cc4dcfda arm: Always keep the dtb section on objcopy
The dtb blob section must always be present in the resulting image.
Either if OF_EMBEDED is used or if unit tests include dtb blobs.

Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-05 14:13:11 -04:00
Simon Glass
457e51cffd common: arm: freescale: layerscape: Move header files out of common.h
We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05 14:12:59 -04:00
Simon Glass
89f5eaa1ee common: arm: davinci: Move header file out of common
We should not have an arch-specific header file in common.h. Instead, use
the asm/hardware.h header to provide the required declarations, and drop
the common.h changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-05 12:31:23 -04:00
Simon Glass
1c16d2e248 common: ep93xx: Move arch-specific declarations out of common
These declarations should not be in common. Remove those that are not
needed and move the others to an arch-specific location.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05 12:31:22 -04:00
Simon Glass
68994b98fc common: freescale: Move arch-specific imx code to arch-imx
These declarations should not be in common.h. Move them to an
arch-specific header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-05 12:31:22 -04:00