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rockchip: arm64: rk3399: revise timeout-handling for DRAM PHY lock

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Revise the loop watching for a timeout on obtaining a DRAM PHY lock to
clearly state a timeout in milliseconds and use get_timer (based on
the ARMv8 architected timer) to detect a timeout.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Philipp Tomsich 2017-05-31 18:16:34 +02:00 committed by Simon Glass
parent a1c29d4b43
commit fbecb94e4b
1 changed files with 11 additions and 6 deletions
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17
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
View file

@ -5,6 +5,7 @@
*
* Adapted from coreboot.
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
@ -19,6 +20,7 @@
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/hardware.h>
#include <linux/err.h>
#include <time.h>
DECLARE_GLOBAL_DATA_PTR;
struct chan_info {
@ -506,6 +508,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
u32 tmp, tmp1, tmp2;
u32 pwrup_srefresh_exit;
int ret;
const ulong timeout_ms = 200;
/*
* work around controller bug:
@ -588,13 +591,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
/* Wating for PHY and DRAM init complete */
tmp = 0;
while (!(readl(&denali_ctl[203]) & (1 << 3))) {
mdelay(10);
tmp++;
if (tmp > 10)
tmp = get_timer(0);
do {
if (get_timer(tmp) > timeout_ms) {
error("DRAM (%s): phy failed to lock within %ld ms\n",
__func__, timeout_ms);
return -ETIME;
}
}
} while (!(readl(&denali_ctl[203]) & (1 << 3)));
debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
pwrup_srefresh_exit);