mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
rockchip: Add basic support for evb-rv1108 board
Add basic support for rv1108 evb, whith this patch we can boot into u-boot console. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Andy Yan
Simon Glass
parent
2c1e11dd52
commit
2d1951fec6
11 changed files with 747 additions and 1 deletions
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@ -46,7 +46,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk3368-px5-evb.dtb \
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rk3399-evb.dtb \
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rk3399-firefly.dtb \
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rk3399-puma.dtb
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rk3399-puma.dtb \
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rv1108-evb.dtb
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dtb-$(CONFIG_ARCH_MESON) += \
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meson-gxbb-odroidc2.dtb
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dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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54
arch/arm/dts/rv1108-evb.dts
Normal file
54
arch/arm/dts/rv1108-evb.dts
Normal file
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@ -0,0 +1,54 @@
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "rv1108.dtsi"
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/ {
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model = "Rockchip RV1108 Evaluation board";
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compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x08000000>;
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};
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chosen {
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stdout-path = "serial2:1500000n8";
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};
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};
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&gmac {
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status = "okay";
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clock_in_out = <0>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 1000000>;
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snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
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};
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&sfc {
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status = "okay";
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flash@0 {
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compatible = "gd25q256","spi-flash";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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spi-max-frequency = <96000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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479
arch/arm/dts/rv1108.dtsi
Normal file
479
arch/arm/dts/rv1108.dtsi
Normal file
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@ -0,0 +1,479 @@
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/rv1108-cru.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rv1108";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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spi0 = &sfc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@102a0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x102a0000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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bus_intmem@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x2000>;
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};
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uart2: serial@10210000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10210000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "disabled";
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};
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uart1: serial@10220000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10220000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart0: serial@10230000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10230000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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grf: syscon@10300000 {
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compatible = "rockchip,rv1108-grf", "syscon";
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reg = <0x10300000 0x1000>;
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};
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pmugrf: syscon@20060000 {
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compatible = "rockchip,rv1108-pmugrf", "syscon";
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reg = <0x20060000 0x1000>;
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};
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cru: clock-controller@20200000 {
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compatible = "rockchip,rv1108-cru";
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reg = <0x20200000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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emmc: dwmmc@30110000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30110000 0x4000>;
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status = "disabled";
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};
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sdio: dwmmc@30120000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30120000 0x4000>;
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status = "disabled";
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};
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sdmmc: dwmmc@30130000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 100000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30130000 0x4000>;
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status = "disabled";
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};
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sfc: sfc@301c0000 {
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compatible = "rockchip,sfc";
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reg = <0x301c0000 0x200>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
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clock-names = "clk_sfc", "hclk_sfc";
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pinctrl-0 = <&sfc_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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gmac: ethernet@30200000 {
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compatible = "rockchip,rv1108-gmac";
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reg = <0x30200000 0x10000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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rockchip,grf = <&grf>;
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clocks = <&cru SCLK_MAC>,
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<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
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<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
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<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
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clock-names = "stmmaceth",
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"mac_clk_rx", "mac_clk_tx",
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"clk_mac_ref", "clk_mac_refout",
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"aclk_mac", "pclk_mac";
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pinctrl-names = "default";
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pinctrl-0 = <&rmii_pins>;
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phy-mode = "rmii";
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max-speed = <100>;
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status = "disabled";
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};
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gic: interrupt-controller@32010000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x32011000 0x1000>,
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<0x32012000 0x1000>,
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<0x32014000 0x2000>,
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<0x32016000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rv1108-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmugrf>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@20030000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20030000 0x100>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@10310000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10310000 0x100>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@10320000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10320000 0x100>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@10330000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10330000 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg-pull-up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg-pull-down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg-pull-none {
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bias-disable;
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};
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pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
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drive-strength = <8>;
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};
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pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
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drive-strength = <12>;
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};
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pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
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bias-pull-up;
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drive-strength = <8>;
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};
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pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
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drive-strength = <4>;
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};
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pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
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bias-pull-up;
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drive-strength = <4>;
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};
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pcfg_output_high: pcfg-output-high {
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output-high;
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};
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pcfg_output_low: pcfg-output-low {
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output-low;
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};
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pcfg_input_high: pcfg-input-high {
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bias-pull-up;
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input-enable;
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};
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gmac {
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rmii_pins: rmii-pins {
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rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
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<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
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<1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
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<1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
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<1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
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<1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
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<1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
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<1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
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<1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
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<1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
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<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
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};
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};
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i2c2m1 {
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i2c2m1_xfer: i2c2m1-xfer {
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rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
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<0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
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};
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i2c2m1_gpio: i2c2m1-gpio {
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rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
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<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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i2c2m05v {
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i2c2m05v_xfer: i2c2m05v-xfer {
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rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
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<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
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};
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i2c2m05v_gpio: i2c2m05v-gpio {
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rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
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<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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i2c3 {
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i2c3_xfer: i2c3-xfer {
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rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sfc {
|
||||
sfc_pins: sfc-pins {
|
||||
rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_cd: sdmmc-cd {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_bus1: sdmmc-bus1 {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts_gpio: uart0-rts-gpio {
|
||||
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart01rts: uart1-rts {
|
||||
rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2m0 {
|
||||
uart2m0_xfer: uart2m0-xfer {
|
||||
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2m1 {
|
||||
uart2m1_xfer: uart2m1-xfer {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_5v {
|
||||
uart2_5v_cts: uart2_5v-cts {
|
||||
rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2_5v_rts: uart2_5v-rts {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,9 +1,28 @@
|
|||
if ROCKCHIP_RV1108
|
||||
|
||||
config TARGET_EVB_RV1108
|
||||
bool "EVB_RV1108"
|
||||
help
|
||||
RV1108 EVB is a evaluation board for Rockchp RV1108.
|
||||
|
||||
Key features of the board include:
|
||||
* one macro USB OTG port
|
||||
* one USB HOST port
|
||||
* one RS232 to USB port route to UART2 as debug port
|
||||
* MIPI screen with resolution 720 x 1280
|
||||
* 128M DDR3
|
||||
* 64M SPI Nor Flash
|
||||
* macro SD card interface
|
||||
* HDMI output
|
||||
* 10/100 Mbps Ethernet
|
||||
* camera interface compatible with imx323 / ov2710 / ov4689
|
||||
|
||||
config SYS_SOC
|
||||
default "rockchip"
|
||||
|
||||
config SYS_MALLOC_F_LEN
|
||||
default 0x400
|
||||
|
||||
source board/rockchip/evb_rv1108/Kconfig
|
||||
|
||||
endif
|
||||
|
|
|
|||
15
board/rockchip/evb_rv1108/Kconfig
Normal file
15
board/rockchip/evb_rv1108/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
if TARGET_EVB_RV1108
|
||||
|
||||
config SYS_BOARD
|
||||
default "evb_rv1108"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "rockchip"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "evb_rv1108"
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
|
||||
endif
|
||||
6
board/rockchip/evb_rv1108/MAINTAINERS
Normal file
6
board/rockchip/evb_rv1108/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
EVB-RV1108
|
||||
M: Andy Yan <andy.yan@rock-chips.com>
|
||||
S: Maintained
|
||||
F: board/rockchip/evb_rv1108
|
||||
F: include/configs/evb_rv1108.h
|
||||
F: configs/evb-rv1108_defconfig
|
||||
7
board/rockchip/evb_rv1108/Makefile
Normal file
7
board/rockchip/evb_rv1108/Makefile
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += evb_rv1108.o
|
||||
47
board/rockchip/evb_rv1108/README
Normal file
47
board/rockchip/evb_rv1108/README
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
Here is the step-by-step to boot U-Boot on rv1108 evb.
|
||||
|
||||
Get ddr init binary
|
||||
==============================================================================
|
||||
> git clone https://github.com/rockchip-linux/rkbin.git
|
||||
> dd if=./rkbin/rv1x/rv1108ddr.bin of=ddr.bin bs=4 skip=1
|
||||
|
||||
Compile U-Boot
|
||||
===========================
|
||||
> make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig all
|
||||
> ./tools/mkimage -n rv1108 -T rksd -d ddr.bin spl.bin
|
||||
> cat spl.bin u-boot.bin > u-boot.img
|
||||
|
||||
Flash the image by rkdeveloptool
|
||||
================================
|
||||
rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git
|
||||
|
||||
Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
|
||||
> rkdeveloptool db ./rkbin/rv1x/RV1108_usb_boot.bin
|
||||
> rkdeveloptool wl 0x40 u-boot.img
|
||||
> rkdeveloptool RD
|
||||
|
||||
You should be able to get U-Boot log message from boot console:
|
||||
|
||||
DDR Version V1.02 20170220
|
||||
In
|
||||
400MHz
|
||||
DDR3
|
||||
Bus Width=16 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=512MB
|
||||
mach:2
|
||||
OUT
|
||||
|
||||
|
||||
U-Boot 2017.05-00693-g3a5b171 (Jun 01 2017 - 17:37:53 +0800)
|
||||
|
||||
Model: Rockchip RV1108 Evaluation board
|
||||
DRAM: 128 MiB
|
||||
APLL: 600000000 DPLL:792000000 GPLL:384000000
|
||||
MMC:
|
||||
Using default environment
|
||||
|
||||
In: serial@10210000
|
||||
Out: serial@10210000
|
||||
Err: serial@10210000
|
||||
Net: No ethernet found.
|
||||
Hit any key to stop autoboot: 0
|
||||
=>
|
||||
52
board/rockchip/evb_rv1108/evb_rv1108.c
Normal file
52
board/rockchip/evb_rv1108/evb_rv1108.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* (C)Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
* Authors: Andy Yan <andy.yan@rock-chips.com>
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <fdtdec.h>
|
||||
#include <asm/arch/grf_rv1108.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int mach_cpu_init(void)
|
||||
{
|
||||
int node;
|
||||
struct rv1108_grf *grf;
|
||||
|
||||
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf");
|
||||
grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
|
||||
|
||||
/*evb board use UART2 m0 for debug*/
|
||||
rk_clrsetreg(&grf->gpio2d_iomux,
|
||||
GPIO2D2_MASK | GPIO2D1_MASK,
|
||||
GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
|
||||
GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
|
||||
rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = 0x8000000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = 0x60000000;
|
||||
gd->bd->bi_dram[0].size = 0x8000000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
40
configs/evb-rv1108_defconfig
Normal file
40
configs/evb-rv1108_defconfig
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ROCKCHIP_RV1108=y
|
||||
CONFIG_TARGET_EVB_RV1108=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
CONFIG_CMD_SF=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_ROCKCHIP_RV1108=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
# CONFIG_SPL_SERIAL_PRESENT is not set
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEBUG_UART_BASE=0x10210000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
26
include/configs/evb_rv1108.h
Normal file
26
include/configs/evb_rv1108.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <configs/rv1108_common.h>
|
||||
|
||||
/*
|
||||
* Default environment settings
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"ipaddr=172.16.12.50\0" \
|
||||
"serverip=172.16.12.69\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"sf probe;" \
|
||||
"sf read 0x62000000 0x140800 0x500000;" \
|
||||
"dcache off;" \
|
||||
"go 0x62000000"
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue