mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-video
This commit is contained in:
commit
d2e1ee686a
9 changed files with 161 additions and 16 deletions
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@ -34,7 +34,9 @@
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#define SUNXI_MS_BASE 0x01c07000
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#define SUNXI_TVD_BASE 0x01c08000
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#define SUNXI_CSI0_BASE 0x01c09000
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#ifndef CONFIG_MACH_SUNXI_H3_H5
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#define SUNXI_TVE0_BASE 0x01c0a000
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#endif
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#define SUNXI_EMAC_BASE 0x01c0b000
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#define SUNXI_LCD0_BASE 0x01c0C000
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#define SUNXI_LCD1_BASE 0x01c0d000
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@ -161,10 +163,18 @@ defined(CONFIG_MACH_SUN50I)
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/* module sram */
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#define SUNXI_SRAM_C_BASE 0x01d00000
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#ifndef CONFIG_MACH_SUN8I_H3
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#define SUNXI_DE_FE0_BASE 0x01e00000
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#else
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#define SUNXI_TVE0_BASE 0x01e00000
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#endif
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#define SUNXI_DE_FE1_BASE 0x01e20000
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#define SUNXI_DE_BE0_BASE 0x01e60000
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#ifndef CONFIG_MACH_SUN50I_H5
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#define SUNXI_DE_BE1_BASE 0x01e40000
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#else
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#define SUNXI_TVE0_BASE 0x01e40000
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#endif
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#define SUNXI_MP_BASE 0x01e80000
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#define SUNXI_AVG_BASE 0x01ea0000
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@ -90,6 +90,23 @@ struct de_ui {
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u32 ovl_size;
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};
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struct de_csc {
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u32 csc_ctl;
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u8 res[0xc];
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u32 coef11;
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u32 coef12;
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u32 coef13;
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u32 coef14;
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u32 coef21;
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u32 coef22;
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u32 coef23;
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u32 coef24;
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u32 coef31;
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u32 coef32;
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u32 coef33;
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u32 coef34;
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};
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/*
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* DE register constants.
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*/
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@ -295,7 +295,7 @@ static void edid_print_dtd(struct edid_monitor_descriptor *monitor,
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h_total = h_active + h_blanking;
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v_total = v_active + v_blanking;
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if (v_total * h_total)
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if (v_total > 0 && h_total > 0)
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vfreq = pixclock / (v_total * h_total);
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else
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vfreq = 1; /* Error case */
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@ -426,7 +426,9 @@ static void atmel_hlcdc_init(struct udevice *dev)
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writel(~0UL, ®s->lcdc_baseidr);
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/* Setup the DMA descriptor, this descriptor will loop to itself */
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desc = (struct lcd_dma_desc *)(uc_plat->base - 16);
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desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
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if (!desc)
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return;
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desc->address = (u32)uc_plat->base;
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@ -436,7 +438,9 @@ static void atmel_hlcdc_init(struct udevice *dev)
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desc->next = (u32)desc;
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/* Flush the DMA descriptor if we enabled dcache */
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flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
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flush_dcache_range((u32)desc,
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ALIGN(((u32)desc + sizeof(*desc)),
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CONFIG_SYS_CACHELINE_SIZE));
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writel(desc->address, ®s->lcdc_baseaddr);
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writel(desc->control, ®s->lcdc_basectrl);
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@ -23,10 +23,54 @@ struct rk_hdmi_priv {
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void *grf;
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};
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/**
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* rk_hdmi_read_edid() - read the attached HDMI/DVI monitor's EDID
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*
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* N.B.: The buffer should be large enough to hold 2 EDID blocks, as
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* this function calls dw_hdmi_read_edid, which ignores buf_size
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* argument and assumes that there's always enough space for 2
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* EDID blocks.
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*
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* @dev: device
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* @buf: output buffer for the EDID
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* @buf_size: number of bytes in the buffer
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* @return number of bytes read if OK, -ve if something went wrong
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*/
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int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size);
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/**
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* rk_hdmi_probe_regulators() - probe (autoset + enable) regulators
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*
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* Probes a list of regulators by performing autoset and enable
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* operations on them. The list of regulators is an array of string
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* pointers and any individual regulator-probe may fail without
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* counting as an error.
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*
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* @dev: device
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* @names: array of string-pointers to regulator names to probe
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* @cnt: number of elements in the 'names' array
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*/
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void rk_hdmi_probe_regulators(struct udevice *dev,
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const char * const *names, int cnt);
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/**
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* rk_hdmi_ofdata_to_platdata() - common ofdata_to_platdata implementation
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*
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* @dev: device
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* @return 0 if OK, -ve if something went wrong
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*/
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int rk_hdmi_ofdata_to_platdata(struct udevice *dev);
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/**
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* rk_hdmi_probe() - common probe implementation
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*
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* Performs the following, common initialisation steps:
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* 1. checks for HPD (i.e. a HDMI monitor being attached)
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* 2. initialises the Designware HDMI core
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* 3. initialises the Designware HDMI PHY
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*
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* @dev: device
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* @return 0 if OK, -ve if something went wrong
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*/
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int rk_hdmi_probe(struct udevice *dev);
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#endif
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@ -25,8 +25,42 @@ struct rkvop_driverdata {
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void (*set_pin_polarity)(struct udevice *, enum vop_modes, u32);
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};
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/**
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* rk_vop_probe() - common probe implementation
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*
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* Performs the rk_display_init on each port-subnode until finding a
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* working port (or returning an error if none of the ports could be
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* successfully initialised).
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*
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* @dev: device
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* @return 0 if OK, -ve if something went wrong
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*/
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int rk_vop_probe(struct udevice *dev);
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/**
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* rk_vop_bind() - common bind implementation
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*
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* Sets the plat->size field to the amount of memory to be reserved for
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* the framebuffer: this is always
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* (32 BPP) x VIDEO_ROCKCHIP_MAX_XRES x VIDEO_ROCKCHIP_MAX_YRES
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*
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* @dev: device
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* @return 0 (always OK)
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*/
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int rk_vop_bind(struct udevice *dev);
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/**
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* rk_vop_probe_regulators() - probe (autoset + enable) regulators
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*
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* Probes a list of regulators by performing autoset and enable
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* operations on them. The list of regulators is an array of string
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* pointers and any individual regulator-probe may fail without
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* counting as an error.
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*
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* @dev: device
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* @names: array of string-pointers to regulator names to probe
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* @cnt: number of elements in the 'names' array
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*/
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void rk_vop_probe_regulators(struct udevice *dev,
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const char * const *names, int cnt);
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@ -5,5 +5,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve.o ../videomodes.o
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obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o ../videomodes.o
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obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
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@ -56,7 +56,7 @@ static void sunxi_de2_composer_init(void)
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}
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static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
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int bpp, ulong address)
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int bpp, ulong address, bool is_composite)
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{
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ulong de_mux_base = (mux == 0) ?
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SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
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@ -72,6 +72,9 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
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(struct de_ui *)(de_mux_base +
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SUNXI_DE2_MUX_CHAN_REGS +
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SUNXI_DE2_MUX_CHAN_SZ * 1);
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struct de_csc * const de_csc_regs =
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(struct de_csc *)(de_mux_base +
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SUNXI_DE2_MUX_DCSC_REGS);
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u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
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int channel;
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u32 format;
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@ -128,7 +131,27 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
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writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_DCSC_REGS);
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if (is_composite) {
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/* set CSC coefficients */
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writel(0x107, &de_csc_regs->coef11);
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writel(0x204, &de_csc_regs->coef12);
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writel(0x64, &de_csc_regs->coef13);
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writel(0x4200, &de_csc_regs->coef14);
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writel(0x1f68, &de_csc_regs->coef21);
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writel(0x1ed6, &de_csc_regs->coef22);
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writel(0x1c2, &de_csc_regs->coef23);
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writel(0x20200, &de_csc_regs->coef24);
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writel(0x1c2, &de_csc_regs->coef31);
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writel(0x1e87, &de_csc_regs->coef32);
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writel(0x1fb7, &de_csc_regs->coef33);
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writel(0x20200, &de_csc_regs->coef34);
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/* enable CSC unit */
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writel(1, &de_csc_regs->csc_ctl);
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} else {
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writel(0, &de_csc_regs->csc_ctl);
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}
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switch (bpp) {
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case 16:
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@ -153,7 +176,7 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
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static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
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enum video_log2_bpp l2bpp,
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struct udevice *disp, int mux)
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struct udevice *disp, int mux, bool is_composite)
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{
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct display_timing timing;
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@ -183,7 +206,7 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
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}
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sunxi_de2_composer_init();
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sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase);
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sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
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ret = display_enable(disp, 1 << l2bpp, &timing);
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if (ret) {
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@ -204,7 +227,6 @@ static int sunxi_de2_probe(struct udevice *dev)
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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struct udevice *disp;
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int ret;
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int mux;
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/* Before relocation we don't need to do anything */
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if (!(gd->flags & GD_FLG_RELOC))
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@ -212,17 +234,31 @@ static int sunxi_de2_probe(struct udevice *dev)
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ret = uclass_find_device_by_name(UCLASS_DISPLAY,
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"sunxi_dw_hdmi", &disp);
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if (!ret) {
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int mux;
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if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
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mux = 0;
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else
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mux = 1;
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
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false);
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if (!ret) {
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video_set_flush_dcache(dev, 1);
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return 0;
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}
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}
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debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
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ret = uclass_find_device_by_name(UCLASS_DISPLAY,
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"sunxi_tve", &disp);
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if (ret) {
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debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
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debug("%s: tv not found (ret=%d)\n", __func__, ret);
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return ret;
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}
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if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
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mux = 0;
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else
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mux = 1;
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux);
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
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if (ret)
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return ret;
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