Commit graph

25222 commits

Author SHA1 Message Date
Chanho Park
83b443df26 riscv: import read/write_relaxed functions
This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02 17:45:53 +08:00
Heinrich Schuchardt
9757cae991 riscv: allow resume after exception
If CSRs like seed are readable by S-mode, may not be determinable by
S-mode. For safe driver probing allow to resume via a longjmp after an
exception.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02 16:22:06 +08:00
Chanho Park
37c2faf325 riscv: cpu: jh7110: Add gpio helper macros
Add gpio.h header file that includes JH7110 helper macros. The file is
imported from StarFive github[1] with small changes such as alignment.

[1]: https://github.com/starfive-tech/u-boot

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02 15:44:56 +08:00
Samuel Holland
bade208b5d riscv: Weakly define invalidate_icache_range()
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02 15:15:54 +08:00
Samuel Holland
3b00fab616 riscv: Align the trap handler to 64 bytes
This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02 15:15:46 +08:00
Samuel Holland
a6a77e4734 riscv: Sort target configs alphabetically
Clean things up for the next time somebody adds a target.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02 15:15:33 +08:00
Michal Simek
18370f1497 Kconfig: Remove all default n/no options
Similar change was done by commit b4c2c151b1 ("Kconfig: Remove all
default n/no options") and again sync is required.

default n/no doesn't need to be specified. It is default option anyway.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
2023-10-30 15:32:49 -04:00
Martin Fäcknitz
e9bf0ce6c1 mpc85xx: relocate code in non-SPL build
When building a non-SPL image, relocation is needed. This patch restores
the old behaviour before commit b35316fb67 ("Convert
CONFIG_SPL_INIT_MINIMAL et al to Kconfig") was only defined if
CONFIG_SPL_BUILD was defined.

Fixes: b35316fb67 ("Convert CONFIG_SPL_INIT_MINIMAL et al to Kconfig")
Signed-off-by: Martin Fäcknitz <faecknitz@hotsplots.de>
2023-10-28 09:17:55 -04:00
Tom Rini
d5d9770f58 bootX measurements and measurement API moved to u-boot core
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Merge tag 'tpm-next-27102023' of https://source.denx.de/u-boot/custodians/u-boot-tpm

bootX measurements and measurement API moved to u-boot core:

Up to now, U-Boot could perform measurements and EventLog creation as
described by the TCG spec when booting via EFI.

The EFI code was residing in lib/efi_loader/efi_tcg2.c and contained
both EFI specific code + the API needed to access the TPM, extend PCRs
and create an EventLog. The non-EFI part proved modular enough and
moving it around to the TPM subsystem was straightforward.

With that in place we can have a common API for measuring binaries
regardless of the boot command, EFI or boot(m|i|z), and contructing an
EventLog.

I've tested all of the EFI cases -- booting with an empty EventLog and
booting with a previous stage loader providing one and found no
regressions.  Eddie tested the bootX part.

Eddie also fixed the sandbox TPM which couldn't be used for the EFI code
and it now supports all the required capabilities. This had a slight
sideeffect in our testing since the EFI subsystem initializes the TPM
early and 'tpm2 init' failed during some python tests. That code only
opens the device though, so we can replace it with 'tpm2 autostart'
which doesn't error out and still allows you to perfom the rest of the
tests but doesn't report an error if the device is already opened.

There's a few minor issues with this PR as well but since testing and
verifying the changes takes a considerable amount of time, I prefer
merging it now.

Heinrich has already sent a PR for -master containing "efi_loader: fix
EFI_ENTRY point on get_active_pcr_banks" and I am not sure if that will
cause any conflicts, but in any case they should be trivial to resolve.

Both the EFI and non-EFI code have a Kconfig for measuring the loaded
Device Tree.  The reason this is optional is that we can't reason
when/if devices add random info like kaslr-seed, mac addresses etc in
the DT. In that case measurements are random, board specific and
eventually useless.  The reason it was difficult to fix it prior to this
patchset is because the EFI subsystem and thus measurements was brought
up late and DT fixups might have already been applied. With this
patchset we can measure the DT really early in the future.

Heinrich also pointed out that the two Kconfigs for the DTB measurements
can be squashed in a single one and that the documentation only explains
the non-EFI case.  I agree on both but as I said this is a sane working
version, so let's pull this first it's aleady big enough and painful to
test.
2023-10-27 19:27:29 -04:00
Eddie James
5999ea20fa test: Add sandbox TPM boot measurement
Use the sandbox TPM driver to measure some boot images in a unit
test case.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-10-27 13:17:21 +03:00
Josua Mayer
a5539f976b arm: mvebu: allow additional 4096 offset for bootable mmc image
Disarm the error message forcing u-boot/spl image to be located at
sector 0 on eMMC data-partition and microSD.
Offset 0 makes sense on eMMC boot partitions only, data partition must
use 4096 to avoid conflicting with MBR.

Valid offsets when booting from microSD, reported by boot-rom v1.73:

BootROM: Bad header at offset 00000200
BootROM: Bad header at offset 00004400
BootROM: Bad header at offset 00200000
BootROM: Bad header at offset 00400000
BootROM: Bad header at offset 00600000
BootROM: Bad header at offset 00800000
BootROM: Bad header at offset 00A00000
BootROM: Bad header at offset 00C00000
BootROM: Bad header at offset 00E00000
BootROM: Bad header at offset 01000000
BootROM: Bad header at offset 01200000
BootROM: Bad header at offset 01400000
BootROM: Bad header at offset 01600000
BootROM: Bad header at offset 01800000
BootROM: Bad header at offset 01A00000
BootROM: Bad header at offset 01C00000
BootROM: Bad header at offset 01E00000
BootROM: Bad header at offset 02000000
BootROM: Bad header at offset 02200000
BootROM: Bad header at offset 02400000
BootROM: Bad header at offset 02600000
BootROM: Bad header at offset 02800000
BootROM: Bad header at offset 02A00000
BootROM: Bad header at offset 02C00000
BootROM: Bad header at offset 02E00000

Valid offsets when booting from eMMC:

BootROM: Bad header at offset 00000000
BootROM: Bad header at offset 00200000
Switching BootPartitions.
BootROM: Bad header at offset 00000000
BootROM: Bad header at offset 00200000

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")

Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-26 14:49:36 +02:00
Marek Behún
94c0f0b177 arm: mvebu: turris_mox: Extend to support RIPE Atlas Probe
Extend Turris Mox board code to support CZ.NIC's RIPE Atlas Probe.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-26 14:49:36 +02:00
AKASHI Takahiro
8e545b3781 sandbox: add SCMI power domain protocol support for testing
SCMI power domain management protocol is supported on sandbox
for test purpose. Add fake agent interfaces and associated
power domain devices.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-24 17:05:24 -04:00
Alexander Gendin
04291ee0ab cmd: mbr: Allow 4 MBR partitions without need for extended
Current code allows up to 3 MBR partitions without extended one.
If more than 3 partitions are required, then extended partition(s)
must be used.
This commit allows up to 4 primary MBR partitions without the
need for extended partition.

Add mbr test unit. In order to run the test manually, mmc6.img file
of size 12 MiB or greater is required in the same directory as u-boot.
Test also runs automatically via ./test/py/test.py tool.
Running mbr test is only supported in sandbox mode.

Signed-off-by: Alex Gendin <agendin@matrox.com>
[ And due to some further changes for testing ]
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-10-24 17:05:24 -04:00
Tom Rini
0b9441ae76 riscv: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-10-24 16:34:45 -04:00
Tom Rini
8991fed97d mips: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-24 16:34:45 -04:00
Tom Rini
577dddb5b7 microblaze: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Michal Simek <michal.simek@amd.com>
2023-10-24 16:34:45 -04:00
Tom Rini
07011890a6 m68k: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
2023-10-24 16:34:45 -04:00
Tom Rini
60c08dd771 arc: Remove common.h usage
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2023-10-24 16:34:45 -04:00
Tom Rini
5cab3515f8 Merge tag 'u-boot-rockchip-20231024' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add Board: rk3588 NanoPC-T6, Orange Pi 5, Orange Pi 5 Plus;
- clk driver fix for rk3568 and rk3588;
- rkmtd cmd support for rockchip nand device;
- dts update and sync from linux;
2023-10-24 09:39:52 -04:00
Tom Rini
1b2a3d08c0 u-boot-imx-20231024
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18211
 
 - Fixes for MC2432 Eeprom
 - i.MX93 ADC
 - Secondary boot mode on i.MX8M
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Merge tag 'u-boot-imx-20231024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20231024
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18211

- Fixes for MC2432 Eeprom
- i.MX93 ADC
- Secondary boot mode on i.MX8M
2023-10-24 09:39:02 -04:00
Jonas Karlman
b51cf8bb09 board: rockchip: Add Xunlong Orange Pi 5 Plus
Xunlong Orange Pi 5 Plus is a single-board computer based on the
Rockchip RK3588 SoC. The board provides abundant interfaces, including
two HDMI output ports, one HDMI input port, two 2.5G Ethernet ports,
M.2 M-Key slot, M.2 E-Key slot, two USB 3.0, two USB 2.0, and two Type-C.

Features tested on a Orange Pi 5 Plus 4GB v1.2:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet

Device tree is imported from linux v6.7-rockchip-dts64-1 tag.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
28c5f941ed board: rockchip: Add Xunlong Orange Pi 5
Xunlong Orange Pi 5 is a single-board computer based on the Rockchip
RK3588S SoC. The board provides abundant interfaces, HDMI output, GPIO
interface, M.2 PCIe2.0, Type-C, Gigabit LAN port, 2*USB2.0, 1*USB3.0,
etc.

Features tested on a Orange Pi 5 4GB v1.2:
- SD-card boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet

Device tree is imported from linux v6.7-rockchip-dts64-1 tag.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
c1710bfc4f rockchip: rk3588-rock-5b: Sync USB3 nodes from mainline linux patches
The device tree for rk3588 and rock-5b contain usb3 nodes that have
deviated too much from current state of submitted mainline linux usb3
patches, see [1].

Sync usb3 related nodes from latest patches and collaboras rk3588 tree
so that dwc3-generic driver can be updated to include support for the
rockchip,rk3588-dwc3 compatible in the future, use rockchip,rk3568-dwc3
compatible until final node is merged in linux maintainer tree.

[1] https://lore.kernel.org/lkml/20231009172129.43568-1-sebastian.reichel@collabora.com/

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Jonas Karlman
57379c0021 rockchip: rk3588: Sync device tree from v6.7-rockchip-dts64-1 tag
Sync rk3588 device tree from v6.7-rockchip-dts64-1 tag.

Adds PCIe, button and led nodes to rk3588-evb1-v10 and rk3588-rock-5b
boards. Also remove includes from u-boot.dtsi-files that is no longer
needed.

Linux commits:
42145b7a8235 ("arm64: dts: rockchip: add PCIe network controller to rock-5b")
199cbd5f195a ("arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b")
da447ec38780 ("arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b")
86a2024d95e2 ("arm64: dts: rockchip: add PCIe2 network controller to rk3588-evb1")
46bb398ea1d8 ("arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1")
1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b")
3eaf2abd11aa ("arm64: dts: rockchip: Add sfc node to rk3588s")
bf012368bb0a ("arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s")
3d77a3e51b0f ("arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s")
0002c377e862 ("arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf from rock-5b")
a6169ab36923 ("arm64: dts: rockchip: Enable UART6 on rock-5b")
dd6dc0c4c126 ("arm64: dts: rockchip: Add AV1 decoder node to rk3588s")
afa933c208e5 ("arm64: dts: rockchip: add ADC buttons to rk3588-evb1")
7952cbbda301 ("arm64: dts: rockchip: add status LED to rock-5b")

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-24 15:55:16 +08:00
Tom Rini
cedc741231 Second set of u-boot-at91 features for the 2024.01 cycle
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Merge tag 'u-boot-at91-2024.01-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2024.01 cycle

This feature set a new board named Conclusive KSTR sama5d27 with some
small prerequisites patches.
2023-10-23 11:39:38 -04:00
Tom Rini
a8f6dab0d4 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
This is mostly about support for the Allwinner R528/T113s SoC, which is
reportedly the same die as the Allwinner D1, but with the two
Arm Cortex-A7 cores activated instead of the RISC-V one.
Using sunxi code outside of arch/arm proved to be difficult, so apart
from enabling this Arm SoC, the patches also prepare for more refactoring
to get the D1 nicely supported some day:
- We get rid of some Kconfig (hard-)coded GPIO pins, responsible for
  enabling regulators.
- The GPIO code is moved out of arch/arm, into drivers/gpio.
- Some definitions are moved out of header files under asm/arch.
- Some T113s/D1 specific definitions are guarded by a generic Kconfig
  symbol (CONFIG_SUNXI_GEN_NCAT2).
- The DRAM controller initialisation code is located under drivers/ram.
- The base SoC .dtsi files are shared (under arch/riscv, as in Linux).

Of course there are also the usual new SoC specific patches, like clock
and pinmux descriptions, alongside a rework of the pinctrl code, since
Allwinner changed the GPIO register layout, for the first time since
sunxi's inception.
On top of this the PSCI code sees some update, to provide SMP services
for R528/T113s boards. Many thanks to Sam for providing this code and
staying strong through the review cycles.
The final patch enables support for one popular board, I hope to see
more DTs and defconfigs contributed in the future!

Many thanks to all the various contributors, testers and reviewers,
that series was a real team effort!
2023-10-23 11:39:33 -04:00
Artur Rojek
27347893f0 board: Add support for Conclusive KSTR-SAMA5D27
Introduce support for Conclusive KSTR-SAMA5D27 Single Board Computer.

Co-developed-by: Jakub Klama <jakub@conclusive.pl>
Signed-off-by: Jakub Klama <jakub@conclusive.pl>
Co-developed-by: Marcin Jabrzyk <marcin@conclusive.pl>
Signed-off-by: Marcin Jabrzyk <marcin@conclusive.pl>
Signed-off-by: Artur Rojek <artur@conclusive.pl>
2023-10-23 17:07:06 +03:00
Artur Rojek
a6965af7e4 arm: dts: at91: sama5: Add flexcom4 node
Set up flexcom4 for Microchip SAMA5D27 SoC and prepare it for usage in
I2C mode.

Signed-off-by: Artur Rojek <artur@conclusive.pl>
2023-10-23 17:07:06 +03:00
Tom Rini
0339e81be1 - sync A1 with Linux and add missing UART compatible
- fix USB2 gadget init on G12/SM1 based Boards
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Merge tag 'u-boot-amlogic-20231023' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- sync A1 with Linux and add missing UART compatible
- fix USB2 gadget init on G12/SM1 based Boards
2023-10-23 09:04:17 -04:00
Matwey V. Kornilov
ad84cc8678 rockchip: dts: rk3328: Sync rock64 device tree file from Linux
Sync the rk3328-rock64 dts from v6.6-rc5.

See Linux kernel commit for details:

    03633c4ef1fb ("arm64: dts: rockchip: fix USB regulator on ROCK64")

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23 18:21:55 +08:00
John Clark
b0b8086898 board: rockchip: add FriendlyElec NanoPC-T6 rk3588 board
The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec.

There are four variants depending on the DRAM size: 4G/32GB eMMC,
8G/64GB eMMC, 16G/16MB SPI NOR, and 16G/256GB eMMC/16MB SPI NOR

Specifications:
    CPU: Rockchip RK3588, 4x Cortex-A76 (up to 2.4GHz)
                        + 4x Cortex-A55 (up to 1.8GHz)
    GPU: Mali-G610 MP4
    VPU: 8K@60fps H.265 and VP9 decoder, 8K@30fps H.264 decoder,
         4K@60fps AV1 decoder, 8K@30fps H.264 and H.265 encoder
    NPU: 6TOPs, supports INT4/INT8/INT16/FP16
    RAM: 64-bit 4GB/8GB/16GB LPDDR4X at 2133MHz
    eMMC: 0GB/32GB/64GB/256GB HS400
    MicroSD Slot: MicroSD SDR104
    PCIe 3.0: M.2 M-Key x1, PCIe 3.0 x4 for NVMe SSDs up to 2,500 MB/s
    Ethernet: PCIe 2.5G 2x Ethernet (RTL8125BG)
    PCIe 2.1: M.2 E-Key x1, PCIe 2.1 x1 and USB2.0 Host,
              supports M.2 WiFi and Bluetooth
    4G Module: MiniPCIe x1, MicroSIM Card Slot x1
    Audio Out: 3.5mm jack for stereo headphone output
    Audio In: 2.0mm PH-2A connector for analog microphone input
    Video Input: standard HDMI input port, up to 4Kp60
    2x 4-lane MIPI-CSI, compatible with MIPI V1.2
    Video Output: 2x standard HDMI output ports compatible with HDMI2.1,
                  HDMI2.0, and HDMI1.4
    2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1
    USB-A: USB 3.0, Type A
    USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0
    40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs,
                                    8x PWMs, 2x I2Ss, 28x GPIOs
    Debug UART: 3 Pin 2.54mm header, 3V level, 1500000bps
    Onboard IR receiver: 38KHz carrier frequency
    RTC Battery: 2 Pin 1.27/1.25mm RTC battery connector for low power
                 RTC IC HYM8563TS
    5V Fan connector
    Working Temperature: 0C to 70C
    Power: 5.5*2.1mm DC Jack, 12VDC input
    Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)

Kernel commits:
893c17716d0c ("arm64: dts: rockchip: Add NanoPC T6")
a721e28dfad2 ("arm64: dts: rockchip: Add NanoPC T6 PCIe Ethernet support")
ac76b786cc37 ("arm64: dts: rockchip: Add NanoPC T6 PCIe e-key support")

Signed-off-by: John Clark <inindev@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23 18:21:55 +08:00
Jonas Karlman
de7f4bb1f1 rockchip: rk3568-radxa-e25: Enable pcie3x1 node
Enable mini PCIe slot, pcie3x1 node, now that the PCIe PHY driver
support bifurcation.

A pinctrl is assigned for reset-gpios or the device may freeze running
pci enum and nothing is connected to the mini PCIe slot.

Also drop the AHCI_PCI Kconfig option as this option is not required for
a functional M.2 SATA drive slot.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23 18:21:55 +08:00
Andre Przywara
fa066df62e sunxi: add MangoPi MQ-R board support
The MangoPi MQ-R board uses an Allwinner T113s Soc (with 128MB of
embedded DRAM), support for which was just added to the code.

Since the devicetree was already synced from the latest Linux kernel
tree, all we need is a _defconfig file to add support for the board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-23 01:00:56 +01:00
Sam Edwards
352ba256da sunxi: psci: implement PSCI on R528
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Tested-by: Maksim Kiselev <bigunclemax@gmail.com>
Tested-by: Kevin Amadiva <kevin.amadiva@mec.at>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Sam Edwards
b1fbc20e76 sunxi: psci: stop modeling register layout with C structs
Since the sunxi support nowadays generally prefers #defined register
offsets instead of modeling register layouts using C structs, now is a
good time to do this for PSCI as well. This patch moves away from using
the structs `sunxi_cpucfg_reg` and `sunxi_prcm_reg` in psci.c.

The former struct and its associated header file existed only to support
PSCI code, so also delete them altogether.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Sam Edwards
3f31c6f103 sunxi: psci: refactor register access to separate functions
This is to prepare for R528, which does not have the typical
"CPUCFG" block; it has a "CPUX" block which provides these
same functions but is organized differently.

Moving the hardware-access bits to their own functions separates the
logic from the hardware so we can reuse the same logic.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Sam Edwards
f9670d7b0b sunxi: psci: clean away preprocessor macros
This patch restructures psci.c to get away from the "many different
function definitions switched by #ifdef" paradigm to the preferred style
of having a single function definition with `if (IS_ENABLED(...))` to
make the optimizer include only the appropriate function bodies instead.

There are no functional changes here.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Andre Przywara
beeace9ba1 sunxi: refactor serial base addresses to avoid asm/arch/cpu.h
At the moment we have each SoC's memory map defined in its own cpu.h,
which is included in include/configs/sunxi_common.h. This will be a
problem with the introduction of Allwinner RISC-V support.

Remove the inclusion of that header file from the common config header,
instead move the required serial base addresses (for the SPL) into a
separate header file. Then include the original cpu.h file only where
we really need it, which is only under arch/arm now.

This disentangles the architecture specific header files from the
generic code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Andre Przywara
95168d77d3 sunxi: add Allwinner R528/T113 SoC support
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Andre Przywara
a94c9c809b sunxi: clock: support D1/R528 PLL6 clock
The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is
new P0 divider at bits [18:16], and the M divider is 1.

Add code to support this version of "PLL6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:51 +01:00
Andre Przywara
39ba474698 sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup
The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
Just enable that when we program that PLL.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:51 +01:00
Andre Przywara
4a9e89a3e3 sunxi: introduce NCAT2 generation model
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the clock controller significantly. We added a
CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits.

Now the Allwinner D1 changes the memory map again, and also extends the
pincontroller, among other peripherals.
To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
this name is reportedly used in the Allwinner BSP code, and prevents us
from inventing our own name.

Add this new symbol to some guards that were already checking for the H6
generation, since many features are shared between the two (like the
renovated clock controller).

This paves the way to introduce a first user of this generation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:41:46 +01:00
Andre Przywara
1da48c99de pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h
On the Allwinner platform we were describing a quite comprehensive
memory map in a per-SoC header unser arch/arm.
In the old days that was used by every driver, but nowadays it should
only be needed by SPL drivers (not using the DT). Many addresses in
there were never used, and some are not needed anymore.

To avoid a dependency on CPU specific headers in an arch specific
directory, move the definition of the pinctroller MMIO base address into
the sunxi_gpio.h header, because the SPL routines for GPIO should be the
only one needing this address.
This is a first step towards getting rid of cpu_sun[x]i.h completely,
and allows to remove the inclusion of that file from the sunxi_gpio.h
header.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:40:57 +01:00
Andre Przywara
207ed0a3dd pinctrl: sunxi: remove GPIO_EXTRA_HEADER
U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code
to more easily include platform specific GPIO headers. This should not
be needed in a DM world anymore, since the generic GPIO framework
handles that nicely.
For Allwinner boards we still need to deal with non-DM GPIO in the SPL,
but this should become the exception, not the rule.

Make this more obvious by removing the definition of GPIO_EXTRA_HEADER,
and just force every legacy user of platform specific GPIO to include
the new sunxi_gpio.h header explicitly. Everyone doing so should feel
ashamed and should find a way to avoid it from now on.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:57 +01:00
Andre Przywara
30097ee3d2 pinctrl: sunxi: remove struct sunxi_gpio
So far every Allwinner SoC used the same basic pincontroller/GPIO
register frame, and just differed by the number of implemented banks and
pins, plus some special functionality from time to time. However the D1
and successors use a slightly different pinctrl register layout.
Use that opportunity to drop "struct sunxi_gpio", that described that
MMIO frame in a C struct. That approach is somewhat frowned upon in the
Linux world and rarely used there, though still popular with U-Boot.

Switching from a C struct to a "base address plus offset" approach allows
to switch between the two models more dynamically, without reverting to
preprocessor macros and #ifdef's.

Model the pinctrl MMIO register frame in the usual "base address +
offset" way, and replace a hard-to-parse CPP macro with a more readable
static function.
All the users get converted over. There are no functional changes at
this point, it just prepares the stages for the D1 and friends.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:57 +01:00
Andre Przywara
20b78c55e7 pinctrl: sunxi: move pinctrl code
Move the existing sunxi-specific low level pinctrl routines from
arch/arm/mach-sunxi into the existing GPIO code under drivers/gpio, so
that the common code can be shared outside of arch/arm.

This also takes the opportunity to move some definitions from our
header file into the driver C file, as they are private to the driver
and are not needed elsewhere.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:56 +01:00
Andre Przywara
5ad98c57b8 sunxi: remove CONFIG_MACPWR
The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
the power for the Ethernet "MAC" (mostly PHY, really).
In the DT this is described with the phy-supply property in the MAC DT
node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
only in U-Boot proper, and use a DM driver there, we should use the DT
instead of hardcoding this.

Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
that regulator and enable it, at probe time. Then drop the current code
from board.c, which was doing that job before.
This allows us to remove the MACPWR Kconfig definition and the respective
values from the defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
2023-10-22 23:40:56 +01:00
Andre Przywara
ae79c1d01f sunxi: remove CONFIG_SATAPWR
The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
enables the power for a SATA harddisk.
In the DT this is described with the target-supply property in the AHCI
DT node, pointing to a (GPIO controlled) regulator. Since we need SATA
only in U-Boot proper, and use a DM driver for AHCI there, we should use
the DT instead of hardcoding this.

Add code to the sunxi AHCI driver to check the DT for that regulator and
enable it, at probe time. Then drop the current code from board.c, which
was doing that job before.
This allows us to remove the SATAPWR Kconfig definition and the
respective values from the defconfigs.
We also select the generic fixed regulator driver, which handles those
GPIO controlled regulators.

Please note that the OrangePi Plus is a bit special here, it's a H3
board without native SATA, but with a USB-to-SATA bridge. The DT models
the SATA power via a VBUS supply regulator, which we don't parse yet in
the USB PHY driver. Use the hardcoded CONFIG_USB3_VBUS_PIN for that
board meanwhile.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:47 +01:00
Andre Przywara
a14c250625 sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6
This copies in some devicetree files from the official Linux kernel tree,
v6.6-rc6. It covers a board with the Allwinner T113s SoC, which shares
many devices with its RISC-V sibling, the Allwinner D1(s). This is the
reason for the core .dtsi files landing in the arch/riscv directory.

We are only adjusting the include path to accommodate for the differences
in the U-Boot build system.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-10-22 01:12:26 +01:00