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riscv: Sort target configs alphabetically
Clean things up for the next time somebody adds a target. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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1 changed files with 9 additions and 9 deletions
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@ -14,6 +14,9 @@ config TARGET_ANDES_AE350
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config TARGET_MICROCHIP_ICICLE
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bool "Support Microchip PolarFire-SoC Icicle Board"
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config TARGET_OPENPITON_RISCV64
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bool "Support RISC-V cores on OpenPiton SoC"
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config TARGET_QEMU_VIRT
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bool "Support QEMU Virt Board"
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@ -24,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED
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bool "Support SiFive Unmatched Board"
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select SYS_CACHE_SHIFT_6
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config TARGET_SIPEED_MAIX
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bool "Support Sipeed Maix Board"
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select SYS_CACHE_SHIFT_6
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config TARGET_STARFIVE_VISIONFIVE2
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bool "Support StarFive VisionFive2 Board"
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select BOARD_LATE_INIT
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@ -32,13 +39,6 @@ config TARGET_TH1520_LPI4A
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bool "Support Sipeed's TH1520 Lichee PI 4A Board"
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select SYS_CACHE_SHIFT_6
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config TARGET_SIPEED_MAIX
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bool "Support Sipeed Maix Board"
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select SYS_CACHE_SHIFT_6
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config TARGET_OPENPITON_RISCV64
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bool "Support RISC-V cores on OpenPiton SoC"
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endchoice
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config SYS_ICACHE_OFF
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@ -76,12 +76,12 @@ config SPL_ZERO_MEM_BEFORE_USE
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source "board/AndesTech/ae350/Kconfig"
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source "board/emulation/qemu-riscv/Kconfig"
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source "board/microchip/mpfs_icicle/Kconfig"
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source "board/openpiton/riscv64/Kconfig"
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source "board/sifive/unleashed/Kconfig"
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source "board/sifive/unmatched/Kconfig"
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source "board/thead/th1520_lpi4a/Kconfig"
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source "board/openpiton/riscv64/Kconfig"
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source "board/sipeed/maix/Kconfig"
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source "board/starfive/visionfive2/Kconfig"
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source "board/thead/th1520_lpi4a/Kconfig"
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# platform-specific options below
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source "arch/riscv/cpu/andesv5/Kconfig"
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