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riscv: Weakly define invalidate_icache_range()

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Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Samuel Holland 2023-10-31 00:37:20 -05:00 committed by Leo Yu-Chi Liang
parent 3b00fab616
commit bade208b5d
1 changed files with 1 additions and 1 deletions
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arch/riscv/lib/cache.c
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@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end)
{
}
void invalidate_icache_range(unsigned long start, unsigned long end)
__weak void invalidate_icache_range(unsigned long start, unsigned long end)
{
/*
* RISC-V does not have an instruction for invalidating parts of the