Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-09-21 15:12:04 +00:00
Code Issues Projects Releases Packages Wiki Activity

riscv: Align the trap handler to 64 bytes

Browse source 
This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Samuel Holland 2023-10-31 00:35:41 -05:00 committed by Leo Yu-Chi Liang
parent a6a77e4734
commit 3b00fab616
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/riscv/cpu/mtrap.S
View file

@ -26,7 +26,7 @@
.text
/* trap entry */
.align 2
.align 6
.global trap_entry
trap_entry:
addi sp, sp, -32 * REGBYTES