mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 13:43:28 +00:00
Merge patch series "Add support for MediaTek MT8365 EVK Board"
Julien Masson <jmasson@baylibre.com> says: This patch series add the support for the MediaTek MT8365 EVK Board [1]. Most of the code have been copied/adapted from Linux tag v6.7-rc2. For now we only enable/test these features: Boot, UART, Watchdog and MMC. [trini: This includes two clocks not listed in the Linux binding, which needs resyncing later]
This commit is contained in:
Tom Rini
commit
9cfef5fcfb
18 changed files with 3698 additions and 0 deletions
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@ -411,6 +411,8 @@ F: drivers/watchdog/mtk_wdt.c
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F: drivers/net/mtk_eth.c
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F: drivers/net/mtk_eth.h
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F: drivers/reset/reset-mediatek.c
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F: include/dt-bindings/clock/mediatek,*
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F: include/dt-bindings/power/mediatek,*
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F: tools/mtk_image.c
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F: tools/mtk_image.h
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F: tools/mtk_nand_headers.c
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|
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282
arch/arm/dts/mt6357.dtsi
Normal file
282
arch/arm/dts/mt6357.dtsi
Normal file
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@ -0,0 +1,282 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Copyright (c) 2023 BayLibre Inc.
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*/
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#include <dt-bindings/input/input.h>
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&pwrap {
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mt6357_pmic: pmic {
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compatible = "mediatek,mt6357";
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regulators {
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mt6357_vproc_reg: buck-vproc {
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regulator-name = "vproc";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vcore_reg: buck-vcore {
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regulator-name = "vcore";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vmodem_reg: buck-vmodem {
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regulator-name = "vmodem";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1193750>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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};
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mt6357_vs1_reg: buck-vs1 {
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regulator-name = "vs1";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <2200000>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vpa_reg: buck-vpa {
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regulator-name = "vpa";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3650000>;
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regulator-ramp-delay = <50000>;
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regulator-enable-ramp-delay = <220>;
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};
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mt6357_vfe28_reg: ldo-vfe28 {
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compatible = "regulator-fixed";
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regulator-name = "vfe28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vxo22_reg: ldo-vxo22 {
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regulator-name = "vxo22";
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regulator-min-microvolt = <2200000>;
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regulator-max-microvolt = <2400000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vrf18_reg: ldo-vrf18 {
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compatible = "regulator-fixed";
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regulator-name = "vrf18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vrf12_reg: ldo-vrf12 {
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compatible = "regulator-fixed";
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regulator-name = "vrf12";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vefuse_reg: ldo-vefuse {
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regulator-name = "vefuse";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn33_bt_reg: ldo-vcn33-bt {
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regulator-name = "vcn33-bt";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3500000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {
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regulator-name = "vcn33-wifi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3500000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn28_reg: ldo-vcn28 {
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compatible = "regulator-fixed";
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regulator-name = "vcn28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn18_reg: ldo-vcn18 {
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compatible = "regulator-fixed";
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regulator-name = "vcn18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcama_reg: ldo-vcama {
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regulator-name = "vcama";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcamd_reg: ldo-vcamd {
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regulator-name = "vcamd";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcamio_reg: ldo-vcamio18 {
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compatible = "regulator-fixed";
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regulator-name = "vcamio";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vldo28_reg: ldo-vldo28 {
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regulator-name = "vldo28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <3000000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vsram_others_reg: ldo-vsram-others {
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regulator-name = "vsram-others";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <110>;
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regulator-always-on;
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};
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mt6357_vsram_proc_reg: ldo-vsram-proc {
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regulator-name = "vsram-proc";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <110>;
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regulator-always-on;
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};
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mt6357_vaux18_reg: ldo-vaux18 {
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compatible = "regulator-fixed";
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regulator-name = "vaux18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vaud28_reg: ldo-vaud28 {
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compatible = "regulator-fixed";
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regulator-name = "vaud28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vio28_reg: ldo-vio28 {
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compatible = "regulator-fixed";
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regulator-name = "vio28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vio18_reg: ldo-vio18 {
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compatible = "regulator-fixed";
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regulator-name = "vio18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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regulator-always-on;
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};
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mt6357_vdram_reg: ldo-vdram {
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regulator-name = "vdram";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1200000>;
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regulator-enable-ramp-delay = <3300>;
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};
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mt6357_vmc_reg: ldo-vmc {
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regulator-name = "vmc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vmch_reg: ldo-vmch {
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regulator-name = "vmch";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vemc_reg: ldo-vemc {
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regulator-name = "vemc";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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regulator-always-on;
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};
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mt6357_vsim1_reg: ldo-vsim1 {
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regulator-name = "vsim1";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vsim2_reg: ldo-vsim2 {
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regulator-name = "vsim2";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vibr_reg: ldo-vibr {
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regulator-name = "vibr";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vusb33_reg: ldo-vusb33 {
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regulator-name = "vusb33";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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};
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rtc {
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compatible = "mediatek,mt6357-rtc";
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};
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keys {
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compatible = "mediatek,mt6357-keys";
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key-power {
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linux,keycodes = <KEY_POWER>;
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wakeup-source;
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};
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key-home {
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linux,keycodes = <KEY_HOME>;
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wakeup-source;
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};
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};
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};
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};
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418
arch/arm/dts/mt8365-evk.dts
Normal file
418
arch/arm/dts/mt8365-evk.dts
Normal file
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@ -0,0 +1,418 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021-2022 BayLibre, SAS.
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* Authors:
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* Fabien Parent <fparent@baylibre.com>
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* Bernhard Rosenkränzer <bero@baylibre.com>
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||||
*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
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#include "mt8365.dtsi"
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#include "mt6357.dtsi"
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/ {
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model = "MediaTek MT8365 Open Platform EVK";
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compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:921600n8";
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};
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firmware {
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||||
optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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||||
};
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||||
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||||
gpio-keys {
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||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys>;
|
||||
|
||||
key-volume-up {
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||||
gpios = <&pio 24 GPIO_ACTIVE_LOW>;
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||||
label = "volume_up";
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linux,code = <KEY_VOLUMEUP>;
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wakeup-source;
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||||
debounce-interval = <15>;
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||||
};
|
||||
};
|
||||
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memory@40000000 {
|
||||
device_type = "memory";
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||||
reg = <0 0x40000000 0 0xc0000000>;
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||||
};
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||||
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||||
usb_otg_vbus: regulator-0 {
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||||
compatible = "regulator-fixed";
|
||||
regulator-name = "otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
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||||
ranges;
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||||
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
bl31_secmon_reserved: secmon@43000000 {
|
||||
no-map;
|
||||
reg = <0 0x43000000 0 0x30000>;
|
||||
};
|
||||
|
||||
/* 12 MiB reserved for OP-TEE (BL32)
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||||
* +-----------------------+ 0x43e0_0000
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||||
* | SHMEM 2MiB |
|
||||
* +-----------------------+ 0x43c0_0000
|
||||
* | | TA_RAM 8MiB |
|
||||
* + TZDRAM +--------------+ 0x4340_0000
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||||
* | | TEE_RAM 2MiB |
|
||||
* +-----------------------+ 0x4320_0000
|
||||
*/
|
||||
optee_reserved: optee@43200000 {
|
||||
no-map;
|
||||
reg = <0 0x43200000 0 0x00c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
proc-supply = <&mt6357_vproc_reg>;
|
||||
sram-supply = <&mt6357_vsram_proc_reg>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
proc-supply = <&mt6357_vproc_reg>;
|
||||
sram-supply = <&mt6357_vsram_proc_reg>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
proc-supply = <&mt6357_vproc_reg>;
|
||||
sram-supply = <&mt6357_vsram_proc_reg>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
proc-supply = <&mt6357_vproc_reg>;
|
||||
sram-supply = <&mt6357_vsram_proc_reg>;
|
||||
};
|
||||
|
||||
ðernet {
|
||||
pinctrl-0 = <ðernet_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy-handle = <ð_phy>;
|
||||
phy-mode = "rmii";
|
||||
/*
|
||||
* Ethernet and HDMI (DSI0) are sharing pins.
|
||||
* Only one can be enabled at a time and require the physical switch
|
||||
* SW2101 to be set on LAN position
|
||||
* mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
|
||||
*/
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eth_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
hs400-ds-delay = <0x12012>;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
pinctrl-0 = <&mmc0_default_pins>;
|
||||
pinctrl-1 = <&mmc0_uhs_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
vmmc-supply = <&mt6357_vemc_reg>;
|
||||
vqmmc-supply = <&mt6357_vio18_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
|
||||
max-frequency = <200000000>;
|
||||
pinctrl-0 = <&mmc1_default_pins>;
|
||||
pinctrl-1 = <&mmc1_uhs_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-sdr50;
|
||||
vmmc-supply = <&mt6357_vmch_reg>;
|
||||
vqmmc-supply = <&mt6357_vmc_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mt6357_pmic {
|
||||
interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
&pio {
|
||||
ethernet_pins: ethernet-pins {
|
||||
phy_reset_pins {
|
||||
pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
|
||||
};
|
||||
|
||||
rmii_pins {
|
||||
pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
|
||||
<MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
|
||||
<MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
|
||||
<MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
|
||||
<MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
|
||||
<MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
|
||||
<MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
|
||||
<MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
|
||||
<MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
|
||||
<MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
|
||||
<MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
|
||||
<MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
|
||||
<MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
|
||||
<MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
|
||||
<MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
|
||||
<MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys: gpio-keys-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
|
||||
<MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_default_pins: mmc0-default-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
|
||||
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
|
||||
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
|
||||
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
|
||||
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
|
||||
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
|
||||
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
|
||||
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
|
||||
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_uhs_pins: mmc0-uhs-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
|
||||
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
|
||||
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
|
||||
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
|
||||
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
|
||||
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
|
||||
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
|
||||
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
|
||||
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
ds-pins {
|
||||
pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_default_pins: mmc1-default-pins {
|
||||
cd-pins {
|
||||
pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
|
||||
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
|
||||
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
|
||||
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
|
||||
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_uhs_pins: mmc1-uhs-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
|
||||
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
|
||||
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
|
||||
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
|
||||
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
|
||||
<MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: uart1-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
|
||||
<MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
|
||||
<MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_pins: usb-pins {
|
||||
id-pins {
|
||||
pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usb0-vbus-pins {
|
||||
pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
usb1-vbus-pins {
|
||||
pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
|
||||
<MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
pinctrl-0 = <&usb_pins>;
|
||||
pinctrl-names = "default";
|
||||
usb-role-switch;
|
||||
vusb33-supply = <&mt6357_vusb33_reg>;
|
||||
status = "okay";
|
||||
|
||||
connector {
|
||||
compatible = "gpio-usb-b-connector", "usb-b-connector";
|
||||
id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
|
||||
type = "micro";
|
||||
vbus-supply = <&usb_otg_vbus>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host {
|
||||
vusb33-supply = <&mt6357_vusb33_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
840
arch/arm/dts/mt8365.dtsi
Normal file
840
arch/arm/dts/mt8365.dtsi
Normal file
|
|
@ -0,0 +1,840 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* (C) 2018 MediaTek Inc.
|
||||
* Copyright (C) 2022 BayLibre SAS
|
||||
* Fabien Parent <fparent@baylibre.com>
|
||||
* Bernhard Rosenkränzer <bero@baylibre.com>
|
||||
*/
|
||||
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/power/mediatek,mt8365-power.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt8365";
|
||||
interrupt-parent = <&sysirq>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-850000000 {
|
||||
opp-hz = /bits/ 64 <850000000>;
|
||||
opp-microvolt = <650000>;
|
||||
};
|
||||
|
||||
opp-918000000 {
|
||||
opp-hz = /bits/ 64 <918000000>;
|
||||
opp-microvolt = <668750>;
|
||||
};
|
||||
|
||||
opp-987000000 {
|
||||
opp-hz = /bits/ 64 <987000000>;
|
||||
opp-microvolt = <687500>;
|
||||
};
|
||||
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-microvolt = <706250>;
|
||||
};
|
||||
|
||||
opp-1125000000 {
|
||||
opp-hz = /bits/ 64 <1125000000>;
|
||||
opp-microvolt = <725000>;
|
||||
};
|
||||
|
||||
opp-1216000000 {
|
||||
opp-hz = /bits/ 64 <1216000000>;
|
||||
opp-microvolt = <750000>;
|
||||
};
|
||||
|
||||
opp-1308000000 {
|
||||
opp-hz = /bits/ 64 <1308000000>;
|
||||
opp-microvolt = <775000>;
|
||||
};
|
||||
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
||||
opp-1466000000 {
|
||||
opp-hz = /bits/ 64 <1466000000>;
|
||||
opp-microvolt = <825000>;
|
||||
};
|
||||
|
||||
opp-1533000000 {
|
||||
opp-hz = /bits/ 64 <1533000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
|
||||
opp-1633000000 {
|
||||
opp-hz = /bits/ 64 <1633000000>;
|
||||
opp-microvolt = <887500>;
|
||||
};
|
||||
|
||||
opp-1700000000 {
|
||||
opp-hz = /bits/ 64 <1700000000>;
|
||||
opp-microvolt = <912500>;
|
||||
};
|
||||
|
||||
opp-1767000000 {
|
||||
opp-hz = /bits/ 64 <1767000000>;
|
||||
opp-microvolt = <937500>;
|
||||
};
|
||||
|
||||
opp-1834000000 {
|
||||
opp-hz = /bits/ 64 <1834000000>;
|
||||
opp-microvolt = <962500>;
|
||||
};
|
||||
|
||||
opp-1917000000 {
|
||||
opp-hz = /bits/ 64 <1917000000>;
|
||||
opp-microvolt = <993750>;
|
||||
};
|
||||
|
||||
opp-2001000000 {
|
||||
opp-hz = /bits/ 64 <2001000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate", "armpll";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate", "armpll";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
|
||||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate", "armpll";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_MCDI: cpu-mcdi {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x00010001>;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <200>;
|
||||
min-residency-us = <1000>;
|
||||
};
|
||||
|
||||
CLUSTER_MCDI: cluster-mcdi {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x01010001>;
|
||||
entry-latency-us = <350>;
|
||||
exit-latency-us = <250>;
|
||||
min-residency-us = <1200>;
|
||||
};
|
||||
|
||||
CLUSTER_DPIDLE: cluster-dpidle {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x01010004>;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <800>;
|
||||
min-residency-us = <3300>;
|
||||
};
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
clk26m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "clk26m";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@c000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x0c000000 0 0x10000>, /* GICD */
|
||||
<0 0x0c080000 0 0x80000>, /* GICR */
|
||||
<0 0x0c400000 0 0x2000>, /* GICC */
|
||||
<0 0x0c410000 0 0x1000>, /* GICH */
|
||||
<0 0x0c420000 0 0x2000>; /* GICV */
|
||||
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8365-topckgen", "syscon";
|
||||
reg = <0 0x10000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
infracfg: syscon@10001000 {
|
||||
compatible = "mediatek,mt8365-infracfg", "syscon";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pericfg: syscon@10003000 {
|
||||
compatible = "mediatek,mt8365-pericfg", "syscon";
|
||||
reg = <0 0x10003000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
syscfg_pctl: syscfg-pctl@10005000 {
|
||||
compatible = "mediatek,mt8365-syscfg", "syscon";
|
||||
reg = <0 0x10005000 0 0x1000>;
|
||||
};
|
||||
|
||||
scpsys: syscon@10006000 {
|
||||
compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
|
||||
reg = <0 0x10006000 0 0x1000>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
/* System Power Manager */
|
||||
spm: power-controller {
|
||||
compatible = "mediatek,mt8365-power-controller";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
/* power domains of the SoC */
|
||||
power-domain@MT8365_POWER_DOMAIN_MM {
|
||||
reg = <MT8365_POWER_DOMAIN_MM>;
|
||||
clocks = <&topckgen CLK_TOP_MM_SEL>,
|
||||
<&mmsys CLK_MM_MM_SMI_COMMON>,
|
||||
<&mmsys CLK_MM_MM_SMI_COMM0>,
|
||||
<&mmsys CLK_MM_MM_SMI_COMM1>,
|
||||
<&mmsys CLK_MM_MM_SMI_LARB0>;
|
||||
clock-names = "mm", "mm-0", "mm-1",
|
||||
"mm-2", "mm-3";
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
mediatek,infracfg-nao = <&infracfg_nao>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
power-domain@MT8365_POWER_DOMAIN_CAM {
|
||||
reg = <MT8365_POWER_DOMAIN_CAM>;
|
||||
clocks = <&camsys CLK_CAM_LARB2>,
|
||||
<&camsys CLK_CAM_SENIF>,
|
||||
<&camsys CLK_CAMSV0>,
|
||||
<&camsys CLK_CAMSV1>,
|
||||
<&camsys CLK_CAM_FDVT>,
|
||||
<&camsys CLK_CAM_WPE>;
|
||||
clock-names = "cam-0", "cam-1",
|
||||
"cam-2", "cam-3",
|
||||
"cam-4", "cam-5";
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
};
|
||||
|
||||
power-domain@MT8365_POWER_DOMAIN_VDEC {
|
||||
reg = <MT8365_POWER_DOMAIN_VDEC>;
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
};
|
||||
|
||||
power-domain@MT8365_POWER_DOMAIN_VENC {
|
||||
reg = <MT8365_POWER_DOMAIN_VENC>;
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
};
|
||||
|
||||
power-domain@MT8365_POWER_DOMAIN_APU {
|
||||
reg = <MT8365_POWER_DOMAIN_APU>;
|
||||
clocks = <&infracfg CLK_IFR_APU_AXI>,
|
||||
<&apu CLK_APU_IPU_CK>,
|
||||
<&apu CLK_APU_AXI>,
|
||||
<&apu CLK_APU_JTAG>,
|
||||
<&apu CLK_APU_IF_CK>,
|
||||
<&apu CLK_APU_EDMA>,
|
||||
<&apu CLK_APU_AHB>;
|
||||
clock-names = "apu", "apu-0",
|
||||
"apu-1", "apu-2",
|
||||
"apu-3", "apu-4",
|
||||
"apu-5";
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
};
|
||||
};
|
||||
|
||||
power-domain@MT8365_POWER_DOMAIN_CONN {
|
||||
reg = <MT8365_POWER_DOMAIN_CONN>;
|
||||
clocks = <&topckgen CLK_TOP_CONN_32K>,
|
||||
<&topckgen CLK_TOP_CONN_26M>;
|
||||
clock-names = "conn", "conn1";
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
};
|
||||
|
||||
power-domain@MT8365_POWER_DOMAIN_MFG {
|
||||
reg = <MT8365_POWER_DOMAIN_MFG>;
|
||||
clocks = <&topckgen CLK_TOP_MFG_SEL>;
|
||||
clock-names = "mfg";
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
};
|
||||
|
||||
power-domain@MT8365_POWER_DOMAIN_AUDIO {
|
||||
reg = <MT8365_POWER_DOMAIN_AUDIO>;
|
||||
clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
|
||||
<&infracfg CLK_IFR_AUDIO>,
|
||||
<&infracfg CLK_IFR_AUD_26M_BK>;
|
||||
clock-names = "audio", "audio1", "audio2";
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
};
|
||||
|
||||
power-domain@MT8365_POWER_DOMAIN_DSP {
|
||||
reg = <MT8365_POWER_DOMAIN_DSP>;
|
||||
clocks = <&topckgen CLK_TOP_DSP_SEL>,
|
||||
<&topckgen CLK_TOP_DSP_26M>;
|
||||
clock-names = "dsp", "dsp1";
|
||||
#power-domain-cells = <0>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
watchdog: watchdog@10007000 {
|
||||
compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
|
||||
reg = <0 0x10007000 0 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pio: pinctrl@1000b000 {
|
||||
compatible = "mediatek,mt8365-pinctrl";
|
||||
reg = <0 0x1000b000 0 0x1000>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
apmixedsys: syscon@1000c000 {
|
||||
compatible = "mediatek,mt8365-apmixedsys", "syscon";
|
||||
reg = <0 0x1000c000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pwrap: pwrap@1000d000 {
|
||||
compatible = "mediatek,mt8365-pwrap";
|
||||
reg = <0 0x1000d000 0 0x1000>;
|
||||
reg-names = "pwrap";
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
|
||||
<&infracfg CLK_IFR_PMIC_AP>,
|
||||
<&infracfg CLK_IFR_PWRAP_SYS>,
|
||||
<&infracfg CLK_IFR_PWRAP_TMR>;
|
||||
clock-names = "spi", "wrap", "sys", "tmr";
|
||||
};
|
||||
|
||||
keypad: keypad@10010000 {
|
||||
compatible = "mediatek,mt6779-keypad";
|
||||
reg = <0 0x10010000 0 0x1000>;
|
||||
wakeup-source;
|
||||
interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
|
||||
clocks = <&clk26m>;
|
||||
clock-names = "kpd";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcucfg: syscon@10200000 {
|
||||
compatible = "mediatek,mt8365-mcucfg", "syscon";
|
||||
reg = <0 0x10200000 0 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sysirq: interrupt-controller@10200a80 {
|
||||
compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0x10200a80 0 0x20>;
|
||||
};
|
||||
|
||||
iommu: iommu@10205000 {
|
||||
compatible = "mediatek,mt8365-m4u";
|
||||
reg = <0 0x10205000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
|
||||
mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
infracfg_nao: infracfg@1020e000 {
|
||||
compatible = "mediatek,mt8365-infracfg", "syscon";
|
||||
reg = <0 0x1020e000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rng: rng@1020f000 {
|
||||
compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
|
||||
reg = <0 0x1020f000 0 0x100>;
|
||||
clocks = <&infracfg CLK_IFR_TRNG>;
|
||||
clock-names = "rng";
|
||||
};
|
||||
|
||||
apdma: dma-controller@11000280 {
|
||||
compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
|
||||
reg = <0 0x11000280 0 0x80>,
|
||||
<0 0x11000300 0 0x80>,
|
||||
<0 0x11000380 0 0x80>,
|
||||
<0 0x11000400 0 0x80>,
|
||||
<0 0x11000580 0 0x80>,
|
||||
<0 0x11000600 0 0x80>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
|
||||
dma-requests = <6>;
|
||||
clocks = <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "apdma";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@11002000 {
|
||||
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
||||
reg = <0 0x11002000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
|
||||
clock-names = "baud", "bus";
|
||||
dmas = <&apdma 0>, <&apdma 1>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11003000 {
|
||||
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
||||
reg = <0 0x11003000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
|
||||
clock-names = "baud", "bus";
|
||||
dmas = <&apdma 2>, <&apdma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11004000 {
|
||||
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
|
||||
reg = <0 0x11004000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
|
||||
clock-names = "baud", "bus";
|
||||
dmas = <&apdma 4>, <&apdma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@11006000 {
|
||||
compatible = "mediatek,mt8365-pwm";
|
||||
reg = <0 0x11006000 0 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_IFR_PWM_HCLK>,
|
||||
<&infracfg CLK_IFR_PWM>,
|
||||
<&infracfg CLK_IFR_PWM1>,
|
||||
<&infracfg CLK_IFR_PWM2>,
|
||||
<&infracfg CLK_IFR_PWM3>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
|
||||
};
|
||||
|
||||
i2c0: i2c@11007000 {
|
||||
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
||||
reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11008000 {
|
||||
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
||||
reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@11009000 {
|
||||
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
||||
reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@1100a000 {
|
||||
compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
|
||||
reg = <0 0x1100a000 0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_IFR_SPI0>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@1100f000 {
|
||||
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
|
||||
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssusb: usb@11201000 {
|
||||
compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
|
||||
reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
|
||||
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||
<&u2port1 PHY_TYPE_USB2>;
|
||||
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
|
||||
<&infracfg CLK_IFR_SSUSB_REF>,
|
||||
<&infracfg CLK_IFR_SSUSB_SYS>,
|
||||
<&infracfg CLK_IFR_ICUSB>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
usb_host: usb@11200000 {
|
||||
compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
|
||||
reg = <0 0x11200000 0 0x1000>;
|
||||
reg-names = "mac";
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
|
||||
<&infracfg CLK_IFR_SSUSB_REF>,
|
||||
<&infracfg CLK_IFR_SSUSB_SYS>,
|
||||
<&infracfg CLK_IFR_ICUSB>,
|
||||
<&infracfg CLK_IFR_SSUSB_XHCI>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck",
|
||||
"dma_ck", "xhci_ck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>,
|
||||
<0 0x11cd0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
|
||||
<&infracfg CLK_IFR_MSDC0_HCLK>,
|
||||
<&infracfg CLK_IFR_MSDC0_SRC>;
|
||||
clock-names = "source", "hclk", "source_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@11240000 {
|
||||
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
||||
reg = <0 0x11240000 0 0x1000>,
|
||||
<0 0x11c90000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
|
||||
<&infracfg CLK_IFR_MSDC1_HCLK>,
|
||||
<&infracfg CLK_IFR_MSDC1_SRC>;
|
||||
clock-names = "source", "hclk", "source_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc2: mmc@11250000 {
|
||||
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
|
||||
reg = <0 0x11250000 0 0x1000>,
|
||||
<0 0x11c60000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
|
||||
<&infracfg CLK_IFR_MSDC2_HCLK>,
|
||||
<&infracfg CLK_IFR_MSDC2_SRC>,
|
||||
<&infracfg CLK_IFR_MSDC2_BK>,
|
||||
<&infracfg CLK_IFR_AP_MSDC0>;
|
||||
clock-names = "source", "hclk", "source_cg",
|
||||
"bus_clk", "sys_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet: ethernet@112a0000 {
|
||||
compatible = "mediatek,mt8365-eth";
|
||||
reg = <0 0x112a0000 0 0x1000>;
|
||||
mediatek,pericfg = <&infracfg>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
||||
<&infracfg CLK_IFR_NIC_AXI>,
|
||||
<&infracfg CLK_IFR_NIC_SLV_AXI>;
|
||||
clock-names = "core", "reg", "trans";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
u3phy: t-phy@11cc0000 {
|
||||
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x11cc0000 0x9000>;
|
||||
|
||||
u2port0: usb-phy@0 {
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
|
||||
<&topckgen CLK_TOP_USB20_48M_EN>;
|
||||
clock-names = "ref", "da_ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
u2port1: usb-phy@1000 {
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
|
||||
<&topckgen CLK_TOP_USB20_48M_EN>;
|
||||
clock-names = "ref", "da_ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt8365-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
smi_common: smi@14002000 {
|
||||
compatible = "mediatek,mt8365-smi-common";
|
||||
reg = <0 0x14002000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_MM_SMI_COMMON>,
|
||||
<&mmsys CLK_MM_MM_SMI_COMMON>,
|
||||
<&mmsys CLK_MM_MM_SMI_COMM0>,
|
||||
<&mmsys CLK_MM_MM_SMI_COMM1>;
|
||||
clock-names = "apb", "smi", "gals0", "gals1";
|
||||
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
|
||||
};
|
||||
|
||||
larb0: larb@14003000 {
|
||||
compatible = "mediatek,mt8365-smi-larb",
|
||||
"mediatek,mt8186-smi-larb";
|
||||
reg = <0 0x14003000 0 0x1000>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
clocks = <&mmsys CLK_MM_MM_SMI_LARB0>,
|
||||
<&mmsys CLK_MM_MM_SMI_LARB0>;
|
||||
clock-names = "apb", "smi";
|
||||
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
|
||||
mediatek,larb-id = <0>;
|
||||
};
|
||||
|
||||
camsys: syscon@15000000 {
|
||||
compatible = "mediatek,mt8365-imgsys", "syscon";
|
||||
reg = <0 0x15000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
larb2: larb@15001000 {
|
||||
compatible = "mediatek,mt8365-smi-larb",
|
||||
"mediatek,mt8186-smi-larb";
|
||||
reg = <0 0x15001000 0 0x1000>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
clocks = <&mmsys CLK_MM_MM_SMI_IMG>,
|
||||
<&camsys CLK_CAM_LARB2>;
|
||||
clock-names = "apb", "smi";
|
||||
power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
|
||||
mediatek,larb-id = <2>;
|
||||
};
|
||||
|
||||
vdecsys: syscon@16000000 {
|
||||
compatible = "mediatek,mt8365-vdecsys", "syscon";
|
||||
reg = <0 0x16000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
larb3: larb@16010000 {
|
||||
compatible = "mediatek,mt8365-smi-larb",
|
||||
"mediatek,mt8186-smi-larb";
|
||||
reg = <0 0x16010000 0 0x1000>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
clocks = <&vdecsys CLK_VDEC_LARB1>,
|
||||
<&vdecsys CLK_VDEC_LARB1>;
|
||||
clock-names = "apb", "smi";
|
||||
power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
|
||||
mediatek,larb-id = <3>;
|
||||
};
|
||||
|
||||
vencsys: syscon@17000000 {
|
||||
compatible = "mediatek,mt8365-vencsys", "syscon";
|
||||
reg = <0 0x17000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
larb1: larb@17010000 {
|
||||
compatible = "mediatek,mt8365-smi-larb",
|
||||
"mediatek,mt8186-smi-larb";
|
||||
reg = <0 0x17010000 0 0x1000>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>;
|
||||
clock-names = "apb", "smi";
|
||||
power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
|
||||
mediatek,larb-id = <1>;
|
||||
};
|
||||
|
||||
apu: syscon@19020000 {
|
||||
compatible = "mediatek,mt8365-apu", "syscon";
|
||||
reg = <0 0x19020000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
system_clk: dummy13m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
systimer: timer@10017000 {
|
||||
compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
|
||||
reg = <0 0x10017000 0 0x100>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&system_clk>;
|
||||
clock-names = "clk13m";
|
||||
};
|
||||
};
|
||||
|
|
@ -76,6 +76,14 @@ config TARGET_MT8183
|
|||
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
|
||||
and LPDDR4 options.
|
||||
|
||||
config TARGET_MT8365
|
||||
bool "MediaTek MT8365 SoC"
|
||||
select ARM64
|
||||
help
|
||||
The MediaTek MT8365 is a ARM64-based SoC with a quad-core Cortex-A53.
|
||||
It is including UART, SPI, USB2.0 dual role, SD and MMC cards, NAND, PWM,
|
||||
I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
|
||||
|
||||
config TARGET_MT8512
|
||||
bool "MediaTek MT8512 M1 Board"
|
||||
select ARM64
|
||||
|
|
@ -133,6 +141,7 @@ config SYS_CONFIG_NAME
|
|||
default "mt7986" if TARGET_MT7986
|
||||
default "mt7988" if TARGET_MT7988
|
||||
default "mt8183" if TARGET_MT8183
|
||||
default "mt8365" if TARGET_MT8365
|
||||
default "mt8512" if TARGET_MT8512
|
||||
default "mt8516" if TARGET_MT8516
|
||||
default "mt8518" if TARGET_MT8518
|
||||
|
|
|
|||
|
|
@ -11,5 +11,6 @@ obj-$(CONFIG_TARGET_MT7981) += mt7981/
|
|||
obj-$(CONFIG_TARGET_MT7986) += mt7986/
|
||||
obj-$(CONFIG_TARGET_MT7988) += mt7988/
|
||||
obj-$(CONFIG_TARGET_MT8183) += mt8183/
|
||||
obj-$(CONFIG_TARGET_MT8365) += mt8365/
|
||||
obj-$(CONFIG_TARGET_MT8516) += mt8516/
|
||||
obj-$(CONFIG_TARGET_MT8518) += mt8518/
|
||||
|
|
|
|||
3
arch/arm/mach-mediatek/mt8365/Makefile
Normal file
3
arch/arm/mach-mediatek/mt8365/Makefile
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
obj-y += init.o
|
||||
51
arch/arm/mach-mediatek/mt8365/init.c
Normal file
51
arch/arm/mach-mediatek/mt8365/init.c
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2023 MediaTek Inc.
|
||||
* Copyright (C) 2023 BayLibre, SAS
|
||||
* Author: Julien Masson <jmasson@baylibre.com>
|
||||
* Author: Fabien Parent <fparent@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/system.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <wdt.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
return fdtdec_setup_mem_size_base();
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = gd->ram_base;
|
||||
gd->bd->bi_dram[0].size = gd->ram_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mtk_soc_early_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(void)
|
||||
{
|
||||
struct udevice *wdt;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PSCI_RESET)) {
|
||||
psci_system_reset();
|
||||
} else {
|
||||
uclass_first_device(UCLASS_WDT, &wdt);
|
||||
if (wdt)
|
||||
wdt_expire_now(wdt, 0);
|
||||
}
|
||||
}
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
printf("CPU: MediaTek MT8365\n");
|
||||
return 0;
|
||||
}
|
||||
6
board/mediatek/mt8365_evk/MAINTAINERS
Normal file
6
board/mediatek/mt8365_evk/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
MT8365 EVK
|
||||
M: Julien Masson <jmasson@baylibre.com>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/mt8365-evk.dts
|
||||
F: board/mediatek/mt8365_evk/
|
||||
F: configs/mt8365_evk_defconfig
|
||||
3
board/mediatek/mt8365_evk/Makefile
Normal file
3
board/mediatek/mt8365_evk/Makefile
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
obj-y += mt8365_evk.o
|
||||
33
board/mediatek/mt8365_evk/mt8365_evk.c
Normal file
33
board/mediatek/mt8365_evk/mt8365_evk.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2023 BayLibre SAS
|
||||
* Author: Julien Masson <jmasson@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <asm/armv8/mmu.h>
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mm_region mt8365_evk_mem_map[] = {
|
||||
{
|
||||
/* DDR */
|
||||
.virt = 0x40000000UL,
|
||||
.phys = 0x40000000UL,
|
||||
.size = 0xc0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
|
||||
}, {
|
||||
.virt = 0x00000000UL,
|
||||
.phys = 0x00000000UL,
|
||||
.size = 0x20000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = mt8365_evk_mem_map;
|
||||
19
configs/mt8365_evk_defconfig
Normal file
19
configs/mt8365_evk_defconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_BOARD="mt8365_evk"
|
||||
CONFIG_COUNTER_FREQUENCY=13000000
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_TEXT_BASE=0x4c000000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt8365-evk"
|
||||
CONFIG_TARGET_MT8365=y
|
||||
CONFIG_IDENT_STRING=" mt8365-evk"
|
||||
CONFIG_SYS_LOAD_ADDR=0x4c000000
|
||||
CONFIG_DEFAULT_FDT_FILE="mt8365-evk"
|
||||
CONFIG_CLK=y
|
||||
CONFIG_MMC_MTK=y
|
||||
CONFIG_BAUDRATE=921600
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_MTK=y
|
||||
|
|
@ -11,5 +11,6 @@ obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
|
|||
obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
|
||||
obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
|
||||
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
|
||||
obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o
|
||||
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
|
||||
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
|
||||
|
|
|
|||
766
drivers/clk/mediatek/clk-mt8365.c
Normal file
766
drivers/clk/mediatek/clk-mt8365.c
Normal file
|
|
@ -0,0 +1,766 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* MediaTek clock driver for MT8365 SoC
|
||||
*
|
||||
* Copyright (C) 2023 BayLibre, SAS
|
||||
* Copyright (c) 2023 MediaTek Inc.
|
||||
* Author: Julien Masson <jmasson@baylibre.com>
|
||||
* Author: Fabien Parent <fparent@baylibre.com>
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
|
||||
#include "clk-mtk.h"
|
||||
|
||||
/* apmixedsys */
|
||||
#define MT8365_PLL_FMAX (3800UL * MHZ)
|
||||
#define MT8365_PLL_FMIN (1500UL * MHZ)
|
||||
#define CON0_MT8365_RST_BAR BIT(23)
|
||||
#define PLL_AO BIT(1)
|
||||
|
||||
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
|
||||
_pd_shift, _pcw_reg, _pcw_shift, _rst_bar_mask, _pcw_chg_reg) { \
|
||||
.id = _id, \
|
||||
.reg = _reg, \
|
||||
.pwr_reg = _pwr_reg, \
|
||||
.en_mask = _en_mask, \
|
||||
.pd_reg = _pd_reg, \
|
||||
.pd_shift = _pd_shift, \
|
||||
.flags = _flags, \
|
||||
.rst_bar_mask = _rst_bar_mask, \
|
||||
.fmax = MT8365_PLL_FMAX, \
|
||||
.fmin = MT8365_PLL_FMIN, \
|
||||
.pcwbits = _pcwbits, \
|
||||
.pcwibits = 8, \
|
||||
.pcw_reg = _pcw_reg, \
|
||||
.pcw_shift = _pcw_shift, \
|
||||
.pcw_chg_reg = _pcw_chg_reg, \
|
||||
}
|
||||
|
||||
static const struct mtk_pll_data apmixed_plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310,
|
||||
24, 0x0310, 0, 0, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22,
|
||||
0x022C, 24, 0x022C, 0, CON0_MT8365_RST_BAR, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22,
|
||||
0x020C, 24, 0x020C, 0, CON0_MT8365_RST_BAR, 0),
|
||||
PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24,
|
||||
0x021C, 0, 0, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24,
|
||||
0x0354, 0, 0, 0),
|
||||
PLL(CLK_APMIXED_MMPLL, 0x0330, 0x033C, 0x00000001, 0, 22, 0x0334, 24,
|
||||
0x0334, 0, 0, 0),
|
||||
PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, 0, 32, 0x0320, 24,
|
||||
0x0324, 0, 0, 0x0320),
|
||||
PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, 0, 32, 0x0364, 24,
|
||||
0x0368, 0, 0, 0x0364),
|
||||
PLL(CLK_APMIXED_LVDSPLL, 0x0374, 0x0380, 0x00000001, 0, 22, 0x0378, 24,
|
||||
0x0378, 0, 0, 0),
|
||||
PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 0, 22, 0x0394, 24,
|
||||
0x0394, 0, 0, 0),
|
||||
PLL(CLK_APMIXED_APUPLL, 0x03A0, 0x03AC, 0x00000001, 0, 22, 0x03A4, 24,
|
||||
0x03A4, 0, 0, 0),
|
||||
};
|
||||
|
||||
/* topckgen */
|
||||
static const struct mtk_fixed_clk top_fixed_clks[] = {
|
||||
FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0),
|
||||
FIXED_CLK(CLK_TOP_I2S0_BCK, CLK_XTAL, 26000000),
|
||||
FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000),
|
||||
FIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000),
|
||||
FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000),
|
||||
};
|
||||
|
||||
#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
|
||||
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
|
||||
|
||||
static const struct mtk_fixed_factor top_divs[] = {
|
||||
PLL_FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", CLK_APMIXED_MAINPLL, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", CLK_APMIXED_MAINPLL, 1, 4),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", CLK_APMIXED_MAINPLL, 1, 8),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", CLK_APMIXED_MAINPLL, 1, 16),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", CLK_APMIXED_MAINPLL, 1, 32),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", CLK_APMIXED_MAINPLL, 1, 3),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", CLK_APMIXED_MAINPLL, 1, 6),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", CLK_APMIXED_MAINPLL, 1, 12),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", CLK_APMIXED_MAINPLL, 1, 24),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", CLK_APMIXED_MAINPLL, 1, 5),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", CLK_APMIXED_MAINPLL, 1, 10),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", CLK_APMIXED_MAINPLL, 1, 20),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", CLK_APMIXED_MAINPLL, 1, 7),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", CLK_APMIXED_MAINPLL, 1, 14),
|
||||
PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL, "univpll", CLK_APMIXED_UNIV_EN, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", CLK_APMIXED_UNIVPLL, 1, 3),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", CLK_APMIXED_UNIVPLL, 1, 6),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", CLK_APMIXED_UNIVPLL, 1, 12),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", CLK_APMIXED_UNIVPLL, 1, 24),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", CLK_APMIXED_UNIVPLL, 1, 96),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", CLK_APMIXED_UNIVPLL, 1, 5),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", CLK_APMIXED_UNIVPLL, 1, 10),
|
||||
PLL_FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", CLK_APMIXED_UNIVPLL, 1, 20),
|
||||
PLL_FACTOR(CLK_TOP_MMPLL, "mmpll_ck", CLK_APMIXED_MMPLL, 1, 1),
|
||||
PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1),
|
||||
PLL_FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", CLK_APMIXED_LVDSPLL, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", CLK_APMIXED_LVDSPLL, 1, 4),
|
||||
PLL_FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", CLK_APMIXED_LVDSPLL, 1, 8),
|
||||
PLL_FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", CLK_APMIXED_LVDSPLL, 1, 16),
|
||||
PLL_FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", CLK_APMIXED_USB20_EN, 1, 13),
|
||||
PLL_FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", CLK_TOP_USB20_192M, 1, 4),
|
||||
PLL_FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", CLK_TOP_USB20_192M, 1, 8),
|
||||
PLL_FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", CLK_TOP_USB20_192M, 1, 16),
|
||||
PLL_FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", CLK_TOP_USB20_192M, 1, 32),
|
||||
PLL_FACTOR(CLK_TOP_APLL1, "apll1_ck", CLK_APMIXED_APLL1, 1, 1),
|
||||
PLL_FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", CLK_APMIXED_APLL1, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", CLK_APMIXED_APLL1, 1, 4),
|
||||
PLL_FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", CLK_APMIXED_APLL1, 1, 8),
|
||||
PLL_FACTOR(CLK_TOP_APLL2, "apll2_ck", CLK_APMIXED_APLL2, 1, 1),
|
||||
PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
|
||||
PLL_FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", CLK_APMIXED_APLL2, 1, 8),
|
||||
PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1),
|
||||
PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1),
|
||||
PLL_FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", CLK_APMIXED_DSPPLL, 1, 2),
|
||||
PLL_FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", CLK_APMIXED_DSPPLL, 1, 4),
|
||||
PLL_FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", CLK_APMIXED_DSPPLL, 1, 8),
|
||||
PLL_FACTOR(CLK_TOP_APUPLL, "apupll_ck", CLK_APMIXED_APUPLL, 1, 1),
|
||||
PLL_FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52),
|
||||
};
|
||||
|
||||
static const int axi_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D7,
|
||||
CLK_TOP_SYSPLL1_D4,
|
||||
CLK_TOP_SYSPLL3_D2
|
||||
};
|
||||
|
||||
static const int mem_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MMPLL,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_SYSPLL1_D2
|
||||
};
|
||||
|
||||
static const int mm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MMPLL,
|
||||
CLK_TOP_SYSPLL1_D2,
|
||||
CLK_TOP_SYSPLL_D5,
|
||||
CLK_TOP_SYSPLL1_D4,
|
||||
CLK_TOP_UNIVPLL_D5,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_MMPLL_D2,
|
||||
};
|
||||
|
||||
static const int scp_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL4_D2,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_SYSPLL1_D2,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D3
|
||||
};
|
||||
|
||||
static const int mfg_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MFGPLL,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D3
|
||||
};
|
||||
|
||||
static const int atb_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL1_D4,
|
||||
CLK_TOP_SYSPLL1_D2
|
||||
};
|
||||
|
||||
static const int camtg_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_USB20_192M_D8,
|
||||
CLK_TOP_UNIVPLL2_D8,
|
||||
CLK_TOP_USB20_192M_D4,
|
||||
CLK_TOP_UNIVPLL2_D32,
|
||||
CLK_TOP_USB20_192M_D16,
|
||||
CLK_TOP_USB20_192M_D32,
|
||||
};
|
||||
|
||||
static const int uart_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL2_D8
|
||||
};
|
||||
|
||||
static const int spi_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_UNIVPLL2_D4,
|
||||
CLK_TOP_UNIVPLL2_D8
|
||||
};
|
||||
|
||||
static const int msdc50_0_hc_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL1_D2,
|
||||
CLK_TOP_UNIVPLL1_D4,
|
||||
CLK_TOP_SYSPLL2_D2
|
||||
};
|
||||
|
||||
static const int msdc50_0_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MSDCPLL,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_SYSPLL1_D2,
|
||||
CLK_TOP_UNIVPLL_D5,
|
||||
CLK_TOP_SYSPLL2_D2,
|
||||
CLK_TOP_UNIVPLL1_D4,
|
||||
CLK_TOP_SYSPLL4_D2
|
||||
};
|
||||
|
||||
static const int msdc50_2_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MSDCPLL,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_SYSPLL1_D2,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_SYSPLL2_D2,
|
||||
CLK_TOP_UNIVPLL1_D4
|
||||
};
|
||||
|
||||
static const int msdc30_1_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MSDCPLL_D2,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_SYSPLL2_D2,
|
||||
CLK_TOP_UNIVPLL1_D4,
|
||||
CLK_TOP_SYSPLL1_D4,
|
||||
CLK_TOP_SYSPLL2_D4,
|
||||
CLK_TOP_UNIVPLL2_D8
|
||||
};
|
||||
|
||||
static const int audio_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL3_D4,
|
||||
CLK_TOP_SYSPLL4_D4,
|
||||
CLK_TOP_SYSPLL1_D16
|
||||
};
|
||||
|
||||
static const int aud_intbus_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL1_D4,
|
||||
CLK_TOP_SYSPLL4_D2
|
||||
};
|
||||
|
||||
static const int aud_1_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_APLL1
|
||||
};
|
||||
|
||||
static const int aud_2_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_APLL2
|
||||
};
|
||||
|
||||
static const int aud_engen1_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_APLL1_D2,
|
||||
CLK_TOP_APLL1_D4,
|
||||
CLK_TOP_APLL1_D8
|
||||
};
|
||||
|
||||
static const int aud_engen2_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_APLL2_D2,
|
||||
CLK_TOP_APLL2_D4,
|
||||
CLK_TOP_APLL2_D8,
|
||||
};
|
||||
|
||||
static const int aud_spdif_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D2
|
||||
};
|
||||
|
||||
static const int disp_pwm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL2_D4
|
||||
};
|
||||
|
||||
static const int dxcc_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL1_D2,
|
||||
CLK_TOP_SYSPLL1_D4,
|
||||
CLK_TOP_SYSPLL1_D8
|
||||
};
|
||||
|
||||
static const int ssusb_sys_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL3_D4,
|
||||
CLK_TOP_UNIVPLL2_D4,
|
||||
CLK_TOP_UNIVPLL3_D2
|
||||
};
|
||||
|
||||
static const int spm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL1_D8
|
||||
};
|
||||
|
||||
static const int i2c_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL3_D4,
|
||||
CLK_TOP_UNIVPLL3_D2,
|
||||
CLK_TOP_SYSPLL1_D8,
|
||||
CLK_TOP_SYSPLL2_D8
|
||||
};
|
||||
|
||||
static const int pwm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL3_D4,
|
||||
CLK_TOP_SYSPLL1_D8
|
||||
};
|
||||
|
||||
static const int senif_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL1_D4,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_UNIVPLL2_D2
|
||||
};
|
||||
|
||||
static const int aes_fde_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MSDCPLL,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_SYSPLL1_D2
|
||||
};
|
||||
|
||||
static const int dpi0_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_LVDSPLL_D2,
|
||||
CLK_TOP_LVDSPLL_D4,
|
||||
CLK_TOP_LVDSPLL_D8,
|
||||
CLK_TOP_LVDSPLL_D16
|
||||
};
|
||||
|
||||
static const int dsp_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYS_26M_D2,
|
||||
CLK_TOP_DSPPLL,
|
||||
CLK_TOP_DSPPLL_D2,
|
||||
CLK_TOP_DSPPLL_D4,
|
||||
CLK_TOP_DSPPLL_D8
|
||||
};
|
||||
|
||||
static const int nfi2x_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL2_D2,
|
||||
CLK_TOP_SYSPLL_D7,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_SYSPLL2_D4,
|
||||
CLK_TOP_MSDCPLL_D2,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_UNIVPLL_D5
|
||||
};
|
||||
|
||||
static const int nfiecc_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL4_D2,
|
||||
CLK_TOP_UNIVPLL2_D4,
|
||||
CLK_TOP_SYSPLL_D7,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_SYSPLL1_D2,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_SYSPLL_D5
|
||||
};
|
||||
|
||||
static const int ecc_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_SYSPLL_D2
|
||||
};
|
||||
|
||||
static const int eth_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL2_D8,
|
||||
CLK_TOP_SYSPLL4_D4,
|
||||
CLK_TOP_SYSPLL1_D8,
|
||||
CLK_TOP_SYSPLL4_D2
|
||||
};
|
||||
|
||||
static const int gcpu_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_SYSPLL2_D2
|
||||
};
|
||||
|
||||
static const int gcpu_cpm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL2_D2,
|
||||
CLK_TOP_SYSPLL2_D2
|
||||
};
|
||||
|
||||
static const int apu_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D2,
|
||||
CLK_APMIXED_APUPLL,
|
||||
CLK_TOP_MMPLL,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL1_D2,
|
||||
CLK_TOP_SYSPLL1_D2,
|
||||
CLK_TOP_SYSPLL1_D4
|
||||
};
|
||||
|
||||
static const struct mtk_composite top_muxes[] = {
|
||||
/* CLK_CFG_0 */
|
||||
MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23),
|
||||
MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31),
|
||||
/* CLK_CFG_1 */
|
||||
MUX_GATE(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23),
|
||||
MUX_GATE(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31),
|
||||
/* CLK_CFG_2 */
|
||||
MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7),
|
||||
MUX_GATE(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23),
|
||||
MUX_GATE(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31),
|
||||
/* CLK_CFG_3 */
|
||||
MUX_GATE(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7),
|
||||
MUX_GATE(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15),
|
||||
MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23),
|
||||
MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31),
|
||||
/* CLK_CFG_4 */
|
||||
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15),
|
||||
MUX_GATE(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23),
|
||||
MUX_GATE(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31),
|
||||
/* CLK_CFG_5 */
|
||||
MUX_GATE(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15),
|
||||
MUX_GATE(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23),
|
||||
/* CLK_CFG_6 */
|
||||
MUX_GATE(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23),
|
||||
MUX_GATE(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31),
|
||||
/* CLK_CFG_7 */
|
||||
MUX_GATE(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7),
|
||||
MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23),
|
||||
MUX_GATE(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31),
|
||||
/* CLK_CFG_8 */
|
||||
MUX_GATE(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15),
|
||||
MUX_GATE(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23),
|
||||
MUX_GATE(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31),
|
||||
/* CLK_CFG_9 */
|
||||
MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7),
|
||||
MUX_GATE(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15),
|
||||
MUX_GATE(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23),
|
||||
MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31),
|
||||
/* CLK_CFG_10 */
|
||||
MUX_GATE(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7),
|
||||
MUX_GATE(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23),
|
||||
MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_tree mt8365_clk_tree = {
|
||||
.xtal_rate = 26 * MHZ,
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
.fdivs_offs = CLK_TOP_SYSPLL_D2,
|
||||
.muxes_offs = CLK_TOP_AXI_SEL,
|
||||
.plls = apmixed_plls,
|
||||
.fclks = top_fixed_clks,
|
||||
.fdivs = top_divs,
|
||||
.muxes = top_muxes,
|
||||
};
|
||||
|
||||
/* topckgen cg */
|
||||
static const struct mtk_gate_regs top0_cg_regs = {
|
||||
.set_ofs = 0,
|
||||
.clr_ofs = 0,
|
||||
.sta_ofs = 0,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs top1_cg_regs = {
|
||||
.set_ofs = 0x104,
|
||||
.clr_ofs = 0x104,
|
||||
.sta_ofs = 0x104,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs top2_cg_regs = {
|
||||
.set_ofs = 0x320,
|
||||
.clr_ofs = 0x320,
|
||||
.sta_ofs = 0x320,
|
||||
};
|
||||
|
||||
#define GATE_TOP0(_id, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.parent = _parent, \
|
||||
.regs = &top0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
|
||||
}
|
||||
|
||||
#define GATE_TOP1(_id, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.parent = _parent, \
|
||||
.regs = &top1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
|
||||
}
|
||||
|
||||
#define GATE_TOP2(_id, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.parent = _parent, \
|
||||
.regs = &top2_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate top_clk_gates[] = {
|
||||
GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
|
||||
GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
|
||||
GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
|
||||
GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
|
||||
GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),
|
||||
GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),
|
||||
GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),
|
||||
GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),
|
||||
GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
|
||||
GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
|
||||
GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0),
|
||||
GATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1),
|
||||
GATE_TOP2(CLK_TOP_AUD_I2S2_M, CLK_TOP_APLL12_CK_DIV2, 2),
|
||||
GATE_TOP2(CLK_TOP_AUD_I2S3_M, CLK_TOP_APLL12_CK_DIV3, 3),
|
||||
GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, CLK_TOP_APLL12_CK_DIV4, 4),
|
||||
GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, CLK_TOP_APLL12_CK_DIV4B, 5),
|
||||
GATE_TOP2(CLK_TOP_AUD_TDMIN_M, CLK_TOP_APLL12_CK_DIV5, 6),
|
||||
GATE_TOP2(CLK_TOP_AUD_TDMIN_B, CLK_TOP_APLL12_CK_DIV5B, 7),
|
||||
GATE_TOP2(CLK_TOP_AUD_SPDIF_M, CLK_TOP_APLL12_CK_DIV6, 8),
|
||||
};
|
||||
|
||||
/* infracfg */
|
||||
static const struct mtk_gate_regs ifr2_cg_regs = {
|
||||
.set_ofs = 0x80,
|
||||
.clr_ofs = 0x84,
|
||||
.sta_ofs = 0x90,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr3_cg_regs = {
|
||||
.set_ofs = 0x88,
|
||||
.clr_ofs = 0x8c,
|
||||
.sta_ofs = 0x94,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr4_cg_regs = {
|
||||
.set_ofs = 0xa4,
|
||||
.clr_ofs = 0xa8,
|
||||
.sta_ofs = 0xac,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr5_cg_regs = {
|
||||
.set_ofs = 0xc0,
|
||||
.clr_ofs = 0xc4,
|
||||
.sta_ofs = 0xc8,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ifr6_cg_regs = {
|
||||
.set_ofs = 0xd0,
|
||||
.clr_ofs = 0xd4,
|
||||
.sta_ofs = 0xd8,
|
||||
};
|
||||
|
||||
#define GATE_IFRX(_id, _parent, _shift, _regs) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.parent = _parent, \
|
||||
.regs = _regs, \
|
||||
.shift = _shift, \
|
||||
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
||||
}
|
||||
|
||||
#define GATE_IFR2(_id, _parent, _shift) \
|
||||
GATE_IFRX(_id, _parent, _shift, &ifr2_cg_regs)
|
||||
|
||||
#define GATE_IFR3(_id, _parent, _shift) \
|
||||
GATE_IFRX(_id, _parent, _shift, &ifr3_cg_regs)
|
||||
|
||||
#define GATE_IFR4(_id, _parent, _shift) \
|
||||
GATE_IFRX(_id, _parent, _shift, &ifr4_cg_regs)
|
||||
|
||||
#define GATE_IFR5(_id, _parent, _shift) \
|
||||
GATE_IFRX(_id, _parent, _shift, &ifr5_cg_regs)
|
||||
|
||||
#define GATE_IFR6(_id, _parent, _shift) \
|
||||
GATE_IFRX(_id, _parent, _shift, &ifr6_cg_regs)
|
||||
|
||||
static const struct mtk_gate ifr_clks[] = {
|
||||
/* IFR2 */
|
||||
GATE_IFR2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0),
|
||||
GATE_IFR2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1),
|
||||
GATE_IFR2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2),
|
||||
GATE_IFR2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3),
|
||||
GATE_IFR2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8),
|
||||
GATE_IFR2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9),
|
||||
GATE_IFR2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10),
|
||||
GATE_IFR2(CLK_IFR_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
|
||||
GATE_IFR2(CLK_IFR_PWM1, CLK_TOP_PWM_SEL, 16),
|
||||
GATE_IFR2(CLK_IFR_PWM2, CLK_TOP_PWM_SEL, 17),
|
||||
GATE_IFR2(CLK_IFR_PWM3, CLK_TOP_PWM_SEL, 18),
|
||||
GATE_IFR2(CLK_IFR_PWM4, CLK_TOP_PWM_SEL, 19),
|
||||
GATE_IFR2(CLK_IFR_PWM5, CLK_TOP_PWM_SEL, 20),
|
||||
GATE_IFR2(CLK_IFR_PWM, CLK_TOP_PWM_SEL, 21),
|
||||
GATE_IFR2(CLK_IFR_UART0, CLK_TOP_UART_SEL, 22),
|
||||
GATE_IFR2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23),
|
||||
GATE_IFR2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24),
|
||||
GATE_IFR2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26),
|
||||
GATE_IFR2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27),
|
||||
GATE_IFR2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28),
|
||||
GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31),
|
||||
/* IFR3 */
|
||||
GATE_IFR3(CLK_IFR_SPI0, CLK_TOP_SPI_SEL, 1),
|
||||
GATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_MSDC50_0_HC_SEL, 2),
|
||||
GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3),
|
||||
GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4),
|
||||
GATE_IFR3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7),
|
||||
GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),
|
||||
GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9),
|
||||
GATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10),
|
||||
GATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14),
|
||||
GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18),
|
||||
GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
|
||||
GATE_IFR3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25),
|
||||
/* IFR4 */
|
||||
GATE_IFR4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0),
|
||||
GATE_IFR4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2),
|
||||
GATE_IFR4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4),
|
||||
GATE_IFR4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27),
|
||||
/* IFR5 */
|
||||
GATE_IFR5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0),
|
||||
GATE_IFR5(CLK_IFR_MSDC1_SF, CLK_TOP_MSDC50_0_SEL, 1),
|
||||
GATE_IFR5(CLK_IFR_MSDC2_SF, CLK_TOP_MSDC50_0_SEL, 2),
|
||||
GATE_IFR5(CLK_IFR_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
|
||||
GATE_IFR5(CLK_IFR_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
|
||||
GATE_IFR5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
|
||||
GATE_IFR5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
|
||||
GATE_IFR5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11),
|
||||
GATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12),
|
||||
GATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13),
|
||||
GATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14),
|
||||
GATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22),
|
||||
GATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23),
|
||||
GATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
|
||||
GATE_IFR5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
|
||||
GATE_IFR5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
|
||||
GATE_IFR5(CLK_IFR_I2C3_AXI, CLK_TOP_I2C_SEL, 27),
|
||||
GATE_IFR5(CLK_IFR_NIC_AXI, CLK_TOP_AXI_SEL, 28),
|
||||
GATE_IFR5(CLK_IFR_NIC_SLV_AXI, CLK_TOP_AXI_SEL, 29),
|
||||
GATE_IFR5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30),
|
||||
/* IFR6 */
|
||||
GATE_IFR6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0),
|
||||
GATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1),
|
||||
GATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2),
|
||||
GATE_IFR6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3),
|
||||
GATE_IFR6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4),
|
||||
GATE_IFR6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5),
|
||||
GATE_IFR6(CLK_IFR_MSDC2_BK, CLK_TOP_AXI_SEL, 6),
|
||||
GATE_IFR6(CLK_IFR_SUSB_133_BK, CLK_TOP_AXI_SEL, 7),
|
||||
GATE_IFR6(CLK_IFR_SUSB_66_BK, CLK_TOP_AXI_SEL, 8),
|
||||
GATE_IFR6(CLK_IFR_SSUSB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
|
||||
GATE_IFR6(CLK_IFR_SSUSB_REF, CLK_TOP_SSUSB_SYS_SEL, 10),
|
||||
GATE_IFR6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
|
||||
};
|
||||
|
||||
static int mt8365_apmixedsys_probe(struct udevice *dev)
|
||||
{
|
||||
return mtk_common_clk_init(dev, &mt8365_clk_tree);
|
||||
}
|
||||
|
||||
static int mt8365_topckgen_probe(struct udevice *dev)
|
||||
{
|
||||
return mtk_common_clk_init(dev, &mt8365_clk_tree);
|
||||
}
|
||||
|
||||
static int mt8365_topckgen_cg_probe(struct udevice *dev)
|
||||
{
|
||||
return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, top_clk_gates);
|
||||
}
|
||||
|
||||
static int mt8365_infracfg_probe(struct udevice *dev)
|
||||
{
|
||||
return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, ifr_clks);
|
||||
}
|
||||
|
||||
static const struct udevice_id mt8365_apmixed_compat[] = {
|
||||
{ .compatible = "mediatek,mt8365-apmixedsys", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct udevice_id mt8365_topckgen_compat[] = {
|
||||
{ .compatible = "mediatek,mt8365-topckgen", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct udevice_id mt8365_topckgen_cg_compat[] = {
|
||||
{ .compatible = "mediatek,mt8365-topckgen-cg", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct udevice_id mt8365_infracfg_compat[] = {
|
||||
{ .compatible = "mediatek,mt8365-infracfg", },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
|
||||
.name = "mt8365-apmixedsys",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = mt8365_apmixed_compat,
|
||||
.probe = mt8365_apmixedsys_probe,
|
||||
.priv_auto = sizeof(struct mtk_clk_priv),
|
||||
.ops = &mtk_clk_apmixedsys_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mtk_clk_topckgen) = {
|
||||
.name = "mt8365-topckgen",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = mt8365_topckgen_compat,
|
||||
.probe = mt8365_topckgen_probe,
|
||||
.priv_auto = sizeof(struct mtk_clk_priv),
|
||||
.ops = &mtk_clk_topckgen_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
|
||||
.name = "mt8365-topckgen-cg",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = mt8365_topckgen_cg_compat,
|
||||
.probe = mt8365_topckgen_cg_probe,
|
||||
.priv_auto = sizeof(struct mtk_cg_priv),
|
||||
.ops = &mtk_clk_gate_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mtk_clk_infracfg) = {
|
||||
.name = "mt8365-infracfg",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = mt8365_infracfg_compat,
|
||||
.probe = mt8365_infracfg_probe,
|
||||
.priv_auto = sizeof(struct mtk_cg_priv),
|
||||
.ops = &mtk_clk_gate_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
12
include/configs/mt8365.h
Normal file
12
include/configs/mt8365.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuration for MT8365 based boards
|
||||
*
|
||||
* Copyright (C) 2023 BayLibre, SAS
|
||||
* Author: Julien Masson <jmasson@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __MT8365_H
|
||||
#define __MT8365_H
|
||||
|
||||
#endif
|
||||
375
include/dt-bindings/clock/mediatek,mt8365-clk.h
Normal file
375
include/dt-bindings/clock/mediatek,mt8365-clk.h
Normal file
|
|
@ -0,0 +1,375 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT8365_H
|
||||
#define _DT_BINDINGS_CLK_MT8365_H
|
||||
|
||||
/* TOPCKGEN */
|
||||
#define CLK_TOP_CLK_NULL 0
|
||||
#define CLK_TOP_I2S0_BCK 1
|
||||
#define CLK_TOP_DSI0_LNTC_DSICK 2
|
||||
#define CLK_TOP_VPLL_DPIX 3
|
||||
#define CLK_TOP_LVDSTX_CLKDIG_CTS 4
|
||||
#define CLK_TOP_MFGPLL 5
|
||||
#define CLK_TOP_SYSPLL_D2 6
|
||||
#define CLK_TOP_SYSPLL1_D2 7
|
||||
#define CLK_TOP_SYSPLL1_D4 8
|
||||
#define CLK_TOP_SYSPLL1_D8 9
|
||||
#define CLK_TOP_SYSPLL1_D16 10
|
||||
#define CLK_TOP_SYSPLL_D3 11
|
||||
#define CLK_TOP_SYSPLL2_D2 12
|
||||
#define CLK_TOP_SYSPLL2_D4 13
|
||||
#define CLK_TOP_SYSPLL2_D8 14
|
||||
#define CLK_TOP_SYSPLL_D5 15
|
||||
#define CLK_TOP_SYSPLL3_D2 16
|
||||
#define CLK_TOP_SYSPLL3_D4 17
|
||||
#define CLK_TOP_SYSPLL_D7 18
|
||||
#define CLK_TOP_SYSPLL4_D2 19
|
||||
#define CLK_TOP_SYSPLL4_D4 20
|
||||
#define CLK_TOP_UNIVPLL 21
|
||||
#define CLK_TOP_UNIVPLL_D2 22
|
||||
#define CLK_TOP_UNIVPLL1_D2 23
|
||||
#define CLK_TOP_UNIVPLL1_D4 24
|
||||
#define CLK_TOP_UNIVPLL_D3 25
|
||||
#define CLK_TOP_UNIVPLL2_D2 26
|
||||
#define CLK_TOP_UNIVPLL2_D4 27
|
||||
#define CLK_TOP_UNIVPLL2_D8 28
|
||||
#define CLK_TOP_UNIVPLL2_D32 29
|
||||
#define CLK_TOP_UNIVPLL_D5 30
|
||||
#define CLK_TOP_UNIVPLL3_D2 31
|
||||
#define CLK_TOP_UNIVPLL3_D4 32
|
||||
#define CLK_TOP_MMPLL 33
|
||||
#define CLK_TOP_MMPLL_D2 34
|
||||
#define CLK_TOP_LVDSPLL_D2 35
|
||||
#define CLK_TOP_LVDSPLL_D4 36
|
||||
#define CLK_TOP_LVDSPLL_D8 37
|
||||
#define CLK_TOP_LVDSPLL_D16 38
|
||||
#define CLK_TOP_USB20_192M 39
|
||||
#define CLK_TOP_USB20_192M_D4 40
|
||||
#define CLK_TOP_USB20_192M_D8 41
|
||||
#define CLK_TOP_USB20_192M_D16 42
|
||||
#define CLK_TOP_USB20_192M_D32 43
|
||||
#define CLK_TOP_APLL1 44
|
||||
#define CLK_TOP_APLL1_D2 45
|
||||
#define CLK_TOP_APLL1_D4 46
|
||||
#define CLK_TOP_APLL1_D8 47
|
||||
#define CLK_TOP_APLL2 48
|
||||
#define CLK_TOP_APLL2_D2 49
|
||||
#define CLK_TOP_APLL2_D4 50
|
||||
#define CLK_TOP_APLL2_D8 51
|
||||
#define CLK_TOP_SYS_26M_D2 52
|
||||
#define CLK_TOP_MSDCPLL 53
|
||||
#define CLK_TOP_MSDCPLL_D2 54
|
||||
#define CLK_TOP_DSPPLL 55
|
||||
#define CLK_TOP_DSPPLL_D2 56
|
||||
#define CLK_TOP_DSPPLL_D4 57
|
||||
#define CLK_TOP_DSPPLL_D8 58
|
||||
#define CLK_TOP_APUPLL 59
|
||||
#define CLK_TOP_CLK26M_D52 60
|
||||
#define CLK_TOP_AXI_SEL 61
|
||||
#define CLK_TOP_MEM_SEL 62
|
||||
#define CLK_TOP_MM_SEL 63
|
||||
#define CLK_TOP_SCP_SEL 64
|
||||
#define CLK_TOP_MFG_SEL 65
|
||||
#define CLK_TOP_ATB_SEL 66
|
||||
#define CLK_TOP_CAMTG_SEL 67
|
||||
#define CLK_TOP_CAMTG1_SEL 68
|
||||
#define CLK_TOP_UART_SEL 69
|
||||
#define CLK_TOP_SPI_SEL 70
|
||||
#define CLK_TOP_MSDC50_0_HC_SEL 71
|
||||
#define CLK_TOP_MSDC2_2_HC_SEL 72
|
||||
#define CLK_TOP_MSDC50_0_SEL 73
|
||||
#define CLK_TOP_MSDC50_2_SEL 74
|
||||
#define CLK_TOP_MSDC30_1_SEL 75
|
||||
#define CLK_TOP_AUDIO_SEL 76
|
||||
#define CLK_TOP_AUD_INTBUS_SEL 77
|
||||
#define CLK_TOP_AUD_1_SEL 78
|
||||
#define CLK_TOP_AUD_2_SEL 79
|
||||
#define CLK_TOP_AUD_ENGEN1_SEL 80
|
||||
#define CLK_TOP_AUD_ENGEN2_SEL 81
|
||||
#define CLK_TOP_AUD_SPDIF_SEL 82
|
||||
#define CLK_TOP_DISP_PWM_SEL 83
|
||||
#define CLK_TOP_DXCC_SEL 84
|
||||
#define CLK_TOP_SSUSB_SYS_SEL 85
|
||||
#define CLK_TOP_SSUSB_XHCI_SEL 86
|
||||
#define CLK_TOP_SPM_SEL 87
|
||||
#define CLK_TOP_I2C_SEL 88
|
||||
#define CLK_TOP_PWM_SEL 89
|
||||
#define CLK_TOP_SENIF_SEL 90
|
||||
#define CLK_TOP_AES_FDE_SEL 91
|
||||
#define CLK_TOP_CAMTM_SEL 92
|
||||
#define CLK_TOP_DPI0_SEL 93
|
||||
#define CLK_TOP_DPI1_SEL 94
|
||||
#define CLK_TOP_DSP_SEL 95
|
||||
#define CLK_TOP_NFI2X_SEL 96
|
||||
#define CLK_TOP_NFIECC_SEL 97
|
||||
#define CLK_TOP_ECC_SEL 98
|
||||
#define CLK_TOP_ETH_SEL 99
|
||||
#define CLK_TOP_GCPU_SEL 100
|
||||
#define CLK_TOP_GCPU_CPM_SEL 101
|
||||
#define CLK_TOP_APU_SEL 102
|
||||
#define CLK_TOP_APU_IF_SEL 103
|
||||
#define CLK_TOP_MBIST_DIAG_SEL 104
|
||||
#define CLK_TOP_APLL_I2S0_SEL 105
|
||||
#define CLK_TOP_APLL_I2S1_SEL 106
|
||||
#define CLK_TOP_APLL_I2S2_SEL 107
|
||||
#define CLK_TOP_APLL_I2S3_SEL 108
|
||||
#define CLK_TOP_APLL_TDMOUT_SEL 109
|
||||
#define CLK_TOP_APLL_TDMIN_SEL 110
|
||||
#define CLK_TOP_APLL_SPDIF_SEL 111
|
||||
#define CLK_TOP_APLL12_CK_DIV0 112
|
||||
#define CLK_TOP_APLL12_CK_DIV1 113
|
||||
#define CLK_TOP_APLL12_CK_DIV2 114
|
||||
#define CLK_TOP_APLL12_CK_DIV3 115
|
||||
#define CLK_TOP_APLL12_CK_DIV4 116
|
||||
#define CLK_TOP_APLL12_CK_DIV4B 117
|
||||
#define CLK_TOP_APLL12_CK_DIV5 118
|
||||
#define CLK_TOP_APLL12_CK_DIV5B 119
|
||||
#define CLK_TOP_APLL12_CK_DIV6 120
|
||||
#define CLK_TOP_AUD_I2S0_M 121
|
||||
#define CLK_TOP_AUD_I2S1_M 122
|
||||
#define CLK_TOP_AUD_I2S2_M 123
|
||||
#define CLK_TOP_AUD_I2S3_M 124
|
||||
#define CLK_TOP_AUD_TDMOUT_M 125
|
||||
#define CLK_TOP_AUD_TDMOUT_B 126
|
||||
#define CLK_TOP_AUD_TDMIN_M 127
|
||||
#define CLK_TOP_AUD_TDMIN_B 128
|
||||
#define CLK_TOP_AUD_SPDIF_M 129
|
||||
#define CLK_TOP_USB20_48M_EN 130
|
||||
#define CLK_TOP_UNIVPLL_48M_EN 131
|
||||
#define CLK_TOP_LVDSTX_CLKDIG_EN 132
|
||||
#define CLK_TOP_VPLL_DPIX_EN 133
|
||||
#define CLK_TOP_SSUSB_TOP_CK_EN 134
|
||||
#define CLK_TOP_SSUSB_PHY_CK_EN 135
|
||||
#define CLK_TOP_CONN_32K 136
|
||||
#define CLK_TOP_CONN_26M 137
|
||||
#define CLK_TOP_DSP_32K 138
|
||||
#define CLK_TOP_DSP_26M 139
|
||||
#define CLK_TOP_NR_CLK 140
|
||||
#define CLK_TOP_CLK26M 141
|
||||
#define CLK_TOP_CLK32K 142
|
||||
|
||||
/* INFRACFG */
|
||||
#define CLK_IFR_PMIC_TMR 0
|
||||
#define CLK_IFR_PMIC_AP 1
|
||||
#define CLK_IFR_PMIC_MD 2
|
||||
#define CLK_IFR_PMIC_CONN 3
|
||||
#define CLK_IFR_ICUSB 4
|
||||
#define CLK_IFR_GCE 5
|
||||
#define CLK_IFR_THERM 6
|
||||
#define CLK_IFR_PWM_HCLK 7
|
||||
#define CLK_IFR_PWM1 8
|
||||
#define CLK_IFR_PWM2 9
|
||||
#define CLK_IFR_PWM3 10
|
||||
#define CLK_IFR_PWM4 11
|
||||
#define CLK_IFR_PWM5 12
|
||||
#define CLK_IFR_PWM 13
|
||||
#define CLK_IFR_UART0 14
|
||||
#define CLK_IFR_UART1 15
|
||||
#define CLK_IFR_UART2 16
|
||||
#define CLK_IFR_DSP_UART 17
|
||||
#define CLK_IFR_GCE_26M 18
|
||||
#define CLK_IFR_CQ_DMA_FPC 19
|
||||
#define CLK_IFR_BTIF 20
|
||||
#define CLK_IFR_SPI0 21
|
||||
#define CLK_IFR_MSDC0_HCLK 22
|
||||
#define CLK_IFR_MSDC2_HCLK 23
|
||||
#define CLK_IFR_MSDC1_HCLK 24
|
||||
#define CLK_IFR_DVFSRC 25
|
||||
#define CLK_IFR_GCPU 26
|
||||
#define CLK_IFR_TRNG 27
|
||||
#define CLK_IFR_AUXADC 28
|
||||
#define CLK_IFR_CPUM 29
|
||||
#define CLK_IFR_AUXADC_MD 30
|
||||
#define CLK_IFR_AP_DMA 31
|
||||
#define CLK_IFR_DEBUGSYS 32
|
||||
#define CLK_IFR_AUDIO 33
|
||||
#define CLK_IFR_PWM_FBCLK6 34
|
||||
#define CLK_IFR_DISP_PWM 35
|
||||
#define CLK_IFR_AUD_26M_BK 36
|
||||
#define CLK_IFR_CQ_DMA 37
|
||||
#define CLK_IFR_MSDC0_SF 38
|
||||
#define CLK_IFR_MSDC1_SF 39
|
||||
#define CLK_IFR_MSDC2_SF 40
|
||||
#define CLK_IFR_AP_MSDC0 41
|
||||
#define CLK_IFR_MD_MSDC0 42
|
||||
#define CLK_IFR_MSDC0_SRC 43
|
||||
#define CLK_IFR_MSDC1_SRC 44
|
||||
#define CLK_IFR_MSDC2_SRC 45
|
||||
#define CLK_IFR_PWRAP_TMR 46
|
||||
#define CLK_IFR_PWRAP_SPI 47
|
||||
#define CLK_IFR_PWRAP_SYS 48
|
||||
#define CLK_IFR_MCU_PM_BK 49
|
||||
#define CLK_IFR_IRRX_26M 50
|
||||
#define CLK_IFR_IRRX_32K 51
|
||||
#define CLK_IFR_I2C0_AXI 52
|
||||
#define CLK_IFR_I2C1_AXI 53
|
||||
#define CLK_IFR_I2C2_AXI 54
|
||||
#define CLK_IFR_I2C3_AXI 55
|
||||
#define CLK_IFR_NIC_AXI 56
|
||||
#define CLK_IFR_NIC_SLV_AXI 57
|
||||
#define CLK_IFR_APU_AXI 58
|
||||
#define CLK_IFR_NFIECC 59
|
||||
#define CLK_IFR_NFIECC_BK 60
|
||||
#define CLK_IFR_NFI1X_BK 61
|
||||
#define CLK_IFR_NFI_BK 62
|
||||
#define CLK_IFR_MSDC2_AP_BK 63
|
||||
#define CLK_IFR_MSDC2_MD_BK 64
|
||||
#define CLK_IFR_MSDC2_BK 65
|
||||
#define CLK_IFR_SUSB_133_BK 66
|
||||
#define CLK_IFR_SUSB_66_BK 67
|
||||
#define CLK_IFR_SSUSB_SYS 68
|
||||
#define CLK_IFR_SSUSB_REF 69
|
||||
#define CLK_IFR_SSUSB_XHCI 70
|
||||
#define CLK_IFR_NR_CLK 71
|
||||
|
||||
/* PERICFG */
|
||||
#define CLK_PERIAXI 0
|
||||
#define CLK_PERI_NR_CLK 1
|
||||
|
||||
/* APMIXEDSYS */
|
||||
#define CLK_APMIXED_ARMPLL 0
|
||||
#define CLK_APMIXED_MAINPLL 1
|
||||
#define CLK_APMIXED_UNIVPLL 2
|
||||
#define CLK_APMIXED_MFGPLL 3
|
||||
#define CLK_APMIXED_MSDCPLL 4
|
||||
#define CLK_APMIXED_MMPLL 5
|
||||
#define CLK_APMIXED_APLL1 6
|
||||
#define CLK_APMIXED_APLL2 7
|
||||
#define CLK_APMIXED_LVDSPLL 8
|
||||
#define CLK_APMIXED_DSPPLL 9
|
||||
#define CLK_APMIXED_APUPLL 10
|
||||
#define CLK_APMIXED_UNIV_EN 11
|
||||
#define CLK_APMIXED_USB20_EN 12
|
||||
#define CLK_APMIXED_NR_CLK 13
|
||||
|
||||
/* GCE */
|
||||
#define CLK_GCE_FAXI 0
|
||||
#define CLK_GCE_NR_CLK 1
|
||||
|
||||
/* AUDIOTOP */
|
||||
#define CLK_AUD_AFE 0
|
||||
#define CLK_AUD_I2S 1
|
||||
#define CLK_AUD_22M 2
|
||||
#define CLK_AUD_24M 3
|
||||
#define CLK_AUD_INTDIR 4
|
||||
#define CLK_AUD_APLL2_TUNER 5
|
||||
#define CLK_AUD_APLL_TUNER 6
|
||||
#define CLK_AUD_SPDF 7
|
||||
#define CLK_AUD_HDMI 8
|
||||
#define CLK_AUD_HDMI_IN 9
|
||||
#define CLK_AUD_ADC 10
|
||||
#define CLK_AUD_DAC 11
|
||||
#define CLK_AUD_DAC_PREDIS 12
|
||||
#define CLK_AUD_TML 13
|
||||
#define CLK_AUD_I2S1_BK 14
|
||||
#define CLK_AUD_I2S2_BK 15
|
||||
#define CLK_AUD_I2S3_BK 16
|
||||
#define CLK_AUD_I2S4_BK 17
|
||||
#define CLK_AUD_NR_CLK 18
|
||||
|
||||
/* MIPI_CSI0A */
|
||||
#define CLK_MIPI0A_CSR_CSI_EN_0A 0
|
||||
#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1
|
||||
|
||||
/* MIPI_CSI0B */
|
||||
#define CLK_MIPI0B_CSR_CSI_EN_0B 0
|
||||
#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1
|
||||
|
||||
/* MIPI_CSI1A */
|
||||
#define CLK_MIPI1A_CSR_CSI_EN_1A 0
|
||||
#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1
|
||||
|
||||
/* MIPI_CSI1B */
|
||||
#define CLK_MIPI1B_CSR_CSI_EN_1B 0
|
||||
#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1
|
||||
|
||||
/* MIPI_CSI2A */
|
||||
#define CLK_MIPI2A_CSR_CSI_EN_2A 0
|
||||
#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1
|
||||
|
||||
/* MIPI_CSI2B */
|
||||
#define CLK_MIPI2B_CSR_CSI_EN_2B 0
|
||||
#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1
|
||||
|
||||
/* MCUCFG */
|
||||
#define CLK_MCU_BUS_SEL 0
|
||||
#define CLK_MCU_NR_CLK 1
|
||||
|
||||
/* MFGCFG */
|
||||
#define CLK_MFG_BG3D 0
|
||||
#define CLK_MFG_MBIST_DIAG 1
|
||||
#define CLK_MFG_NR_CLK 2
|
||||
|
||||
/* MMSYS */
|
||||
#define CLK_MM_MM_MDP_RDMA0 0
|
||||
#define CLK_MM_MM_MDP_CCORR0 1
|
||||
#define CLK_MM_MM_MDP_RSZ0 2
|
||||
#define CLK_MM_MM_MDP_RSZ1 3
|
||||
#define CLK_MM_MM_MDP_TDSHP0 4
|
||||
#define CLK_MM_MM_MDP_WROT0 5
|
||||
#define CLK_MM_MM_MDP_WDMA0 6
|
||||
#define CLK_MM_MM_DISP_OVL0 7
|
||||
#define CLK_MM_MM_DISP_OVL0_2L 8
|
||||
#define CLK_MM_MM_DISP_RSZ0 9
|
||||
#define CLK_MM_MM_DISP_RDMA0 10
|
||||
#define CLK_MM_MM_DISP_WDMA0 11
|
||||
#define CLK_MM_MM_DISP_COLOR0 12
|
||||
#define CLK_MM_MM_DISP_CCORR0 13
|
||||
#define CLK_MM_MM_DISP_AAL0 14
|
||||
#define CLK_MM_MM_DISP_GAMMA0 15
|
||||
#define CLK_MM_MM_DISP_DITHER0 16
|
||||
#define CLK_MM_MM_DSI0 17
|
||||
#define CLK_MM_MM_DISP_RDMA1 18
|
||||
#define CLK_MM_MM_MDP_RDMA1 19
|
||||
#define CLK_MM_DPI0_DPI0 20
|
||||
#define CLK_MM_MM_FAKE 21
|
||||
#define CLK_MM_MM_SMI_COMMON 22
|
||||
#define CLK_MM_MM_SMI_LARB0 23
|
||||
#define CLK_MM_MM_SMI_COMM0 24
|
||||
#define CLK_MM_MM_SMI_COMM1 25
|
||||
#define CLK_MM_MM_CAM_MDP 26
|
||||
#define CLK_MM_MM_SMI_IMG 27
|
||||
#define CLK_MM_MM_SMI_CAM 28
|
||||
#define CLK_MM_IMG_IMG_DL_RELAY 29
|
||||
#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30
|
||||
#define CLK_MM_DSI0_DIG_DSI 31
|
||||
#define CLK_MM_26M_HRTWT 32
|
||||
#define CLK_MM_MM_DPI0 33
|
||||
#define CLK_MM_LVDSTX_PXL 34
|
||||
#define CLK_MM_LVDSTX_CTS 35
|
||||
#define CLK_MM_NR_CLK 36
|
||||
|
||||
/* IMGSYS */
|
||||
#define CLK_CAM_LARB2 0
|
||||
#define CLK_CAM 1
|
||||
#define CLK_CAMTG 2
|
||||
#define CLK_CAM_SENIF 3
|
||||
#define CLK_CAMSV0 4
|
||||
#define CLK_CAMSV1 5
|
||||
#define CLK_CAM_FDVT 6
|
||||
#define CLK_CAM_WPE 7
|
||||
#define CLK_CAM_NR_CLK 8
|
||||
|
||||
/* VDECSYS */
|
||||
#define CLK_VDEC_VDEC 0
|
||||
#define CLK_VDEC_LARB1 1
|
||||
#define CLK_VDEC_NR_CLK 2
|
||||
|
||||
/* VENCSYS */
|
||||
#define CLK_VENC 0
|
||||
#define CLK_VENC_JPGENC 1
|
||||
#define CLK_VENC_NR_CLK 2
|
||||
|
||||
/* APUSYS */
|
||||
#define CLK_APU_IPU_CK 0
|
||||
#define CLK_APU_AXI 1
|
||||
#define CLK_APU_JTAG 2
|
||||
#define CLK_APU_IF_CK 3
|
||||
#define CLK_APU_EDMA 4
|
||||
#define CLK_APU_AHB 5
|
||||
#define CLK_APU_NR_CLK 6
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8365_H */
|
||||
858
include/dt-bindings/pinctrl/mt8365-pinfunc.h
Normal file
858
include/dt-bindings/pinctrl/mt8365-pinfunc.h
Normal file
|
|
@ -0,0 +1,858 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2021 MediaTek Inc.
|
||||
*/
|
||||
#ifndef __MT8365_PINFUNC_H
|
||||
#define __MT8365_PINFUNC_H
|
||||
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
|
||||
#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
|
||||
#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1)
|
||||
#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2)
|
||||
#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)
|
||||
#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)
|
||||
#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5)
|
||||
#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
|
||||
|
||||
#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
|
||||
#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1)
|
||||
#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2)
|
||||
#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3)
|
||||
#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)
|
||||
#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5)
|
||||
#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7)
|
||||
|
||||
#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
|
||||
#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1)
|
||||
#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2)
|
||||
#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3)
|
||||
#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)
|
||||
#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5)
|
||||
#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7)
|
||||
|
||||
#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
|
||||
#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1)
|
||||
#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2)
|
||||
#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3)
|
||||
#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)
|
||||
#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5)
|
||||
#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6)
|
||||
#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7)
|
||||
|
||||
#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
|
||||
#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1)
|
||||
#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2)
|
||||
#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3)
|
||||
#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)
|
||||
#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5)
|
||||
#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6)
|
||||
#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7)
|
||||
|
||||
#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
|
||||
#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1)
|
||||
#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2)
|
||||
#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3)
|
||||
#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)
|
||||
#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5)
|
||||
#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6)
|
||||
#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7)
|
||||
|
||||
#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
|
||||
#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1)
|
||||
#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2)
|
||||
#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3)
|
||||
#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)
|
||||
#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5)
|
||||
#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6)
|
||||
#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7)
|
||||
|
||||
#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
|
||||
#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1)
|
||||
#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3)
|
||||
#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)
|
||||
#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5)
|
||||
#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7)
|
||||
|
||||
#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
|
||||
#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1)
|
||||
#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2)
|
||||
#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3)
|
||||
#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)
|
||||
#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5)
|
||||
#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7)
|
||||
|
||||
#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
|
||||
#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1)
|
||||
#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2)
|
||||
#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3)
|
||||
#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)
|
||||
#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5)
|
||||
#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7)
|
||||
|
||||
#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
|
||||
#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1)
|
||||
#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2)
|
||||
#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3)
|
||||
#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)
|
||||
#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5)
|
||||
#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7)
|
||||
|
||||
#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
|
||||
#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1)
|
||||
#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2)
|
||||
#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3)
|
||||
#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4)
|
||||
#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5)
|
||||
#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7)
|
||||
|
||||
#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
|
||||
#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1)
|
||||
#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2)
|
||||
#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3)
|
||||
#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4)
|
||||
#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5)
|
||||
#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7)
|
||||
|
||||
#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
|
||||
#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1)
|
||||
#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2)
|
||||
#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3)
|
||||
#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4)
|
||||
#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5)
|
||||
#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7)
|
||||
|
||||
#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
|
||||
#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1)
|
||||
#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2)
|
||||
#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3)
|
||||
#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4)
|
||||
#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5)
|
||||
#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6)
|
||||
#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7)
|
||||
|
||||
#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
|
||||
#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1)
|
||||
#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2)
|
||||
#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3)
|
||||
#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4)
|
||||
#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5)
|
||||
#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6)
|
||||
#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7)
|
||||
|
||||
#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
|
||||
#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1)
|
||||
#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2)
|
||||
#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3)
|
||||
#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4)
|
||||
#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5)
|
||||
#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6)
|
||||
#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7)
|
||||
|
||||
#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
|
||||
#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1)
|
||||
#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2)
|
||||
#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3)
|
||||
#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4)
|
||||
#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5)
|
||||
#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6)
|
||||
#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7)
|
||||
|
||||
#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
|
||||
#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1)
|
||||
#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2)
|
||||
#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3)
|
||||
#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4)
|
||||
#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5)
|
||||
#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6)
|
||||
#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7)
|
||||
|
||||
#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
|
||||
#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1)
|
||||
#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2)
|
||||
#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7)
|
||||
|
||||
#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
|
||||
#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1)
|
||||
#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2)
|
||||
#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7)
|
||||
|
||||
#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
|
||||
#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1)
|
||||
#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2)
|
||||
#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3)
|
||||
#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4)
|
||||
#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7)
|
||||
|
||||
#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
|
||||
#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1)
|
||||
#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7)
|
||||
|
||||
#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
|
||||
#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1)
|
||||
#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2)
|
||||
#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3)
|
||||
#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4)
|
||||
#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5)
|
||||
#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6)
|
||||
#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7)
|
||||
|
||||
#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
|
||||
#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1)
|
||||
#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7)
|
||||
|
||||
#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
|
||||
#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1)
|
||||
#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2)
|
||||
#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3)
|
||||
#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4)
|
||||
#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5)
|
||||
#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6)
|
||||
#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7)
|
||||
|
||||
#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
|
||||
#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1)
|
||||
#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3)
|
||||
#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4)
|
||||
#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5)
|
||||
#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6)
|
||||
#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7)
|
||||
|
||||
#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
|
||||
#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1)
|
||||
#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3)
|
||||
#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4)
|
||||
#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5)
|
||||
#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6)
|
||||
#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7)
|
||||
|
||||
#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
|
||||
#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1)
|
||||
#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2)
|
||||
#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3)
|
||||
#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4)
|
||||
#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5)
|
||||
#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6)
|
||||
#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7)
|
||||
|
||||
#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
|
||||
#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1)
|
||||
#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2)
|
||||
#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3)
|
||||
#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4)
|
||||
#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5)
|
||||
#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6)
|
||||
#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7)
|
||||
|
||||
#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
|
||||
#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1)
|
||||
#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2)
|
||||
#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3)
|
||||
#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4)
|
||||
#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5)
|
||||
#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6)
|
||||
|
||||
#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
|
||||
#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1)
|
||||
#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2)
|
||||
#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3)
|
||||
#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4)
|
||||
#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5)
|
||||
#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6)
|
||||
|
||||
#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
|
||||
#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1)
|
||||
#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2)
|
||||
#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3)
|
||||
#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4)
|
||||
#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5)
|
||||
|
||||
#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
|
||||
#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1)
|
||||
#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2)
|
||||
#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3)
|
||||
#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4)
|
||||
#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5)
|
||||
|
||||
#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
|
||||
#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1)
|
||||
#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2)
|
||||
#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3)
|
||||
#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4)
|
||||
#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5)
|
||||
|
||||
#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
|
||||
#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1)
|
||||
#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2)
|
||||
#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7)
|
||||
|
||||
#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
|
||||
#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1)
|
||||
#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2)
|
||||
#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7)
|
||||
|
||||
#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
|
||||
#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1)
|
||||
#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2)
|
||||
#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3)
|
||||
#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4)
|
||||
#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5)
|
||||
#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6)
|
||||
#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7)
|
||||
|
||||
#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
|
||||
#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1)
|
||||
#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2)
|
||||
#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3)
|
||||
#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4)
|
||||
#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5)
|
||||
#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6)
|
||||
#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7)
|
||||
|
||||
#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
|
||||
#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1)
|
||||
#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2)
|
||||
#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3)
|
||||
#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4)
|
||||
#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5)
|
||||
#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6)
|
||||
#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7)
|
||||
|
||||
#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
|
||||
#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1)
|
||||
#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2)
|
||||
#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3)
|
||||
#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4)
|
||||
#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5)
|
||||
#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6)
|
||||
#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7)
|
||||
|
||||
#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
|
||||
#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1)
|
||||
#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2)
|
||||
|
||||
#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
|
||||
#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1)
|
||||
#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2)
|
||||
|
||||
#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
|
||||
#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1)
|
||||
|
||||
#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
|
||||
#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1)
|
||||
|
||||
#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
|
||||
#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1)
|
||||
|
||||
#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
|
||||
#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1)
|
||||
|
||||
#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
|
||||
#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1)
|
||||
#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2)
|
||||
|
||||
#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
|
||||
#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1)
|
||||
|
||||
#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
|
||||
#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1)
|
||||
#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2)
|
||||
#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3)
|
||||
|
||||
#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
|
||||
#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1)
|
||||
#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2)
|
||||
#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3)
|
||||
|
||||
#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
|
||||
#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1)
|
||||
#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2)
|
||||
#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3)
|
||||
|
||||
#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
|
||||
#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1)
|
||||
#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2)
|
||||
#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3)
|
||||
|
||||
#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
|
||||
#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1)
|
||||
#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2)
|
||||
#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3)
|
||||
|
||||
#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
|
||||
#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1)
|
||||
#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2)
|
||||
#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3)
|
||||
|
||||
#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
|
||||
#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1)
|
||||
#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2)
|
||||
#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3)
|
||||
|
||||
#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
|
||||
#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1)
|
||||
#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2)
|
||||
#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3)
|
||||
|
||||
#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
|
||||
#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1)
|
||||
|
||||
#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
|
||||
#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1)
|
||||
|
||||
#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
|
||||
#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1)
|
||||
#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6)
|
||||
#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7)
|
||||
|
||||
#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
|
||||
#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1)
|
||||
#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6)
|
||||
#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7)
|
||||
|
||||
#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
|
||||
#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1)
|
||||
|
||||
#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
|
||||
#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1)
|
||||
|
||||
#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
|
||||
#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1)
|
||||
|
||||
#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
|
||||
#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1)
|
||||
|
||||
#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
|
||||
#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1)
|
||||
#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2)
|
||||
#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7)
|
||||
|
||||
#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
|
||||
#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1)
|
||||
#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2)
|
||||
#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7)
|
||||
|
||||
#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
|
||||
#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1)
|
||||
#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2)
|
||||
#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4)
|
||||
#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5)
|
||||
#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7)
|
||||
|
||||
#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
|
||||
#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1)
|
||||
#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2)
|
||||
#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4)
|
||||
#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5)
|
||||
#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7)
|
||||
|
||||
#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
|
||||
#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1)
|
||||
#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2)
|
||||
#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3)
|
||||
#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4)
|
||||
#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5)
|
||||
#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7)
|
||||
|
||||
#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
|
||||
#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1)
|
||||
#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2)
|
||||
#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4)
|
||||
#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5)
|
||||
#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7)
|
||||
|
||||
#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
|
||||
#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1)
|
||||
#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2)
|
||||
#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7)
|
||||
|
||||
#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
|
||||
#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1)
|
||||
#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2)
|
||||
#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5)
|
||||
#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7)
|
||||
|
||||
#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
|
||||
#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1)
|
||||
#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2)
|
||||
#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5)
|
||||
#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7)
|
||||
|
||||
#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
|
||||
#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1)
|
||||
#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2)
|
||||
#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5)
|
||||
#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7)
|
||||
|
||||
#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
|
||||
#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1)
|
||||
#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5)
|
||||
#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7)
|
||||
|
||||
#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
|
||||
#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1)
|
||||
#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5)
|
||||
#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7)
|
||||
|
||||
#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
|
||||
#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1)
|
||||
#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5)
|
||||
#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7)
|
||||
|
||||
#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
|
||||
#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1)
|
||||
#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5)
|
||||
#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7)
|
||||
|
||||
#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
|
||||
#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1)
|
||||
#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5)
|
||||
#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7)
|
||||
|
||||
#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
|
||||
#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1)
|
||||
#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2)
|
||||
#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3)
|
||||
#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4)
|
||||
#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5)
|
||||
#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6)
|
||||
|
||||
#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
|
||||
#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1)
|
||||
#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2)
|
||||
#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3)
|
||||
#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4)
|
||||
#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5)
|
||||
#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6)
|
||||
|
||||
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
|
||||
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1)
|
||||
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2)
|
||||
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3)
|
||||
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4)
|
||||
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5)
|
||||
#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6)
|
||||
|
||||
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
|
||||
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1)
|
||||
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2)
|
||||
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3)
|
||||
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4)
|
||||
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5)
|
||||
#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6)
|
||||
|
||||
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
|
||||
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1)
|
||||
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2)
|
||||
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3)
|
||||
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4)
|
||||
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5)
|
||||
#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6)
|
||||
|
||||
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
|
||||
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1)
|
||||
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2)
|
||||
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3)
|
||||
#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5)
|
||||
|
||||
#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
|
||||
#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1)
|
||||
#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2)
|
||||
#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3)
|
||||
|
||||
#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
|
||||
#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1)
|
||||
#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2)
|
||||
#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3)
|
||||
#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4)
|
||||
#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5)
|
||||
#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6)
|
||||
#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7)
|
||||
|
||||
#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
|
||||
#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1)
|
||||
#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2)
|
||||
#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3)
|
||||
#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4)
|
||||
#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5)
|
||||
#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6)
|
||||
#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7)
|
||||
|
||||
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
|
||||
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1)
|
||||
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
|
||||
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3)
|
||||
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4)
|
||||
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5)
|
||||
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6)
|
||||
#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7)
|
||||
|
||||
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
|
||||
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1)
|
||||
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2)
|
||||
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3)
|
||||
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4)
|
||||
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5)
|
||||
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6)
|
||||
#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7)
|
||||
|
||||
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
|
||||
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1)
|
||||
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2)
|
||||
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3)
|
||||
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4)
|
||||
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5)
|
||||
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6)
|
||||
#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7)
|
||||
|
||||
#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
|
||||
#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1)
|
||||
#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2)
|
||||
#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3)
|
||||
|
||||
#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
|
||||
#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1)
|
||||
#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2)
|
||||
|
||||
#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
|
||||
#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1)
|
||||
#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2)
|
||||
|
||||
#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
|
||||
#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1)
|
||||
#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2)
|
||||
|
||||
#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
|
||||
#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1)
|
||||
#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2)
|
||||
|
||||
#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
|
||||
#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1)
|
||||
#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2)
|
||||
|
||||
#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
|
||||
#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1)
|
||||
#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2)
|
||||
|
||||
#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
|
||||
#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1)
|
||||
#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2)
|
||||
|
||||
#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
|
||||
#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1)
|
||||
#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2)
|
||||
|
||||
#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
|
||||
#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1)
|
||||
#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2)
|
||||
|
||||
#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
|
||||
#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1)
|
||||
#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2)
|
||||
|
||||
#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
|
||||
#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1)
|
||||
#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2)
|
||||
|
||||
#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
|
||||
#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1)
|
||||
|
||||
#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
|
||||
#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1)
|
||||
#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2)
|
||||
#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7)
|
||||
|
||||
#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
|
||||
#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1)
|
||||
#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2)
|
||||
#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7)
|
||||
|
||||
#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
|
||||
#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1)
|
||||
#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2)
|
||||
#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7)
|
||||
|
||||
#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
|
||||
#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1)
|
||||
#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2)
|
||||
#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7)
|
||||
|
||||
#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
|
||||
#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1)
|
||||
#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2)
|
||||
#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7)
|
||||
|
||||
#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
|
||||
#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1)
|
||||
#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2)
|
||||
#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3)
|
||||
#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4)
|
||||
#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5)
|
||||
|
||||
#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
|
||||
#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1)
|
||||
#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2)
|
||||
#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3)
|
||||
#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4)
|
||||
#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5)
|
||||
|
||||
#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
|
||||
#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1)
|
||||
#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2)
|
||||
#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3)
|
||||
#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4)
|
||||
#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5)
|
||||
|
||||
#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
|
||||
#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1)
|
||||
#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2)
|
||||
#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3)
|
||||
#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4)
|
||||
#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5)
|
||||
|
||||
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
|
||||
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1)
|
||||
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2)
|
||||
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3)
|
||||
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4)
|
||||
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5)
|
||||
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6)
|
||||
#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7)
|
||||
|
||||
#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
|
||||
#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1)
|
||||
#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2)
|
||||
#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3)
|
||||
#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4)
|
||||
#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5)
|
||||
#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6)
|
||||
#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7)
|
||||
|
||||
#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
|
||||
#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1)
|
||||
#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2)
|
||||
#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3)
|
||||
#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4)
|
||||
#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5)
|
||||
#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6)
|
||||
#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7)
|
||||
|
||||
#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
|
||||
#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1)
|
||||
#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2)
|
||||
#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7)
|
||||
|
||||
#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
|
||||
#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1)
|
||||
#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2)
|
||||
#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7)
|
||||
|
||||
#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
|
||||
#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1)
|
||||
#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2)
|
||||
#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7)
|
||||
|
||||
#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
|
||||
#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1)
|
||||
#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2)
|
||||
#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7)
|
||||
|
||||
#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
|
||||
#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1)
|
||||
#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2)
|
||||
#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7)
|
||||
|
||||
#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
|
||||
#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1)
|
||||
#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2)
|
||||
#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7)
|
||||
|
||||
#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
|
||||
#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1)
|
||||
#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2)
|
||||
#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7)
|
||||
|
||||
#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
|
||||
#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1)
|
||||
#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2)
|
||||
#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7)
|
||||
|
||||
#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
|
||||
#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1)
|
||||
#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2)
|
||||
#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7)
|
||||
|
||||
#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
|
||||
#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1)
|
||||
#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2)
|
||||
|
||||
#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
|
||||
#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1)
|
||||
#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2)
|
||||
|
||||
#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
|
||||
#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1)
|
||||
#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2)
|
||||
#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3)
|
||||
|
||||
#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
|
||||
#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1)
|
||||
#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2)
|
||||
#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3)
|
||||
|
||||
#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
|
||||
#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1)
|
||||
#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2)
|
||||
#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3)
|
||||
|
||||
#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
|
||||
#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1)
|
||||
#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2)
|
||||
#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3)
|
||||
|
||||
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
|
||||
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1)
|
||||
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2)
|
||||
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3)
|
||||
#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7)
|
||||
|
||||
#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
|
||||
#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1)
|
||||
#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7)
|
||||
|
||||
#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
|
||||
#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1)
|
||||
#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7)
|
||||
|
||||
#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
|
||||
#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1)
|
||||
#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7)
|
||||
|
||||
#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
|
||||
#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1)
|
||||
|
||||
#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
|
||||
#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1)
|
||||
|
||||
#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
|
||||
#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1)
|
||||
|
||||
#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
|
||||
#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1)
|
||||
|
||||
#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
|
||||
#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1)
|
||||
|
||||
#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
|
||||
#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1)
|
||||
|
||||
#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
|
||||
#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1)
|
||||
|
||||
#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
|
||||
#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1)
|
||||
|
||||
#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
|
||||
#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1)
|
||||
|
||||
#endif /* __MT8365_PINFUNC_H */
|
||||
19
include/dt-bindings/power/mediatek,mt8365-power.h
Normal file
19
include/dt-bindings/power/mediatek,mt8365-power.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H
|
||||
#define _DT_BINDINGS_POWER_MT8365_POWER_H
|
||||
|
||||
#define MT8365_POWER_DOMAIN_MM 0
|
||||
#define MT8365_POWER_DOMAIN_CONN 1
|
||||
#define MT8365_POWER_DOMAIN_MFG 2
|
||||
#define MT8365_POWER_DOMAIN_AUDIO 3
|
||||
#define MT8365_POWER_DOMAIN_CAM 4
|
||||
#define MT8365_POWER_DOMAIN_DSP 5
|
||||
#define MT8365_POWER_DOMAIN_VDEC 6
|
||||
#define MT8365_POWER_DOMAIN_VENC 7
|
||||
#define MT8365_POWER_DOMAIN_APU 8
|
||||
|
||||
#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */
|
||||
Loading…
Reference in a new issue