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arm: mediatek: add support for MediaTek MT8365 SoC

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This patch adds basic support for MediaTek MT8365 SoC.
The dtsi has been copied from Linux source code tag v6.7-rc2.
(commit 9b5d64654ea8f51fe1e8e29ca1777b620be8fb7c)

Signed-off-by: Julien Masson <jmasson@baylibre.com>
This commit is contained in:
Julien Masson 2023-12-04 11:48:55 +01:00 committed by Tom Rini
parent 80cdb6df22
commit ee33f6539d
6 changed files with 916 additions and 0 deletions
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840
arch/arm/dts/mt8365.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* (C) 2018 MediaTek Inc.
* Copyright (C) 2022 BayLibre SAS
* Fabien Parent <fparent@baylibre.com>
* Bernhard Rosenkränzer <bero@baylibre.com>
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mediatek,mt8365-power.h>
/ {
compatible = "mediatek,mt8365";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-850000000 {
opp-hz = /bits/ 64 <850000000>;
opp-microvolt = <650000>;
};
opp-918000000 {
opp-hz = /bits/ 64 <918000000>;
opp-microvolt = <668750>;
};
opp-987000000 {
opp-hz = /bits/ 64 <987000000>;
opp-microvolt = <687500>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <706250>;
};
opp-1125000000 {
opp-hz = /bits/ 64 <1125000000>;
opp-microvolt = <725000>;
};
opp-1216000000 {
opp-hz = /bits/ 64 <1216000000>;
opp-microvolt = <750000>;
};
opp-1308000000 {
opp-hz = /bits/ 64 <1308000000>;
opp-microvolt = <775000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <800000>;
};
opp-1466000000 {
opp-hz = /bits/ 64 <1466000000>;
opp-microvolt = <825000>;
};
opp-1533000000 {
opp-hz = /bits/ 64 <1533000000>;
opp-microvolt = <850000>;
};
opp-1633000000 {
opp-hz = /bits/ 64 <1633000000>;
opp-microvolt = <887500>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <912500>;
};
opp-1767000000 {
opp-hz = /bits/ 64 <1767000000>;
opp-microvolt = <937500>;
};
opp-1834000000 {
opp-hz = /bits/ 64 <1834000000>;
opp-microvolt = <962500>;
};
opp-1917000000 {
opp-hz = /bits/ 64 <1917000000>;
opp-microvolt = <993750>;
};
opp-2001000000 {
opp-hz = /bits/ 64 <2001000000>;
opp-microvolt = <1025000>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
idle-states {
entry-method = "psci";
CPU_MCDI: cpu-mcdi {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x00010001>;
entry-latency-us = <300>;
exit-latency-us = <200>;
min-residency-us = <1000>;
};
CLUSTER_MCDI: cluster-mcdi {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x01010001>;
entry-latency-us = <350>;
exit-latency-us = <250>;
min-residency-us = <1200>;
};
CLUSTER_DPIDLE: cluster-dpidle {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x01010004>;
entry-latency-us = <300>;
exit-latency-us = <800>;
min-residency-us = <3300>;
};
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
};
};
clk26m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x10000>, /* GICD */
<0 0x0c080000 0 0x80000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8365-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt8365-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt8365-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
};
syscfg_pctl: syscfg-pctl@10005000 {
compatible = "mediatek,mt8365-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
scpsys: syscon@10006000 {
compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8365-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8365_POWER_DOMAIN_MM {
reg = <MT8365_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&mmsys CLK_MM_MM_SMI_COMMON>,
<&mmsys CLK_MM_MM_SMI_COMM0>,
<&mmsys CLK_MM_MM_SMI_COMM1>,
<&mmsys CLK_MM_MM_SMI_LARB0>;
clock-names = "mm", "mm-0", "mm-1",
"mm-2", "mm-3";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
mediatek,infracfg-nao = <&infracfg_nao>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@MT8365_POWER_DOMAIN_CAM {
reg = <MT8365_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB2>,
<&camsys CLK_CAM_SENIF>,
<&camsys CLK_CAMSV0>,
<&camsys CLK_CAMSV1>,
<&camsys CLK_CAM_FDVT>,
<&camsys CLK_CAM_WPE>;
clock-names = "cam-0", "cam-1",
"cam-2", "cam-3",
"cam-4", "cam-5";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
mediatek,smi = <&smi_common>;
};
power-domain@MT8365_POWER_DOMAIN_VDEC {
reg = <MT8365_POWER_DOMAIN_VDEC>;
#power-domain-cells = <0>;
mediatek,smi = <&smi_common>;
};
power-domain@MT8365_POWER_DOMAIN_VENC {
reg = <MT8365_POWER_DOMAIN_VENC>;
#power-domain-cells = <0>;
mediatek,smi = <&smi_common>;
};
power-domain@MT8365_POWER_DOMAIN_APU {
reg = <MT8365_POWER_DOMAIN_APU>;
clocks = <&infracfg CLK_IFR_APU_AXI>,
<&apu CLK_APU_IPU_CK>,
<&apu CLK_APU_AXI>,
<&apu CLK_APU_JTAG>,
<&apu CLK_APU_IF_CK>,
<&apu CLK_APU_EDMA>,
<&apu CLK_APU_AHB>;
clock-names = "apu", "apu-0",
"apu-1", "apu-2",
"apu-3", "apu-4",
"apu-5";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
mediatek,smi = <&smi_common>;
};
};
power-domain@MT8365_POWER_DOMAIN_CONN {
reg = <MT8365_POWER_DOMAIN_CONN>;
clocks = <&topckgen CLK_TOP_CONN_32K>,
<&topckgen CLK_TOP_CONN_26M>;
clock-names = "conn", "conn1";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_MFG {
reg = <MT8365_POWER_DOMAIN_MFG>;
clocks = <&topckgen CLK_TOP_MFG_SEL>;
clock-names = "mfg";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_AUDIO {
reg = <MT8365_POWER_DOMAIN_AUDIO>;
clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&infracfg CLK_IFR_AUDIO>,
<&infracfg CLK_IFR_AUD_26M_BK>;
clock-names = "audio", "audio1", "audio2";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_DSP {
reg = <MT8365_POWER_DOMAIN_DSP>;
clocks = <&topckgen CLK_TOP_DSP_SEL>,
<&topckgen CLK_TOP_DSP_26M>;
clock-names = "dsp", "dsp1";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
#reset-cells = <1>;
};
pio: pinctrl@1000b000 {
compatible = "mediatek,mt8365-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8365-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8365-pwrap";
reg = <0 0x1000d000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
<&infracfg CLK_IFR_PMIC_AP>,
<&infracfg CLK_IFR_PWRAP_SYS>,
<&infracfg CLK_IFR_PWRAP_TMR>;
clock-names = "spi", "wrap", "sys", "tmr";
};
keypad: keypad@10010000 {
compatible = "mediatek,mt6779-keypad";
reg = <0 0x10010000 0 0x1000>;
wakeup-source;
interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk26m>;
clock-names = "kpd";
status = "disabled";
};
mcucfg: syscon@10200000 {
compatible = "mediatek,mt8365-mcucfg", "syscon";
reg = <0 0x10200000 0 0x2000>;
#clock-cells = <1>;
};
sysirq: interrupt-controller@10200a80 {
compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200a80 0 0x20>;
};
iommu: iommu@10205000 {
compatible = "mediatek,mt8365-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>;
#iommu-cells = <1>;
};
infracfg_nao: infracfg@1020e000 {
compatible = "mediatek,mt8365-infracfg", "syscon";
reg = <0 0x1020e000 0 0x1000>;
#clock-cells = <1>;
};
rng: rng@1020f000 {
compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
clocks = <&infracfg CLK_IFR_TRNG>;
clock-names = "rng";
};
apdma: dma-controller@11000280 {
compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
reg = <0 0x11000280 0 0x80>,
<0 0x11000300 0 0x80>,
<0 0x11000380 0 0x80>,
<0 0x11000400 0 0x80>,
<0 0x11000580 0 0x80>,
<0 0x11000600 0 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
dma-requests = <6>;
clocks = <&infracfg CLK_IFR_AP_DMA>;
clock-names = "apdma";
#dma-cells = <1>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
pwm: pwm@11006000 {
compatible = "mediatek,mt8365-pwm";
reg = <0 0x11006000 0 0x1000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_IFR_PWM_HCLK>,
<&infracfg CLK_IFR_PWM>,
<&infracfg CLK_IFR_PWM1>,
<&infracfg CLK_IFR_PWM2>,
<&infracfg CLK_IFR_PWM3>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi: spi@1100a000 {
compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
reg = <0 0x1100a000 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_IFR_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssusb: usb@11201000 {
compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u2port1 PHY_TYPE_USB2>;
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
<&infracfg CLK_IFR_SSUSB_REF>,
<&infracfg CLK_IFR_SSUSB_SYS>,
<&infracfg CLK_IFR_ICUSB>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_host: usb@11200000 {
compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
<&infracfg CLK_IFR_SSUSB_REF>,
<&infracfg CLK_IFR_SSUSB_SYS>,
<&infracfg CLK_IFR_ICUSB>,
<&infracfg CLK_IFR_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck",
"dma_ck", "xhci_ck";
status = "disabled";
};
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11cd0000 0 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
<&infracfg CLK_IFR_MSDC0_HCLK>,
<&infracfg CLK_IFR_MSDC0_SRC>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11c90000 0 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
<&infracfg CLK_IFR_MSDC1_HCLK>,
<&infracfg CLK_IFR_MSDC1_SRC>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc2: mmc@11250000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11250000 0 0x1000>,
<0 0x11c60000 0 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
<&infracfg CLK_IFR_MSDC2_HCLK>,
<&infracfg CLK_IFR_MSDC2_SRC>,
<&infracfg CLK_IFR_MSDC2_BK>,
<&infracfg CLK_IFR_AP_MSDC0>;
clock-names = "source", "hclk", "source_cg",
"bus_clk", "sys_cg";
status = "disabled";
};
ethernet: ethernet@112a0000 {
compatible = "mediatek,mt8365-eth";
reg = <0 0x112a0000 0 0x1000>;
mediatek,pericfg = <&infracfg>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_ETH_SEL>,
<&infracfg CLK_IFR_NIC_AXI>,
<&infracfg CLK_IFR_NIC_SLV_AXI>;
clock-names = "core", "reg", "trans";
status = "disabled";
};
u3phy: t-phy@11cc0000 {
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11cc0000 0x9000>;
u2port0: usb-phy@0 {
reg = <0x0 0x400>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
<&topckgen CLK_TOP_USB20_48M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
u2port1: usb-phy@1000 {
reg = <0x1000 0x400>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
<&topckgen CLK_TOP_USB20_48M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt8365-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
smi_common: smi@14002000 {
compatible = "mediatek,mt8365-smi-common";
reg = <0 0x14002000 0 0x1000>;
clocks = <&mmsys CLK_MM_MM_SMI_COMMON>,
<&mmsys CLK_MM_MM_SMI_COMMON>,
<&mmsys CLK_MM_MM_SMI_COMM0>,
<&mmsys CLK_MM_MM_SMI_COMM1>;
clock-names = "apb", "smi", "gals0", "gals1";
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
};
larb0: larb@14003000 {
compatible = "mediatek,mt8365-smi-larb",
"mediatek,mt8186-smi-larb";
reg = <0 0x14003000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&mmsys CLK_MM_MM_SMI_LARB0>,
<&mmsys CLK_MM_MM_SMI_LARB0>;
clock-names = "apb", "smi";
power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
mediatek,larb-id = <0>;
};
camsys: syscon@15000000 {
compatible = "mediatek,mt8365-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
larb2: larb@15001000 {
compatible = "mediatek,mt8365-smi-larb",
"mediatek,mt8186-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&mmsys CLK_MM_MM_SMI_IMG>,
<&camsys CLK_CAM_LARB2>;
clock-names = "apb", "smi";
power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
mediatek,larb-id = <2>;
};
vdecsys: syscon@16000000 {
compatible = "mediatek,mt8365-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
larb3: larb@16010000 {
compatible = "mediatek,mt8365-smi-larb",
"mediatek,mt8186-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&vdecsys CLK_VDEC_LARB1>,
<&vdecsys CLK_VDEC_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
mediatek,larb-id = <3>;
};
vencsys: syscon@17000000 {
compatible = "mediatek,mt8365-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
larb1: larb@17010000 {
compatible = "mediatek,mt8365-smi-larb",
"mediatek,mt8186-smi-larb";
reg = <0 0x17010000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>;
clock-names = "apb", "smi";
power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
mediatek,larb-id = <1>;
};
apu: syscon@19020000 {
compatible = "mediatek,mt8365-apu", "syscon";
reg = <0 0x19020000 0 0x1000>;
#clock-cells = <1>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
system_clk: dummy13m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
systimer: timer@10017000 {
compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x100>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&system_clk>;
clock-names = "clk13m";
};
};

9
arch/arm/mach-mediatek/Kconfig
View file

@ -76,6 +76,14 @@ config TARGET_MT8183
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
config TARGET_MT8365
bool "MediaTek MT8365 SoC"
select ARM64
help
The MediaTek MT8365 is a ARM64-based SoC with a quad-core Cortex-A53.
It is including UART, SPI, USB2.0 dual role, SD and MMC cards, NAND, PWM,
I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
config TARGET_MT8512
bool "MediaTek MT8512 M1 Board"
select ARM64
@ -133,6 +141,7 @@ config SYS_CONFIG_NAME
default "mt7986" if TARGET_MT7986
default "mt7988" if TARGET_MT7988
default "mt8183" if TARGET_MT8183
default "mt8365" if TARGET_MT8365
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518

1
arch/arm/mach-mediatek/Makefile
View file

@ -11,5 +11,6 @@ obj-$(CONFIG_TARGET_MT7981) += mt7981/
obj-$(CONFIG_TARGET_MT7986) += mt7986/
obj-$(CONFIG_TARGET_MT7988) += mt7988/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
obj-$(CONFIG_TARGET_MT8365) += mt8365/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/

3
arch/arm/mach-mediatek/mt8365/Makefile Normal file
View file

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += init.o

51
arch/arm/mach-mediatek/mt8365/init.c Normal file
View file

@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2023 MediaTek Inc.
* Copyright (C) 2023 BayLibre, SAS
* Author: Julien Masson <jmasson@baylibre.com>
* Author: Fabien Parent <fparent@baylibre.com>
*/
#include <asm/global_data.h>
#include <asm/system.h>
#include <dm/uclass.h>
#include <wdt.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}
int mtk_soc_early_init(void)
{
return 0;
}
void reset_cpu(void)
{
struct udevice *wdt;
if (IS_ENABLED(CONFIG_PSCI_RESET)) {
psci_system_reset();
} else {
uclass_first_device(UCLASS_WDT, &wdt);
if (wdt)
wdt_expire_now(wdt, 0);
}
}
int print_cpuinfo(void)
{
printf("CPU: MediaTek MT8365\n");
return 0;
}

12
include/configs/mt8365.h Normal file
View file

@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration for MT8365 based boards
*
* Copyright (C) 2023 BayLibre, SAS
* Author: Julien Masson <jmasson@baylibre.com>
*/
#ifndef __MT8365_H
#define __MT8365_H
#endif