Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next

- VisionFive2: Enable CONFIG_SYSRESET
- StarFive: Modify starfive timer driver
- AMD/Xilinx: Add MicroBlaze V support
- Unmatched: Migrate to text environment

arch/riscv/Kconfig

@@ -39,6 +39,9 @@ config TARGET_TH1520_LPI4A
 	bool "Support Sipeed's TH1520 Lichee PI 4A Board"
 	select SYS_CACHE_SHIFT_6
 
+config TARGET_XILINX_MBV
+	bool "Support AMD/Xilinx MicroBlaze V"
+
 endchoice
 
 config SYS_ICACHE_OFF
@@ -82,6 +85,7 @@ source "board/sifive/unmatched/Kconfig"
 source "board/sipeed/maix/Kconfig"
 source "board/starfive/visionfive2/Kconfig"
 source "board/thead/th1520_lpi4a/Kconfig"
+source "board/xilinx/mbv/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/andesv5/Kconfig"

arch/riscv/dts/Makefile

@@ -9,6 +9,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
 dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
+dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
+
 include $(srctree)/scripts/Makefile.dts
 
 targets += $(dtb-y)

arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi

@@ -34,6 +34,11 @@
 		device_type = "memory";
 		reg = <0x0 0x40000000 0x2 0x0>;
 	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
+	};
 };
 
 &osc {

arch/riscv/dts/xilinx-mbv32.dts

@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for AMD MicroBlaze V
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "AMD MicroBlaze V 32bit";
+	compatible = "amd,mbv";
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <102000000>;
+		cpu_0: cpu@0 {
+			compatible = "amd,mbv32", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv32imafdc";
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
+			clock-frequency = <102000000>;
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@20000000 {
+		device_type = "memory";
+		reg = <0x20000000 0x20000000>;
+	};
+
+	clk102: clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <102000000>;
+	};
+
+	axi: axi {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		bootph-all;
+
+		axi_intc: interrupt-controller@41200000 {
+			compatible = "xlnx,xps-intc-1.00.a";
+			reg = <0x41200000 0x1000>;
+			interrupt-controller;
+			interrupt-parent = <&cpu0_intc>;
+			#interrupt-cells = <2>;
+			kind-of-intr = <0>;
+		};
+
+		xlnx_timer0: timer@41c00000 {
+			compatible = "xlnx,xps-timer-1.00.a";
+			reg = <0x41c00000 0x1000>;
+			interrupt-parent = <&axi_intc>;
+			interrupts = <1 2>;
+			bootph-all;
+			xlnx,one-timer-only = <0>;
+			clock-names = "s_axi_aclk";
+			clocks = <&clk102>;
+		};
+
+		xlnx_timer1: timer@41c20000 {
+			compatible = "xlnx,xps-timer-1.00.a";
+			reg = <0x41c20000 0x1000>;
+			interrupt-parent = <&axi_intc>;
+			interrupts = <0 2>;
+			xlnx,one-timer-only = <0>;
+			clock-names = "s_axi_aclk";
+			clocks = <&clk102>;
+		};
+
+		uart0: serial@40600000 {
+			compatible = "xlnx,xps-uartlite-1.00.a";
+			reg = <0x40600000 0x1000>;
+			interrupt-parent = <&axi_intc>;
+			interrupts = <2 2>;
+			bootph-all;
+			clocks = <&clk102>;
+			current-speed = <115200>;
+			xlnx,data-bits = <8>;
+			xlnx,use-parity = <0>;
+		};
+	};
+};

board/sifive/unmatched/unmatched.env

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* environment for HiFive Unmatched boards */
+
+kernel_addr_r=0x80200000
+kernel_comp_addr_r=0x88000000
+kernel_comp_size=0x4000000
+fdt_addr_r=0x8c000000
+scriptaddr=0x8c100000
+pxefile_addr_r=0x8c200000
+ramdisk_addr_r=0x8c300000
+type_guid_gpt_loader1=5B193300-FC78-40CD-8002-E86C45580B47
+type_guid_gpt_loader2=2E54B353-1271-4842-806F-E436D6AF6985
+type_guid_gpt_system=0FC63DAF-8483-4772-8E79-3D69D8477DE4
+partitions=
+    name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};
+    name=loader2,size=4MB,type=${type_guid_gpt_loader2};
+    name=system,size=-,bootable,type=${type_guid_gpt_system};
+fdtfile= CONFIG_DEFAULT_FDT_FILE

board/xilinx/Kconfig

@@ -51,10 +51,11 @@ config XILINX_OF_BOARD_DTB_ADDR
 
 config BOOT_SCRIPT_OFFSET
 	hex "Boot script offset"
-	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV
 	default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
 	default 0x3E80000 if ARCH_ZYNQMP
 	default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET
+	default 0 if TARGET_XILINX_MBV
 	help
 	   Specifies distro boot script offset in NAND/QSPI/NOR flash.
 

board/xilinx/common/board.c

@@ -652,6 +652,11 @@ int embedded_dtb_select(void)
 #endif
 
 #if defined(CONFIG_LMB)
+
+#ifndef MMU_SECTION_SIZE
+#define MMU_SECTION_SIZE        (1 * 1024 * 1024)
+#endif
+
 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 {
 	phys_size_t size;

board/xilinx/mbv/Kconfig

@@ -0,0 +1,28 @@
+if TARGET_XILINX_MBV
+
+config SYS_BOARD
+	default "mbv"
+
+config SYS_VENDOR
+	default "xilinx"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "xilinx_mbv"
+
+config TEXT_BASE
+	default 0x80000000 if !RISCV_SMODE
+	default 0x80400000 if RISCV_SMODE && ARCH_RV32I
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select GENERIC_RISCV
+	imply BOARD_LATE_INIT
+	imply CMD_SBI
+	imply CMD_PING
+
+source "board/xilinx/Kconfig"
+
+endif

board/xilinx/mbv/MAINTAINERS

@@ -0,0 +1,7 @@
+XILINX MicroBlaze V BOARD
+M:	Michal Simek <michal.simek@amd.com>
+S:	Maintained
+F:	arch/riscv/dts/xilinx-mbv*
+F:	board/xilinx/mbv/
+F:	configs/xilinx_mbv*
+F:	include/configs/xilinx_mbv.h

board/xilinx/mbv/Makefile

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+obj-y	+= board.o

board/xilinx/mbv/board.c

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}

configs/sifive_unmatched_defconfig

@@ -23,7 +23,7 @@ CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
 CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"

configs/starfive_visionfive2_defconfig

@@ -125,6 +125,7 @@ CONFIG_DM_RNG=y
 CONFIG_RNG_JH7110=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
 CONFIG_TIMER_EARLY=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

configs/xilinx_mbv32_defconfig

@@ -0,0 +1,30 @@
+CONFIG_RISCV=y
+CONFIG_TEXT_BASE=0x21200000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
+CONFIG_DEBUG_UART_BASE=0x40600000
+CONFIG_DEBUG_UART_CLOCK=1000000
+CONFIG_SYS_CLK_FREQ=100000000
+CONFIG_BOOT_SCRIPT_OFFSET=0x0
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_DEBUG_UART=y
+CONFIG_TARGET_XILINX_MBV=y
+CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_MTD=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_XILINX_UARTLITE=y
+CONFIG_XILINX_TIMER=y
+CONFIG_PANIC_HANG=y

configs/xilinx_mbv32_smode_defconfig

@@ -0,0 +1,32 @@
+CONFIG_RISCV=y
+CONFIG_TEXT_BASE=0x21200000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
+CONFIG_DEBUG_UART_BASE=0x40600000
+CONFIG_DEBUG_UART_CLOCK=1000000
+CONFIG_SYS_CLK_FREQ=100000000
+CONFIG_BOOT_SCRIPT_OFFSET=0x0
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_TARGET_XILINX_MBV=y
+CONFIG_RISCV_SMODE=y
+CONFIG_FIT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_MTD=y
+CONFIG_DEBUG_UART_UARTLITE=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_XILINX_UARTLITE=y
+# CONFIG_RISCV_TIMER is not set
+CONFIG_XILINX_TIMER=y
+CONFIG_PANIC_HANG=y

drivers/timer/starfive-timer.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2022 StarFive, Inc. All rights reserved.
- *   Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ *   Author: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
  */
 
 #include <common.h>
@@ -48,8 +48,8 @@ static int starfive_probe(struct udevice *dev)
 	int ret;
 
 	priv->base = dev_read_addr_ptr(dev);
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
+	if (!priv->base)
+		return -EINVAL;
 
 	timer_channel = dev_read_u32_default(dev, "channel", 0);
 	priv->base = priv->base + (0x40 * timer_channel);
@@ -64,14 +64,16 @@ static int starfive_probe(struct udevice *dev)
 		return ret;
 	uc_priv->clock_rate = clk_get_rate(&clk);
 
-	/* Initiate timer, channel 0 */
-	/* Unmask Interrupt Mask */
+	/*
+	 * Initiate timer, channel 0
+	 * Unmask Interrupt Mask
+	 */
 	writel(0, priv->base + STF_TIMER_INT_MASK);
 	/* Single run mode Setting */
 	if (dev_read_bool(dev, "single-run"))
 		writel(1, priv->base + STF_TIMER_CTL);
 	/* Set Reload value */
-	priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff);
+	priv->timer_size = dev_read_u32_default(dev, "timer-size", -1U);
 	writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
 	/* Enable to start timer */
 	writel(1, priv->base + STF_TIMER_ENABLE);
@@ -85,7 +87,7 @@ static const struct udevice_id starfive_ids[] = {
 };
 
 U_BOOT_DRIVER(jh8100_starfive_timer) = {
-	.name		= "jh8100_starfive_timer",
+	.name		= "starfive_timer",
 	.id		= UCLASS_TIMER,
 	.of_match	= starfive_ids,
 	.probe		= starfive_probe,

include/configs/sifive-unmatched.h

@@ -13,41 +13,4 @@
 
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
-/* Environment options */
-
-#define BOOT_TARGET_DEVICES(func) \
-	func(NVME, nvme, 0) \
-	func(NVME, nvme, 1) \
-	func(USB, usb, 0) \
-	func(MMC, mmc, 0) \
-	func(SCSI, scsi, 0) \
-	func(PXE, pxe, na) \
-	func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-#define TYPE_GUID_LOADER1	"5B193300-FC78-40CD-8002-E86C45580B47"
-#define TYPE_GUID_LOADER2	"2E54B353-1271-4842-806F-E436D6AF6985"
-#define TYPE_GUID_SYSTEM	"0FC63DAF-8483-4772-8E79-3D69D8477DE4"
-
-#define PARTS_DEFAULT \
-	"name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
-	"name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
-	"name=system,size=-,bootable,type=${type_guid_gpt_system};"
-
-#define CFG_EXTRA_ENV_SETTINGS \
-	"kernel_addr_r=0x80200000\0" \
-	"kernel_comp_addr_r=0x88000000\0" \
-	"kernel_comp_size=0x4000000\0" \
-	"fdt_addr_r=0x8c000000\0" \
-	"scriptaddr=0x8c100000\0" \
-	"pxefile_addr_r=0x8c200000\0" \
-	"ramdisk_addr_r=0x8c300000\0" \
-	"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
-	"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
-	"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
-	"partitions=" PARTS_DEFAULT "\0" \
-	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	BOOTENV
-
 #endif /* __SIFIVE_UNMATCHED_H */

include/configs/xilinx_mbv.h

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */