mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 07:31:15 +00:00
- Add support for new GXL MDIO mux, with driver and Linux DT sync from v6.4
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This commit is contained in:
commit
f7655af980
28 changed files with 342 additions and 90 deletions
|
@ -17,7 +17,7 @@
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|||
io-channel-names = "buttons";
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||||
keyup-threshold-microvolt = <1800000>;
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||||
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update-button {
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button-update {
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label = "update";
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linux,code = <KEY_VENDOR>;
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press-threshold-microvolt = <1300000>;
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@ -416,7 +416,7 @@
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pinctrl-names = "default";
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status = "okay";
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gd25lq128: spi-flash@0 {
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gd25lq128: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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|
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@ -49,6 +49,12 @@
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no-map;
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};
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/* 32 MiB reserved for ARM Trusted Firmware (BL32) */
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secmon_reserved_bl32: secmon@5300000 {
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reg = <0x0 0x05300000 0x0 0x2000000>;
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no-map;
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};
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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@ -126,6 +132,7 @@
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l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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@ -226,7 +233,7 @@
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reg = <0x14 0x10>;
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};
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eth_mac: eth_mac@34 {
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eth_mac: eth-mac@34 {
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reg = <0x34 0x10>;
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};
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@ -243,7 +250,7 @@
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scpi_clocks: clocks {
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compatible = "arm,scpi-clocks";
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scpi_dvfs: scpi_clocks@0 {
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scpi_dvfs: clocks-0 {
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compatible = "arm,scpi-dvfs-clocks";
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#clock-cells = <1>;
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clock-indices = <0>;
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@ -444,7 +451,7 @@
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sysctrl_AO: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
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reg = <0x0 0x0 0x0 0x100>;
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reg = <0x0 0x0 0x0 0x100>;
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-gx-aoclkc";
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@ -525,7 +532,7 @@
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
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hwrng: rng {
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hwrng: rng@0 {
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compatible = "amlogic,meson-rng";
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reg = <0x0 0x0 0x0 0x4>;
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};
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@ -596,21 +603,21 @@
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sd_emmc_a: mmc@70000 {
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compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
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reg = <0x0 0x70000 0x0 0x800>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sd_emmc_b: mmc@72000 {
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compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
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reg = <0x0 0x72000 0x0 0x800>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sd_emmc_c: mmc@74000 {
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compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
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reg = <0x0 0x74000 0x0 0x800>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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|
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@ -385,9 +385,20 @@
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/* Bluetooth on AP6212 */
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&uart_A {
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status = "disabled";
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status = "okay";
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pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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bluetooth {
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compatible = "brcm,bcm43438-bt";
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clocks = <&wifi_32k>;
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clock-names = "lpo";
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vbat-supply = <&vddio_ao3v3>;
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vddio-supply = <&vddio_ao18>;
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host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
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shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
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};
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};
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/* 40-pin CON1 */
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@ -250,21 +250,6 @@
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};
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};
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&gpio_ao {
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/*
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* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
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* to be turned high in order to be detected by the USB Controller
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* This signal should be handled by a USB specific power sequence
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* in order to reset the Hub when USB bus is powered down.
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*/
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hog-0 {
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gpio-hog;
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gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb-hub-reset";
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};
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};
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&hdmi_tx {
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status = "okay";
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pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
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@ -414,5 +399,16 @@
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};
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&usb1 {
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dr_mode = "host";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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hub@1 {
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/* Genesys Logic GL852G USB 2.0 hub */
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compatible = "usb5e3,610";
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reg = <1>;
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vdd-supply = <&p5v0>;
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reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
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};
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};
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@ -300,8 +300,8 @@
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};
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&gpio_intc {
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compatible = "amlogic,meson-gpio-intc",
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"amlogic,meson-gxbb-gpio-intc";
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compatible = "amlogic,meson-gxbb-gpio-intc",
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"amlogic,meson-gpio-intc";
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status = "okay";
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};
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@ -427,6 +427,20 @@
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};
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};
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spi_idle_high_pins: spi-idle-high-pins {
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mux {
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groups = "spi_sclk";
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bias-pull-up;
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};
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};
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spi_idle_low_pins: spi-idle-low-pins {
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mux {
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groups = "spi_sclk";
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bias-pull-down;
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};
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};
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spi_ss0_pins: spi-ss0 {
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mux {
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groups = "spi_ss0";
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@ -298,7 +298,7 @@
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pinctrl-0 = <&nor_pins>;
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pinctrl-names = "default";
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w25q32: spi-flash@0 {
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w25q32: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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@ -86,11 +86,11 @@
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};
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&efuse {
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bt_mac: bt_mac@6 {
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bt_mac: bt-mac@6 {
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reg = <0x6 0x6>;
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};
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wifi_mac: wifi_mac@C {
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wifi_mac: wifi-mac@c {
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reg = <0xc 0x6>;
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};
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};
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@ -213,6 +213,12 @@
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pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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bluetooth {
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compatible = "realtek,rtl8822cs-bt";
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enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
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host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
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};
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};
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&uart_C {
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@ -233,7 +239,7 @@
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_b_pins>;
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pcf8563: pcf8563@51 {
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pcf8563: rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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status = "okay";
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@ -140,7 +140,6 @@
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compatible = "haoyu,hym8563";
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reg = <0x51>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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};
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};
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@ -218,20 +217,7 @@
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};
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&sd_emmc_a {
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brcmf: wifi@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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};
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};
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&uart_A {
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bluetooth {
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compatible = "brcm,bcm43438-bt";
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shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
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max-speed = <2000000>;
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clocks = <&wifi32k>;
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clock-names = "lpo";
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};
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max-frequency = <100000000>;
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};
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/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
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@ -284,7 +284,7 @@
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pinctrl-0 = <&nor_pins>;
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pinctrl-names = "default";
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nor_4u1: spi-flash@0 {
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nor_4u1: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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@ -305,7 +305,6 @@
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};
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&usb2_phy0 {
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pinctrl-names = "default";
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phy-supply = <&vcc5v>;
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};
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|
|
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@ -7,11 +7,19 @@
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/dts-v1/;
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#include "meson-gxl-s905x-p212.dtsi"
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#include <dt-bindings/sound/meson-aiu.h>
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/ {
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compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
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model = "Amlogic Meson GXL (S905X) P212 Development Board";
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dio2133: analog-amplifier {
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compatible = "simple-audio-amplifier";
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sound-name-prefix = "AU2";
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VCC-supply = <&hdmi_5v>;
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enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
|
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};
|
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|
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cvbs-connector {
|
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compatible = "composite-video-connector";
|
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|
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|
@ -32,6 +40,66 @@
|
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};
|
||||
};
|
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};
|
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|
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sound {
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compatible = "amlogic,gx-sound-card";
|
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model = "S905X-P212";
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audio-aux-devs = <&dio2133>;
|
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audio-widgets = "Line", "Lineout";
|
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audio-routing = "AU2 INL", "ACODEC LOLN",
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"AU2 INR", "ACODEC LORN",
|
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"Lineout", "AU2 OUTL",
|
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"Lineout", "AU2 OUTR";
|
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assigned-clocks = <&clkc CLKID_MPLL0>,
|
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<&clkc CLKID_MPLL1>,
|
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<&clkc CLKID_MPLL2>;
|
||||
assigned-clock-parents = <0>, <0>, <0>;
|
||||
assigned-clock-rates = <294912000>,
|
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<270950400>,
|
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<393216000>;
|
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dai-link-0 {
|
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sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
|
||||
};
|
||||
|
||||
dai-link-1 {
|
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sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
|
||||
dai-format = "i2s";
|
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mclk-fs = <256>;
|
||||
|
||||
codec-0 {
|
||||
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
|
||||
};
|
||||
|
||||
codec-1 {
|
||||
sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
|
||||
};
|
||||
};
|
||||
|
||||
dai-link-2 {
|
||||
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
|
||||
|
||||
codec-0 {
|
||||
sound-dai = <&hdmi_tx>;
|
||||
};
|
||||
};
|
||||
|
||||
dai-link-3 {
|
||||
sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
|
||||
|
||||
codec-0 {
|
||||
sound-dai = <&acodec>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&acodec {
|
||||
AVDD-supply = <&vddio_ao18>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aiu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
|
|
|
@ -97,6 +97,14 @@
|
|||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pwm_ef {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_e_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&clkc CLKID_FCLK_DIV4>;
|
||||
clock-names = "clkin0";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vddio_ao18>;
|
||||
|
@ -125,6 +133,11 @@
|
|||
|
||||
vmmc-supply = <&vddao_3v3>;
|
||||
vqmmc-supply = <&vddio_boot>;
|
||||
|
||||
brcmf: wifi@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
};
|
||||
};
|
||||
|
||||
/* SD card */
|
||||
|
@ -165,14 +178,6 @@
|
|||
vqmmc-supply = <&vddio_boot>;
|
||||
};
|
||||
|
||||
&pwm_ef {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_e_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&clkc CLKID_FCLK_DIV4>;
|
||||
clock-names = "clkin0";
|
||||
};
|
||||
|
||||
/* This is connected to the Bluetooth module: */
|
||||
&uart_A {
|
||||
status = "okay";
|
||||
|
|
|
@ -312,8 +312,8 @@
|
|||
};
|
||||
|
||||
&gpio_intc {
|
||||
compatible = "amlogic,meson-gpio-intc",
|
||||
"amlogic,meson-gxl-gpio-intc";
|
||||
compatible = "amlogic,meson-gxl-gpio-intc",
|
||||
"amlogic,meson-gpio-intc";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -429,6 +429,20 @@
|
|||
};
|
||||
};
|
||||
|
||||
spi_idle_high_pins: spi-idle-high-pins {
|
||||
mux {
|
||||
groups = "spi_sclk";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
spi_idle_low_pins: spi-idle-low-pins {
|
||||
mux {
|
||||
groups = "spi_sclk";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
spi_ss0_pins: spi-ss0 {
|
||||
mux {
|
||||
groups = "spi_ss0";
|
||||
|
@ -759,16 +773,23 @@
|
|||
};
|
||||
};
|
||||
|
||||
eth-phy-mux {
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
eth_phy_mux: mdio@558 {
|
||||
reg = <0x0 0x558 0x0 0xc>;
|
||||
compatible = "amlogic,gxl-mdio-mux";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x55c 0x0 0x4>;
|
||||
mux-mask = <0xffffffff>;
|
||||
clocks = <&clkc CLKID_FCLK_DIV4>;
|
||||
clock-names = "ref";
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
|
||||
internal_mdio: mdio@e40908ff {
|
||||
reg = <0xe40908ff>;
|
||||
external_mdio: mdio@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
internal_mdio: mdio@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
@ -779,12 +800,6 @@
|
|||
max-speed = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
external_mdio: mdio@2009087f {
|
||||
reg = <0x2009087f>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -52,10 +52,11 @@
|
|||
gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH
|
||||
&gpio GPIODV_15 GPIO_ACTIVE_HIGH>;
|
||||
/* Dummy RPM values since fan is optional */
|
||||
gpio-fan,speed-map = <0 0
|
||||
1 1
|
||||
2 2
|
||||
3 3>;
|
||||
gpio-fan,speed-map =
|
||||
<0 0>,
|
||||
<1 1>,
|
||||
<2 2>,
|
||||
<3 3>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
|
@ -270,7 +271,6 @@
|
|||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
};
|
||||
};
|
||||
|
@ -307,7 +307,8 @@
|
|||
#size-cells = <0>;
|
||||
|
||||
bus-width = <4>;
|
||||
max-frequency = <60000000>;
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <100000000>;
|
||||
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
@ -373,7 +374,7 @@
|
|||
pinctrl-0 = <&nor_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
w25q32: spi-flash@0 {
|
||||
w25q32: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "winbond,w25q16", "jedec,spi-nor";
|
||||
|
|
|
@ -45,8 +45,6 @@
|
|||
|
||||
gpio-keys-polled {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
poll-interval = <100>;
|
||||
|
||||
button-power {
|
||||
|
|
|
@ -46,7 +46,7 @@ CONFIG_PHY_REALTEK=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -54,7 +54,7 @@ CONFIG_PHY_MESON_GXL=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -51,7 +51,7 @@ CONFIG_PHY_REALTEK=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -45,7 +45,7 @@ CONFIG_PHY_MESON_GXL=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -57,7 +57,7 @@ CONFIG_PHY_MESON_GXL=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -44,7 +44,7 @@ CONFIG_PHY_MESON_GXL=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -52,7 +52,7 @@ CONFIG_PHY_MESON_GXL=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
|
|
|
@ -53,7 +53,7 @@ CONFIG_PHY_REALTEK=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -52,7 +52,7 @@ CONFIG_PHY_REALTEK=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -40,7 +40,7 @@ CONFIG_PHY_MESON_GXL=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -46,7 +46,7 @@ CONFIG_PHY_REALTEK=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_DM_MDIO_MUX=y
|
||||
CONFIG_ETH_DESIGNWARE_MESON8B=y
|
||||
CONFIG_MDIO_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_MUX_MESON_GXL=y
|
||||
CONFIG_MESON_GXL_USB_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_GXL=y
|
||||
|
|
|
@ -980,4 +980,11 @@ config MDIO_MUX_MESON_G12A
|
|||
This driver is used for the MDIO mux found on the Amlogic G12A & compatible
|
||||
SoCs.
|
||||
|
||||
config MDIO_MUX_MESON_GXL
|
||||
bool "MDIO MUX for Amlogic Meson GXL SoCs"
|
||||
depends on DM_MDIO_MUX
|
||||
help
|
||||
This driver is used for the MDIO mux found on the Amlogic GXL & compatible
|
||||
SoCs.
|
||||
|
||||
endif # NETDEVICES
|
||||
|
|
|
@ -57,6 +57,7 @@ obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
|
|||
obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
|
||||
obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
|
||||
obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o
|
||||
obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o
|
||||
obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o
|
||||
obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
|
||||
obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
|
||||
|
|
138
drivers/net/mdio_mux_meson_gxl.c
Normal file
138
drivers/net/mdio_mux_meson_gxl.c
Normal file
|
@ -0,0 +1,138 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2022 Baylibre, SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
* Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <log.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#define ETH_REG2 0x0
|
||||
#define REG2_PHYID GENMASK(21, 0)
|
||||
#define EPHY_GXL_ID 0x110181
|
||||
#define REG2_LEDACT GENMASK(23, 22)
|
||||
#define REG2_LEDLINK GENMASK(25, 24)
|
||||
#define REG2_DIV4SEL BIT(27)
|
||||
#define REG2_ADCBYPASS BIT(30)
|
||||
#define REG2_CLKINSEL BIT(31)
|
||||
#define ETH_REG3 0x4
|
||||
#define REG3_ENH BIT(3)
|
||||
#define REG3_CFGMODE GENMASK(6, 4)
|
||||
#define REG3_AUTOMDIX BIT(7)
|
||||
#define REG3_PHYADDR GENMASK(12, 8)
|
||||
#define REG3_PWRUPRST BIT(21)
|
||||
#define REG3_PWRDOWN BIT(22)
|
||||
#define REG3_LEDPOL BIT(23)
|
||||
#define REG3_PHYMDI BIT(26)
|
||||
#define REG3_CLKINEN BIT(29)
|
||||
#define REG3_PHYIP BIT(30)
|
||||
#define REG3_PHYEN BIT(31)
|
||||
#define ETH_REG4 0x8
|
||||
#define REG4_PWRUPRSTSIG BIT(0)
|
||||
|
||||
#define MESON_GXL_MDIO_EXTERNAL_ID 0
|
||||
#define MESON_GXL_MDIO_INTERNAL_ID 1
|
||||
|
||||
struct mdio_mux_meson_gxl_priv {
|
||||
phys_addr_t regs;
|
||||
};
|
||||
|
||||
static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Setup the internal phy */
|
||||
val = (REG3_ENH |
|
||||
FIELD_PREP(REG3_CFGMODE, 0x7) |
|
||||
REG3_AUTOMDIX |
|
||||
FIELD_PREP(REG3_PHYADDR, 8) |
|
||||
REG3_LEDPOL |
|
||||
REG3_PHYMDI |
|
||||
REG3_CLKINEN |
|
||||
REG3_PHYIP);
|
||||
|
||||
writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4);
|
||||
writel(val, priv->regs + ETH_REG3);
|
||||
mdelay(10);
|
||||
|
||||
/* NOTE: The HW kept the phy id configurable at runtime.
|
||||
* The id below is arbitrary. It is the one used in the vendor code.
|
||||
* The only constraint is that it must match the one in
|
||||
* drivers/net/phy/meson-gxl.c to properly match the PHY.
|
||||
*/
|
||||
writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
|
||||
priv->regs + ETH_REG2);
|
||||
|
||||
/* Enable the internal phy */
|
||||
val |= REG3_PHYEN;
|
||||
writel(val, priv->regs + ETH_REG3);
|
||||
writel(0, priv->regs + ETH_REG4);
|
||||
|
||||
/* The phy needs a bit of time to power up */
|
||||
mdelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_gxl_enable_external_mdio(struct mdio_mux_meson_gxl_priv *priv)
|
||||
{
|
||||
/* Reset the mdio bus mux to the external phy */
|
||||
writel(0, priv->regs + ETH_REG3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mdio_mux_meson_gxl_select(struct udevice *mux, int cur, int sel)
|
||||
{
|
||||
struct mdio_mux_meson_gxl_priv *priv = dev_get_priv(mux);
|
||||
|
||||
debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
|
||||
|
||||
/* if last selection didn't change we're good to go */
|
||||
if (cur == sel)
|
||||
return 0;
|
||||
|
||||
switch (sel) {
|
||||
case MESON_GXL_MDIO_EXTERNAL_ID:
|
||||
return meson_gxl_enable_external_mdio(priv);
|
||||
case MESON_GXL_MDIO_INTERNAL_ID:
|
||||
return meson_gxl_enable_internal_mdio(priv);
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mdio_mux_ops mdio_mux_meson_gxl_ops = {
|
||||
.select = mdio_mux_meson_gxl_select,
|
||||
};
|
||||
|
||||
static int mdio_mux_meson_gxl_probe(struct udevice *dev)
|
||||
{
|
||||
struct mdio_mux_meson_gxl_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->regs = dev_read_addr(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id mdio_mux_meson_gxl_ids[] = {
|
||||
{ .compatible = "amlogic,gxl-mdio-mux" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mdio_mux_meson_gxl) = {
|
||||
.name = "mdio_mux_meson_gxl",
|
||||
.id = UCLASS_MDIO_MUX,
|
||||
.of_match = mdio_mux_meson_gxl_ids,
|
||||
.probe = mdio_mux_meson_gxl_probe,
|
||||
.ops = &mdio_mux_meson_gxl_ops,
|
||||
.priv_auto = sizeof(struct mdio_mux_meson_gxl_priv),
|
||||
};
|
Loading…
Reference in a new issue