Commit graph

1416 commits

Author SHA1 Message Date
Heiko Schocher
0660481a59 ARM: AM33xx: Move s_init to a common place
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2013-08-15 08:51:10 -04:00
Lokesh Vutla
95cb69faeb ARM: AM33xx: Cleanup clocks layer
Cleaning up the clocks layer.
This helps in addition of new Soc with minimal
changes.
This is derived from OMAP4 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2013-08-15 08:51:10 -04:00
Lokesh Vutla
94d77fb656 ARM: AM33xx: Cleanup dplls data
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.

This is derived from OMAP4 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2013-08-15 08:51:10 -04:00
Michal Simek
39523bef29 zynq: slcr: Wait 100ms till clk is properly setup
If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-08-12 08:59:55 +02:00
Michal Simek
148ba55cc6 zynq: Add new ddrc driver for ECC support
The first 1MB is not initialized by first stage bootloader.
Check if memory is setup to 16bit mode and ECC is enabled.
If it is, clear the first 1MB.
Also u-boot should report only the half size of memory.

Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-12 08:59:55 +02:00
Stephen Warren
065202803d config: don't define CONFIG_ARCH_DEVICE_TREE
Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-08-02 18:30:11 -04:00
Stefano Babic
326ea986ac Merge git://git.denx.de/u-boot-arm
Conflicts:
	board/freescale/mx6qsabrelite/Makefile
	board/freescale/mx6qsabrelite/mx6qsabrelite.c
	include/configs/mx6qsabrelite.h

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-07-31 11:30:38 +02:00
Steve Kipisz
c5c7a7c32d am335x_evm: Add support to boot from NOR.
NOR requires that s_init be within the first 4KiB of the image so that
we can perform the rest of the required pinmuxing to talk with the rest
of NOR that we are found on.  When NOR_BOOT is set we save our
environment in NOR at 512KiB and a redundant copy at 768KiB.  We avoid
using SPL for this case and u-boot.bin is written directly to the start
of NOR.

We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c
with TI81xx checks as at this time U-Boot does not discard unused
sections in the main build and this code relies on functions specific to
(and only provided in) ti81xx-related code.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:41 -04:00
Steve Kipisz
cd8845d7a4 am335x_evm: Add support for the NOR module on the memory cape
This patch adds support for the NOR module that attaches
to the memory cape for a Beaglebone board. This does not
add booting support; only support so that you can boot from
SD/MMC and see the NOR module so that it can be programmed.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Clean up config changes slightly]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:41 -04:00
Tom Rini
392bba4ad0 am33xx: Correct gpmc_cfg->irqstatus/enable
Based on our usage of the GPMC, either with NOR or NAND we do not need
to be setting the irqstatus or irqenable bits and should clear them like
we have historically.

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-30 09:21:41 -04:00
Pardeep Kumar Singla
5ea7f0e328 mx6: Factor out common HDMI setup code
Instead of duplicating HDMI setup code for every mx6 board, factor out the common code

Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
2013-07-27 10:49:36 +02:00
Mugunthan V N
b1e26e3bfb ARM: DRA7xx: Add CPSW support to DRA7xx EVM
Adding support for CPSW Ethernet support found in DRA7xx EVM

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-26 16:39:11 -04:00
Mugunthan V N
f986d97208 ARM: DRA7xx: Enable GMAC clock control
Enabling CPSW module by enabling GMAC clock control

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-26 16:39:11 -04:00
Lokesh Vutla
65e9d56fb9 ARM: DRA7xx: Lock DPLL_GMAC
Locking DPLL_GMAC

[mugunthanvnm@ti.com:Configure only if CPSW is selected]

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-26 16:39:11 -04:00
Andreas Bießmann
c4ec281822 omap3/sys_info: fix printout of OMAP36XX L3 freqency
The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz
used by OMAP34xx/OMAP35xx.

Also fix checkpatch warning about alignment.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-07-26 16:39:10 -04:00
Stefan Roese
bf0e86606d arm: omap3: spl: Fix problem with 8bit NAND devices
Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit
access. This patch adds support for 8bit NAND devices as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-07-26 16:39:10 -04:00
Albert ARIBAUD
8b485ba12b Merge branch 'u-boot/master' into u-boot-arm/master 2013-07-25 17:57:46 +02:00
Rob Herring
0f7cf3803f ARM: highbank: avoid bss write in timer_init
The timer_init function is called before relocation and writes to bss data
were corrupting relocation data. Fix this by removing the call to
reset_timer_masked. The initial timer count should be 0 or near 0 anyway,
so initializing the variables are not needed.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25 08:15:44 +02:00
Rob Herring
714d1f5da5 ARM: highbank: set timer prescaler to 256
The 150MHz clock rate gives u-boot time functions problems and there's no
benefit to a fast clock, so lower the rate.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25 08:15:33 +02:00
Rob Herring
ec0e413f93 ARM: highbank: fix get_tbclk value to timer rate
get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-07-25 08:15:25 +02:00
Tom Rini
c2120fbfbc Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.

Conflicts:
	board/sandburst/common/ppc440gx_i2c.c
	board/sandburst/common/ppc440gx_i2c.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:24 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Alison Wang
1221b3d74a vf610: Add I2C support for Vybrid VF610 platform
This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.

Signed-off-by: Alison Wang <b18965@freescale.com>
2013-07-23 08:34:57 +02:00
Łukasz Majewski
f4eaf88e6d arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.
Provide proper setting for the APLL fout frequency calculation for
Exynos4 based targets (especially Exynos4210 - Trats board).

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2013-07-16 09:20:16 -04:00
Tom Rini
fbbbc86e8e Merge branch 'master' of git://git.denx.de/u-boot-arm
Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.

Conflicts:
	arch/arm/dts/exynos5250.dtsi

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-12 10:36:48 -04:00
Albert ARIBAUD
630aacb085 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-07-10 20:40:47 +02:00
Minkyu Kang
e161f60f4d arm: exynos: fix clock calculation
There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2013-07-09 16:15:30 +09:00
Rajeshwari Shinde
643be9c07e EXYNOS: Move files from board/samsung to arch/arm
This patch performs the following:

1) Convert the assembly code for memory and clock initialization to C code.
2) Move the memory and clock init codes from board/samsung to arch/arm
3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted
   the common lowlevel_init from assembly to C-code
4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already
   done in _main.
6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.

TEST: Tested SD-MMC boot on SMDK5250 and Origen.
      Tested USB and SPI boot on SMDK5250
      Compile tested for SMDKV310.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-07-05 17:06:55 +09:00
Rajeshwari Shinde
198a40b9f6 EXYNOS4210: Configure GPIO for uart
This patch configures the gpio values for UART
on Origen and SMDKV310 using pinmux

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-07-05 17:06:55 +09:00
Rajeshwari Shinde
dc20fdd76a EXYNOS: Add API for power reset and exit wakeup
This patch adds APIs to get power reset status and exit the wakeup condition for
both exynos5 and exynos4

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-07-05 17:06:54 +09:00
Axel Lin
87bd05d78f ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5
The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.

This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h.
2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5.

Thanks for Lubomir Popov to provide valuable comments to fix this issue.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Heiko Schocher <hs@denx.de>
2013-07-02 09:21:16 -04:00
Lokesh Vutla
e3f53104e2 ARM: OMAP4+: Fix MA detection during SDRAM_AUTO_DETECTION
During SDRAM_AUTO_DETECTION MA is not configured.
For Soc's > OMAP4460 MA is present. So populating
MA for the same.

Tested on OMAP4430 PANDA, OMAP4460 PANDA.

Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-07-02 09:21:16 -04:00
Albert ARIBAUD
e6c7f86f03 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-06-28 17:51:13 +02:00
trem
79713f0ad8 mx27: add i2c clock
Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-06-26 17:34:21 +02:00
trem
6247c4653b mx27: add function enable_caches
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-06-26 17:34:21 +02:00
Simon Glass
ca35a0cdf2 exynos: Avoid function instrumentation for microsecond timer
For tracing to work it has to be able to access the microsecond timer
without causing a recursive call to the function entry/exit handlers.
Add attributes to the relevant functions to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:18:56 -04:00
Mike Dunn
84c617beb2 pxa: use -mcpu=xscale compiler option
Pass '-mcpu=xscale' to the compiler instead of march and mtune.  This will cause
gcc to define the __XSCALE__ macro.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Mike Dunn
097d86d098 pxa: turn icache off in cpu_init_crit()
The comment in the low-level initialization function cpu_init_crit() says that
the caches are being disabled, but (oddly) the icache is actually turned on.
This is probably not a good idea prior to relocating code, so this patch turns
it off.  Tested on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
2013-06-22 15:25:28 +02:00
Albert ARIBAUD
47bd65ef05 arm: make __rel_dyn_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain relocation symbols yet remain
unchanged.

__rel_dyn_start and __rel_dyn_end each requires
its own output section; putting them in relocation
sections changes their flags and breaks relocation.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:29 +02:00
Albert ARIBAUD
d026dec875 arm: make __image_copy_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain __image_copy_{start,end} yet
remain unchanged.

Also, __image_copy_end needs its own section; putting
it in relocation sections changes their flags and makes
relocation break.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:05 +02:00
Albert ARIBAUD
09d81184e1 remove all references to .dynsym
Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase

Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:04:05 +02:00
Albert ARIBAUD
c2543a21df Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-06-19 23:58:01 +02:00
Albert ARIBAUD
69f14dc2fd Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Conflicts:
	spl/Makefile
2013-06-19 12:53:59 +02:00
Heiko Schocher
7ea7f689ca arm, am33xx: move uart soft reset code to common place
move uart soft reset code to common place and call
this function from board code, instead of copy and paste
this code for every board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
[trini: Fix igep0033 build, remove 'regval' on pcm051]
Signed-off-by: Tom Rini <trini@ti.com>
2013-06-18 10:40:06 -04:00
Heiko Schocher
7b9c5d0bfd arm, am335x: make mpu pll config configurable
upcoming support for siemens boards switches mpu pll clk in board
code. So make this configurable.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-06-18 09:18:46 -04:00
Heiko Schocher
49f7836500 arm, am33xx: move rtc32k_enable() to common place
move rtc32k_enable() to common place so all am33xx boards can use it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
2013-06-18 09:12:38 -04:00
Amar
2b81c26b7c EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.
This patch initialises the local variable 'shift' to zero.
The uninitialised local variable 'shift' had garbage value and was
resulting in unwnated results in the functions exynos5_get_mmc_clk()
and exynos4_get_mmc_clk().

Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:35:14 +09:00
Sergey Yanovich
847e6693cc arm: pxa: config option for PXA270 turbo mode
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
default run mode. Activating the mode early significantly speeds
up boot process.

Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
2013-06-12 22:24:12 +02:00
Vishwanathrao Badarkhe, Manish
68cd4a4c9f arm: da830: moved pinmux configurations to the arch tree
Move pinmux configurations for the DA830 SoCs from board file
to the arch tree so that it can be used for all da830 based devices.
Also, avoids duplicate pinmuxing in case of NAND.

Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
2013-06-10 08:54:46 -04:00
Lubomir Popov
ee28edac43 OMAP5: Enable access to auxclk registers
auxclk0 and auxclk1 are utilized on some OMAP5 boards.
Define the infrastructure needed for accessing them
without using magic numbers.

Also remove unrelated TPS62361 defines from clocks.h

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-06-10 08:54:46 -04:00
Tom Rini
7f5eef93af arm: Remove OMAP2420H4 and all omap24xx support
The omap2420H4 was the only mainline omap24xx board.  Prior to being
fixed by Jon Hunter in time for v2013.04 it had been functionally broken
for a very long time.  Remove this board as there's not been interest in
it in U-Boot for quite a long time.

Signed-off-by: Tom Rini <trini@ti.com>
2013-06-10 08:43:19 -04:00
Sricharan R
92b0482c17 ARM: DRA7xx: EMIF: Change settings required for EVM board
DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
97405d843e ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-06-10 08:43:10 -04:00
Sricharan R
f9b814a8e9 ARM: DRA7xx: Correct the SYS_CLK to 20MHZ
The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
e9d6cd042d ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Nishanth Menon
18c9d55ac6 ARM: OMAP5: DRA7xx: support class 0 optimized voltages
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
3332b24421 ARM: DRA7xx: clocks: Fixing i2c_init for PMIC
In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
63fc0c775c ARM: DRA7xx: power Add support for tps659038 PMIC
TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
4ca94d8186 ARM: OMAP4+: pmic: Make generic bus init and write functions
Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
af1d002f89 ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h
To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Sricharan R
bcdd8f72f3 ARM: OMAP5: clocks: Do not enable sgx clocks
SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
9239f5b625 ARM: OMAP4+: Cleanup header files
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lubomir Popov
e0a8c99e61 OMAP5: Fix bug in omap5_es1_prcm struct
The newly introduced function setup_warmreset_time(), called
from within prcm_init(), tries to write to the prm_rsttime
OMAP5 register. The struct member holding this register's
address is however initialized for OMAP5 ES2.0 only. On ES1.0
devices this uninitialized value causes a second (warm) reset
at startup.

Add .prm_rsttime address init to the ES1.0 struct.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Tom Rini <trini@ti.com>
2013-06-10 08:43:09 -04:00
Andrii Tseglytskyi
e69c585d76 OMAP5: add ABB setup for MPU voltage domain
Patch adds a call of abb_setup() function, and proper registers
definitions needed for ABB setup sequence. ABB is initialized
for MPU voltage domain.

Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
2013-06-10 08:43:09 -04:00
Andrii Tseglytskyi
4d0df9c1e9 OMAP3+: introduce generic ABB support
Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains
starting with OMAP3630. There are three modes of operation:

* Bypass - the default, it just follows the vdd voltage
* Foward Body-Bias - applies voltage bias to increase transistor
  performance at the cost of power.  Used to operate safely at high
  OPPs.
* Reverse Body-Bias - applies voltage bias to decrease leakage and
  save power.  Used to save power at lower OPPs.

Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
2013-06-10 08:43:09 -04:00
Albert ARIBAUD
10e167329b Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/serial/Makefile
2013-06-08 14:35:10 +02:00
Tom Warren
dbc000bfb5 ARM: tegra: only enable SCU on Tegra20
The non-SPL build of U-Boot on Tegra only runs on a single CPU, and
hence there is no need to enable the SCU when running U-Boot. If an
SMP OS is booted, and it needs the SCU enabled, it will enable the SCU
itself. U-Boot doing so is redundant.

The one exception is Tegra20, where an enabled SCU is required for some
aspects of PCIe to work correctly.

Some Tegra SoCs contain CPUs without a software-controlled SCU. In this
case, attempting to turn it on actively causes problems. This is the case
for Tegra114. For example, when running Linux, the first (or at least
some very early) user-space process will trigger the following kernel
message:

Unhandled fault: imprecise external abort (0x406) at 0x00000000

This is typically accompanied by that process receving a fatal signal,
and exiting. Since this process is usually pid 1, this causes total
system boot failure.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, fleshed out description, ported to upstream chipid APIs]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-06-06 09:12:32 -07:00
Tom Rini
4596dcc1d4 am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c
We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common.  Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx.  Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.

Reviewed-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-06-05 08:46:49 -04:00
Tom Rini
0ac6db2631 omap-common/hwinit-common.c: Mark omap_rev_string as static
Only called in this file, mark as static.

Signed-off-by: Tom Rini <trini@ti.com>
2013-06-04 16:32:31 -04:00
Inderpal Singh
b5f9756f7f exynos: update tzpc to make it common for exynos4 and exynos5
This requires that cpu_is_exynos4/5 should be made available before tzpc_init.
Hence this patch also makes necessary changes to have cpu_info in spl and
invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-04 15:23:17 +09:00
Inderpal Singh
72af2fc850 exynos: move tzpc_init to armv7/exynos
tzpc_init is common for all exynos5 boards, hence move it to
armv7/exynos so that all other boards can use it.

Also update the smdk5250 Makefile and config file.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-04 15:22:10 +09:00
Marek Vasut
86fb7b3d5b arm: mxs: Fix vectoring table crafting
The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28
starts from RAM, so the vectoring table at 0x0 is not present. Craft
code that will be placed at 0x0 and will redirect interrupt vectoring
to proper location of the U-Boot in RAM.

Signed-off-by: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-06-03 12:49:50 +02:00
Alison Wang
24e8bee508 arm: vf610: Add Vybrid VF610 CPU support
This patch adds generic codes to support Freescale's Vybrid VF610 CPU.

It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.

Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-03 10:56:53 +02:00
Albert ARIBAUD
3da0e5750b arm: factorize relocate_code routine
Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
2013-05-30 20:24:38 +02:00
Albert ARIBAUD
fa6c7413d1 arm: do not compile relocate_code() for SPL builds
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
2013-05-30 20:24:07 +02:00
Axel Lin
60985bba58 tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL build
Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:44 -07:00
Axel Lin
578e63782b ARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_crit
cpu_init_crit() can be skipped, but the code is still enabled requiring a
platform to supply lowlevel_init().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:43 -07:00
Stephen Warren
20583d04fb ARM: tegra: support SKU 7 of Tegra20
Make U-Boot aware of the Tegra20 SKU 7, and treat it identically
to any other Tegra20.

My Whistler board has a SoC with this SKU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:43 -07:00
Stephen Warren
840167c2c2 ARM: tegra: support SKU 1 of Tegra114
Make U-Boot aware of the Tegra114 SKU 1, and treat it identically
to any other Tegra114.

This value is used on (at least some) Dalmore boards with a production
rather than engineering chip. Such boards are in the hands of some
partners who want to use upstream U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:43 -07:00
Allen Martin
a51f7de161 Tegra: clk: always use find_best_divider() for periph clocks
When adjusting peripheral clocks always use find_best_divider()
instead of clk_get_divider() even when a secondary divider is not
available.  In the case where is requested clock is too slow to be
derived from the parent clock this allows a best effort to get close
to the requested clock.

This comes up for commands like "sf" where the user can pass a clock
speed on the command line or "sspi" where the clock is hardcoded to
1MHz, but the Tegra114 SPI controller can't go that low.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-05-28 12:58:42 -07:00
Tom Rini
fd72569179 arm: Enable -ffunction-sections / -fdata-sections / --gc-sections
While other architectures have enabled these gcc / ld options for some
time on U-Boot itself, ARM has only been doing this on SPL.  Enable this
on full U-Boot as well now.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-23 12:09:56 +02:00
Akshay Saraswat
234370cab4 Exynos5: clock: Update the equation to calculate PLL output frequency
According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-05-21 20:17:30 +09:00
Bo Shen
3225f34e5c ARM: atmel: add sama5d3xek support
Add sama5d3xek support with following feature
  - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector
  - boot from SPI flash support
  - boot from SD card support
  - LCD support
  - EMAC support
  - USB OHCI support

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-21 11:54:16 +02:00
Wu, Josh
a73267a7ce arm: at91: enable mci support for at91sam9g20ek.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-12 16:42:24 +02:00
Wu, Josh
9e33690389 arm: at91: add at91sam9n12ek board support
Add support for following features:
  - nand boot, with PMECC 2bit ECC for 512 bytes sector
  - SPI flash boot
  - SD card boot
  - LCD support

Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix -Wimplicit-function-declaration for at91_lcd_hw_init()]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-12 16:40:42 +02:00
Albert ARIBAUD
cac423a730 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-05-11 22:24:28 +02:00
Albert ARIBAUD
ec7023db8d Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/mtd/nand/mxc_nand_spl.c
	include/configs/m28evk.h
2013-05-11 09:25:36 +02:00
Albert ARIBAUD
e825b100d2 Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2013-05-11 00:06:03 +02:00
SRICHARAN R
47c6ea076e ARM: OMAP: Add arch_cpu_init function
The boot parameters passed from SPL to UBOOT
must be saved as a part of uboot's gd data
as early as possible, before we will inadvertently
overwrite it. So adding a arch_cpu_init for the required
Socs to save it.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:56 -04:00
SRICHARAN R
4a0eb75752 ARM: OMAP: Cleanup boot parameters usage
The boot parameters are read from individual variables
assigned for each of them. This been corrected and now
they are stored as a part of the global data 'gd'
structure. So read them from 'gd' instead.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:56 -04:00
SRICHARAN R
fda06812a0 ARM: OMAP: Correct save_boot_params and replace with 'C' function
Currently save_boot_params saves the boot parameters passed
from romcode. But this is not stored in a writable location
consistently. So the current code would not work for a
'XIP' boot. Change this by saving the boot parameters in
'gd' which is always writable. Also add a 'C' function
instead of an assembly code that is more readable.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-05-10 08:25:56 -04:00
SRICHARAN R
f92f2277a6 ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
These defines are same across OMAP4/5. So move them to
omap_common.h. This is required for the patches that
follow.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-05-10 08:25:56 -04:00
Tom Rini
30bba01751 am33xx: Fix warning with CONFIG_DISPLAY_CPUINFO
The arm_freq and ddr_freq variables are unused, so remove.  Fixup
whitespace slightly while in here.

Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:56 -04:00
Eric Benard
81ac7e51cc da850: provide davinci_enable_uart0
this is needed to bring UART0 out of reset but this function
currently only exists for dm644x/355/365/646x when da850 (at
least am1808 also need it).

Signed-off-by: Eric Bénard <eric@eukrea.com>
2013-05-10 08:25:56 -04:00
Lokesh Vutla
0b1b60c779 ARM: OMAP5: Fix warm reset with USB cable connected
Warm reset on OMAP5 freezes when USB cable is connected.
Fix requires PRM_RSTTIME.RSTTIME1 to be programmed
with the time for which reset should be held low for the
voltages and the oscillator to reach stable state.

There are 3 parameters to be considered for calculating
the time, which are mostly board and PMIC dependent.
-1- Time taken by the Oscillator to shut + restart
-2- PMIC OTP times
-3- Voltage rail ramp times, which inturn depends on the
PMIC slew rate and value of the voltage ramp needed.

In order to keep the code in u-boot simple, have a way
for boards to specify a pre computed time directly using
the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'
option. If boards fail to specify the time, use a default
as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead.
Using the default value translates into some ~22ms and should work in
all cases.
However in order to avoid this large delay hiding other bugs,
its recommended that all boards look at their respective data
sheets and specify a pre computed and optimal value using
'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'

In order to help future board additions to compute this
config option value, add a README at doc/README.omap-reset-time
which explains how to compute the value. Also update the toplevel
README with the additional option and pointers to
doc/README.omap-reset-time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[rnayak@ti.com: Updated changelog and added the README]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-05-10 08:25:55 -04:00
Lubomir Popov
2bcc785a1e OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work
USB TLL clocks do not support 'explicit_en', only 'hw_auto'
control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be
moved to the clk_modules_hw_auto_essential[] array in order
to make the clock work.

This fix is needed (but not sufficient) for USB EHCI operation
in U-Boot.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-05-10 08:25:55 -04:00
Lokesh Vutla
166e5cc627 arm: omap: emif: Fix DDR3 init after warm reset
EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.

Tested on OMAP5432 ES2.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-05-10 08:25:55 -04:00
Lubomir Popov
3935277dbf OMAP5: I2C: Enable i2c5 clocks
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The i2c5 clock was however not enabled; do this here.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-05-10 08:25:55 -04:00
Matt Porter
035d563937 am33xx: add pll and clock support for TI814x CPSW
Enables required PLLs and clocks for CPSW on TI814x.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-10 08:25:54 -04:00
Marek Vasut
7411cdf0e2 arm: mxs: Add LCDIF clock configuration function
This function turns on the LCDIF clock and configures it's frequency. The
dividers settings are calculated within the function and the current
implementation should be fast and accurate.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-05-06 17:40:22 +02:00
Michal Simek
d5dae85f23 fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.

The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:24 +02:00
Marek Vasut
714dc001fc arm: mxs: Preprocess u-boot.bd so they contain full path
The u-boot-imx23.bd and u-boot-imx28.bd need to be preprocessed, otherwise
they have issues with out-of-tree build where elftosb tool couldn't sometimes
find the u-boot.bin and spl/u-boot-spl.bin .

Preprocess these .bd files with sed and insert full path to u-boot.bin and
spl/u-boot-spl.bin to prevent this issue. Moreover, to avoid adding more
churn into main Makefile, move all this preprocessing and u-boot.sb generation
into CPU directory instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-05-06 10:37:36 +02:00
Marek Vasut
dd3ecf020e arm: mx23: Fix VDDMEM misconfiguration
The VDDMEM ramped up in very weird way as it was horribly misconfigured.
Instead of setting up VDDMEM in one swipe, let it rise slowly the same
way as VDDD and VDDA in spl_power_init.c and then only clear ILIMIT before
memory gets inited. This makes sure the VDDMEM rises sanely, not jumps up
and down as it did till now.

The VDDMEM prior to this change did this:
     2V0____   .--------2V5
       |    `--'
 0V____|

The VDDMEM now does this:
    2V0_____,-----------2V5
      /
 0V__|

Moreover, VDDIO on MX23 uses 25mV steps while MX28 uses 50mV steps,
fix this difference too.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
2013-05-06 10:20:33 +02:00
Fabio Estevam
286a88cf34 mxs: Explain why some mx23 DDR registers are not configured
Put an explanation in the source code as to why some DDR registers do not
need to be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-06 09:55:52 +02:00
Fabio Estevam
26be20fac0 mx23: Operate DDR voltage supply at 2.5V
After the recent fixes in the mx23 DDR setup, it is safe to operate DDR voltage
at the recommended 2.5V voltage level again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-06 09:55:51 +02:00
Łukasz Dałek
2ac2bb7ad2 pxa: Add weak attribute to reset_cpu() function
This commit allows pxa2xx based boards to reimplement reset_cpu()
function with board specific reset sequence.

Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
2013-05-05 23:47:05 +02:00
Benoît Thébaudeau
ba5dfc11ba imx: mx5: Remove legacy iomux support
Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2013-05-05 17:55:05 +02:00
Benoît Thébaudeau
e2003c16c0 imx: mx35: Remove legacy iomux support
Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:04 +02:00
Benoît Thébaudeau
9e933b43f3 imx: mx25: Remove legacy iomux support
Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:03 +02:00
Marek Vasut
f399f63647 arm: mx5: Add NAND clock handling
Augment the MX5 clock code with function to enable and configure
NFC clock. This is necessary to get NFC working on MX5.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-05-05 17:45:05 +02:00
Fabio Estevam
fb7383a7a2 mxs: spl_mem_init: Change EMI port priority
FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL
as 0x2, which means:

PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:47 +02:00
Fabio Estevam
39a538d992 mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registers
HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per
FSL bootlets code.

mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved".

HW_DRAM_CTL8 is setup as the last element.

So skip the initialization of these DRAM_CTL registers.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:46 +02:00
Fabio Estevam
b0d4bf9f0c mxs: spl_mem_init: Remove erroneous DDR setting
On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18.

Remove this erroneous setting.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:46 +02:00
Fabio Estevam
8a47c997c5 mxs: spl_mem_init: Fix comment about start bit
Start bit is part of HW_DRAM_CTL8 register, so  fix the comment.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:46 +02:00
Andreas Bießmann
d2eae43ba8 lib: consolidate hang()
Delete all occurrences of hang() and provide a generic function.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01 16:41:08 -04:00
Michal Simek
80243528ef net: gem: Fix gem driver on 1Gbps LAN
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:19 +02:00
Michal Simek
4b21284b8c zynq: Move scutimer baseaddr to hardware.h
Move baseaddr to hardware.h to be shared between
configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:12 +02:00
David Andrey
d54cc00787 arm: zynq: U-Boot udelay < 1000 FIX
Rework the __udelay function of U-Boot Zynq Arch to handle
delay < 1000 usec

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-04-30 11:39:10 +02:00
Benoît Thébaudeau
112fd2ec6c Add mxc_ocotp driver
Add an mxc_ocotp driver for i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:07:43 +02:00
Benoît Thébaudeau
8f3ff11c1f imx: Homogenize and fix fuse register definitions
IIM:
 - Homogenize prg_p naming (the reference manuals are not always self-consistent
   for that).
 - Add missing SCSx and bank registers.
 - Fix the number of banks on i.MX53.

OCOTP:
 - Rename iim to ocotp in order to avoid confusion.
 - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
   reference manual.
 - Merge the existing spinoff gp1 fuse definition on i.MX6.
 - Fix the number of banks on i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-28 11:07:40 +02:00
Fabio Estevam
cdc203682f mx23: Put back RAM voltage level to its original value
commit 5c2f444c9 (mxs: Reset the EMI block on mx23) changed the DDR voltage
level, which causes mx23evk to fail to load a kernel.

Put back the original values, so that mx23evk can boot a kernel again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
2013-04-28 11:06:27 +02:00
Fabio Estevam
11c08d4ec5 mx5: Define a common get_board_rev()
When booting a FSL kernel based on 2.6.35 it is necessary to pass the revision
tag to the kernel.

Place a common weak function into soc.c for such purpose.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-04-25 21:48:21 +02:00
Stefan Roese
ae695b18df mtd: mxs_nand: Add support for i.MX6
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:36 +02:00
Stefan Roese
8870e45996 imx: Move some i.MX common functions into the imx-common directory
This patch moves the following functions into the imx-common
directory:

- mxs_wait_mask_set()
- mxs_wait_mask_clr()
- mxs_reset_block()

These are currently used by i.MX28. But the upcoming GPMI NAND port
for i.MX6 will also use these functions. So lets move them to a
common location to re-use them.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:23:42 +02:00
Stefan Roese
0499218dbc imx: Move some header files from arch-mxs to imx-common
The following headers are moved to a i.MX common location:

- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.h

This way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:22:22 +02:00
Fabio Estevam
25b4aa146a mx6: Add solo-lite variant support
mx6 solo-lite is another member of the mx6 series.

For more information about mx6 solo-lite, please visit:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 09:57:44 +02:00
Stefano Babic
cd53034613 Merge branch 'next' 2013-04-21 11:32:19 +02:00
Simon Glass
dc47e2bc7d exynos: Correct use of 64-bit division
The current code is causing errors like this on my toolchains:

/usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/
ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/
armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o)

Use do_div() to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-17 10:00:40 +09:00
Philip Paeps
04f79536c3 mx35 iomux: correct offsets of IOMUX registers
This makes mxc_iomux_set_input() work correctly.  Previously, the
incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input()
to write to the wrong register, possibly resulting in unexpected
behaviour.

Signed-off-by: Philip Paeps <philip@paeps.cx>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-16 18:58:47 +02:00
Tom Warren
49493cb714 Tegra: Split tegra_get_chip_type() into soc & sku funcs
As suggested by Stephen Warren, use tegra_get_chip() to return
the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for
Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true
function, i.e. tegra_get_chip_sku(), which returns an ID like
TEGRA_SOC_T25, TEGRA_SOC_T33, etc.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
d94c2dbd0a Tegra: Fix MSELECT clock divisors for T30/T114.
A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
b40f734af9 Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
d0edce4fa3 Tegra: Configure L2 cache control reg properly.
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-04-15 11:01:38 -07:00
Tom Warren
3ebbbfe4c7 Tegra: Restore cp15 VBAR _start vector write for ARMv7
A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53),
and caused the old monilithic Tegra builds to hang due to an undefined
instruction trap. Previously, the code needed to run on both the
AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register.
I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but
now that we use SPL, and boot the AVP w/o any ARMv7 code, I can
revert my change, and make Aneesh's change apply to Tegra.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-04-15 11:01:37 -07:00
Stephen Warren
eb222d1d7d ARM: tegra: support T33 SKU of Tegra30
Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically
to any other Tegra30.

An alternative would be to simply remove the SKU checking from
tegra_get_chip_type(); most use of the value most likely simply wants
to know the current chip, not the specific SKU. Or, the function could
be split into separate tegra_get_chip() and tegra_get_sku() for the
cases where differentiation really is required.

I wonder whether tegra_get_chip_type() should printf() whenever any
unkown chip/SKU is found, although perhaps the function is called so
early that the printf() wouldn't actually make it to the UART anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-04-15 11:01:37 -07:00
Andre Przywara
c4a4e2e20c ARMv7: start.S: stay in HYP mode if u-boot is entered in it
The KVM and Xen hypervisors for the Cortex-A15 virtualization
implementation need to be entered in HYP mode. Should the primary
board firmware already enter HYP mode (Calxeda firmware does that),
we should not deliberately drop back to SVC mode.
Since U-boot does not use the MMU, running in HYP mode is just fine.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-04-15 18:30:59 +02:00
Albert ARIBAUD
6ebc346111 ARM: fix CONFIG_SPL_MAX_SIZE semantics
Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds
as this file is never used for SPL builds.

Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds
to separately test image (text,data,rodata...) size,
BSS size, and full footprint each against its own max,
and make Tegra boards check full footprint.

Also, output section mmutable is not used in SPL builds.
Remove it.

Finally, update README regarding the (now homogeneous)
semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new
CONFIG_SPL_MAX_FOOTPRINT macro.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-14 16:07:14 +02:00
Albert ARIBAUD
f84a7b8f54 ARM: Fix __bss_start and __bss_end in linker scripts
Commit 3ebd1cbc introduced compiler-generated __bss_start
and __bss_end__ and commit c23561e7 rewrote all __bss_end__
as __bss_end. Their merge caused silent and harmless but
potentially bug-inducing clashes between compiler- and linker-
generated __bss_end symbols.

Make __bss_end and __bss_start compiler-only, and create
__bss_base and __bss_limit for linker-only use.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-13 22:37:20 +02:00
Tetsuyuki Kobayashi
4411b2aea7 BUGFIX: arm: data abort in get_bad_stack_swi
When swi instruction is executed, it is expected to get message
"software interrupt" in console and dump registers and reboot, as
do_software_interrupt() in arch/arm/lib/interrupts.c.
But, actually it causes data abort accessing wrong address in get_bad_stack_swi
macro in arch/arm/cpu/v7/start.S.
This patch fixes this problem.

The same mistake in arch/arm/cpu/{arm1136,arm1176,pxa}/start.S.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
2013-04-13 11:12:46 +02:00
Albert ARIBAUD
0c669fd17a Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-04-13 09:39:29 +02:00
Albert ARIBAUD
1812201997 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/video/exynos_fb.c
2013-04-12 22:07:57 +02:00
man.huber@arcor.de
9d0fd10ca1 omap3: Display MHz instead of mHz on the console
The processor is hopefully running with M(ega)Hz and not with m(illi)Hz.

Signed-off-by: Manfred Huber <man.huber@arcor.de>
2013-04-12 15:29:23 -04:00
Albert ARIBAUD
c97b6df1ae Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-04-12 08:51:41 +02:00
Benoît Thébaudeau
1a9a91dcfa arm: Make all linker scripts compatible with per-symbol sections
Let all ARM linker scripts handle properly -ffunction-sections
and -fdata-sections. This will be useful for future changes in order to create
symbol-specific sections in common .S files.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:09 +02:00
Benoît Thébaudeau
9ce8e2386c arm1176: Remove unused MMU setup from start.S
Following the removal of the smdk6400 board, the MMU setup code in
arm1176/start.S becomes unused, so remove it. It will still be possible to
restore it later from the Git history if necessary, in which case it should be
moved out of the relocate_code() function.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:09 +02:00
Benoît Thébaudeau
66f30bf983 arm: Remove deprecated and now unused NAND SPL
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
e53232250b arm: Remove support for unused s3c64xx
Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so
remove associated code. It will still be possible to restore it later from the
Git history if necessary.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:08 +02:00
Benoît Thébaudeau
5c6db120fc arm: Remove unused relocate_code() parameters
Commit e05e5de7fa made the 2 1st parameters of
ARM's relocate_code() useless since it moved the code handling them to crt0.S.
So, drop these parameters.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
ac415a5720 arm926ejs: Remove deprecated and now unused NAND SPL
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
da962b7175 nand: mxc: Switch NAND SPL to generic SPL
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fa.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12 07:55:07 +02:00