u-boot/arch/arm/cpu
Nishanth Menon 18c9d55ac6 ARM: OMAP5: DRA7xx: support class 0 optimized voltages
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
..
arm720t arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
arm920t arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
arm925t arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
arm926ejs Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-06-08 14:35:10 +02:00
arm946es arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
arm1136 arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
arm1176 arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
arm_intcm arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
armv7 ARM: OMAP5: DRA7xx: support class 0 optimized voltages 2013-06-10 08:43:10 -04:00
ixp arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
pxa arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
s3c44b0 arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
sa1100 arm: factorize relocate_code routine 2013-05-30 20:24:38 +02:00
tegra-common ARM: tegra: only enable SCU on Tegra20 2013-06-06 09:12:32 -07:00
tegra20-common Tegra: Split tegra_get_chip_type() into soc & sku funcs 2013-04-15 11:01:38 -07:00
tegra30-common Tegra114: Initialize System Counter (TSC) with osc frequency 2013-04-15 11:01:38 -07:00
tegra114-common Tegra114: Initialize System Counter (TSC) with osc frequency 2013-04-15 11:01:38 -07:00
u-boot-spl.lds ARM: fix CONFIG_SPL_MAX_SIZE semantics 2013-04-14 16:07:14 +02:00
u-boot.lds ARM: fix CONFIG_SPL_MAX_SIZE semantics 2013-04-14 16:07:14 +02:00