The fsl_esdhc_init() was actually to get configuration of mmc_config.
So rename it to fsl_esdhc_get_cfg_common() and make it common for both
DM_MMC and non-DM_MMC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This patch is to clean up bus width setting code.
- For DM_MMC, remove getting "bus-width" from device tree.
This has been done in mmc_of_parse().
- For non-DM_MMC, move bus width configuration from fsl_esdhc_init()
to fsl_esdhc_initialize() which is non-DM_MMC specific.
And fix up bus width configuration to support only 1-bit, 4-bit,
or 8-bit. Keep using 8-bit if it's not set because many platforms
use driver without providing max bus width.
- Remove bus_width member from fsl_esdhc_priv structure.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Voltage validation should be done by CMD8. Current comparison between
mmc_cfg voltages and host voltage capabilities is meaningless.
So drop current comparison and let voltage validation is through CMD8.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Controller initialization is not needed in fsl_esdhc_init().
It will be done in esdhc_init() for non-DM_MMC, and in
esdhc_init_common() in probe for DM_MMC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
A previous patch below adding DDR mode support was actually for i.MX
platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC,
it uses different process for DDR mode, and hasn't been supported.
Let's drop DDR support code for i.MX in fsl_esdhc driver.
0e1bf61 mmc: fsl_esdhc: Add support for DDR mode
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
support it, so let's force to use it.
- Drop non-BLK support for DM_MMC introduced by below patch.
66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
- Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC).
- Use DM_MMC instead of BLK for conditional compile.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This patch adds a dts property cd-active-high for builtin-cd mode to make
it configurable instead of using hardcoded active-low.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
- Add sdhci driver for Broadcom iProc platform
- Add a driver callback for power-cycle for mmc
- Implement host_power_cycle callback for stm32_sdmmc2
- spl: dm_mmc: Initialize only the required mmc device
Power-domain is enabled by default in device_probe. am654 mmc driver
is enabling power-domain again in probe. As the second call is
redundant, drop power_domain_on from probe.
Tested-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
For the correct power cycle sequence with stm32_sdmmc2, the write of the
power cycle value in PWRCTL field of SDMMC_POWER register is now done in
stm32_sdmmc2_host_power_cycle() and no more in stm32_sdmmc2_pwrcycle().
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Some MMC peripherals require specific power cycle sequence, where some
registers need to be written between the regulator is turned off and then
back on. This is the case for the MMC IP embedded in STM32MP1 SoC.
In STM32MP157 reference manual [1], the power cycle sequence is:
1. Reset the SDMMC with the RCC.SDMMCxRST register bit. This will reset
the SDMMC to the reset state and the CPSM and DPSM to the Idle state.
2. Disable the Vcc power to the card.
3. Set the SDMMC in power-cycle state. This will make that the
SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low, to prevent the card
from being supplied through the signal lines.
4. After minimum 1ms enable the Vcc power to the card.
5. After the power ramp period set the SDMMC to the power-off state for
minimum 1ms. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are set to
drive “1”.
6. After the 1ms delay set the SDMMC to power-on state in which the
SDMMC_CK clock will be enabled.
7. After 74 SDMMC_CK cycles the first command can be sent to the card.
The step 3. cannot be handled by the current framework implementation.
A new callback (host_power_cycle) is created, and called in
mmc_power_cycle(), after mmc_power_off().
The incorrect power cycle sequence has shown some boot failures on
STM32MP1 with some SD-cards, especially on cold boots when the input
frequency is low (<= 25MHz).
Those failures are no more seen with this correct power cycle sequence.
[1] https://www.st.com/resource/en/reference_manual/DM00327659.pdf
Signed-off-by: Yann Gautier <yann.gautier@st.com>
In SPL, all the available mmc devices gets initialized during boot.
This might not work in cases where clocks are not available for
certain mmc devices(other than boot device) and the support for
enabling device might not be ready.
Texas Instruments' K3 J721E device having a central system controller
(dmsc) is one such example falling in this category. Below is the
sequence for the failing scenario:
- ROM comes up in SD mode and loads SPL by just initialing SD card.
- SPL loads dmsc firmware from SD Card.
Since ROM has enabled SD, SPL need not enable the SD, just need
to re initialize the card. But SPL is trying to initialize other MMC
instances which are in disabled state. Since dmsc firmware is not yet
available, devices cannot be enabled. So in SPL, initialize only the
mmc device that is needed.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
- Rename existing FSP code to fsp1
- Add fsp2 directory in preparation to support FSP 2.0
- Various x86 platform codes update
- Various bug fixes and updates in dm core, sandbox and spl
This change replaces printf() with debug() for the notification about
commands timeouts.
This is done on purpose (also other drivers use such approach - dw_mmc.c,
mvebu_mmc.c), as the mmc core code (mmc.c) uses timeouts to assess if one
is using sd card or eMMC device.
In such situation timeout is a some kind of a "normal" behavior and there
shall not be any output to the console.
There is no impact on boot time for boards using this driver (even in SPL)
when two extra timeouts are returned (no SD card present, only eMMC
available).
Boot time tested with grabserial:
sudo grabserial -b 115200 -d /dev/ttyUSB1 -e 30 -t -m "^U-Boot SPL*"
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch converts the mxsmmc driver to support DM/DTS.
Moreover, it is also possible to use it in early SPL with
SPL_OF_PLATDATA enabled.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The zynq_sdhci drivers depends on DM_MMC in Kconfig so no need to check for
DM_MMC in the driver so this patch removes it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
At present there is only one control for this and it is used for both SPL
and TPL. But SPL might have a lot more space than TPL so the extra cost of
a full printf() might be acceptable.
Split the option into two, providing separate SPL and TPL controls. The
TPL setting defaults to the same as SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present running sandbox with valgrind produces some warnings due to the
MMC emulator not filling in all the expected fields. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: use sizeof() instead of hardcoded 16]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add eMMC hs200 mode for ls1028a, ls1012a, lx2160a.
This increases eMMC performance.
Tuning procedure is currently not supported.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
NXP fsl_esdhc controller supports two reference clocks:
platform clock and peripheral clock
Peripheral clock can provide higher clock frequency
which is required to be used for tuning of SD UHS mode
and eMMC HS200/HS400 modes.
Peripheral clock is enabled by default by defining config
option FSL_ESDHC_USE_PERIPHERAL_CLK if eMMC HS200/HS400 modes
are supported.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
- fix bcm2835_sdhost to wait long enough for a transfer to complete
- increase kernel image size from 8 MB to 64 MB on arm64
- add support for RPi4
- add prefixes for raspberry pi related stuff to git-mailrc
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Merge tag 'rpi-next-2019.10' of https://github.com/mbgg/u-boot
- fix mailbox status register used for polling
- fix bcm2835_sdhost to wait long enough for a transfer to complete
- increase kernel image size from 8 MB to 64 MB on arm64
- add support for RPi4
- add prefixes for raspberry pi related stuff to git-mailrc
The bcm2711 has two emmc controllers. The difference is the clocks
they use. Add support for the second emmc controller.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Andrei Gherzan <andrei@balena.io>
Function bcm_2835_wait_transfer_complete() is not waiting long enough.
The previous code was claiming to wait for ~1 seconds, but as it depends
on register reads it's time actually varies.
Some cards require wait times of up to ~56 ms to perform
the command 'saveenv' on an EXT4 partition.
Re-implement the loop exit condition to use get_timer() which allows
to specify the wait time in more reliable manner. Set the maximum wait
time to the originally intended 1 second.
Signed-off by: Raul Benet <raul.benet_at_kaptivo.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
The sdhci capabilities registers can be incorrect. The
sdhci-caps-mask and sdhci-caps dt properties specify which bits of
the registers are incorrect and what their values should be. This
patch makes the sdhci driver use those properties to correct the caps.
Also use "dev_read_u64_default" instead of "dev_read_u32_array" for
caps mask.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The mmc_spi driver's priv is not available in its bind phase(). Use
platdata instead.
Fixes: 05e35d4297 ("mmc: mmc_spi: Re-write driver using DM framework")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
There are two cases not been considered:
- use uint for timeout, it will overflow when size bigger than 512KB for
it *8*1000 at the beginning, but we may use size up to 32MB; The
'timeout' will overflow if size bigger than 51.2MB after this fix, which
should be enough for U-Boot;
- The timeout is using clock speed for data rate, but the device may not
have such high speed, eg. clock is 52MHz while the device write speed may
be less than 10MB/s, and we may use up to 150MHz clock.
Fix them in this patch, the max timeout is about 6500 when size is 32MB
after fix.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
It's quite hard to figure out time units for various function that have
timeout parameters. This leads to possible errors when one forgets to
convert ms to us, for example. Let's rename those parameters
correspondingly to 'timeout_us' and 'timeout_ms' to prevent such issues
further.
While at it, add time units info as comments to struct mmc fields.
This commit doesn't change the behavior, only renames parameters names.
Buildman should report no changes at all.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
mmc_wait_dat0() expects timeout argument to be in usec units. But some
overlying functions operate on timeout in msec units. Convert timeout
from msec to usec when passing it to mmc_wait_dat0().
This fixes 'avb' commands on BeagleBoard X15, because next chain was
failing:
get_partition() -> mmc_switch_part() -> __mmc_switch() ->
mmc_wait_dat0()
when passing incorrect timeout from __mmc_switch() to mmc_wait_dat0().
Fixes: bb98b8c5c0 ("mmc: During a switch, poll on dat0 if available and check the final status")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Tested-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
When look through the code, I found this bare metal
drives is not used, so remove it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
eMMC device has multiple hw partitions both address from zero. However the
mmc driver lacks block cache invalidation for switch hwpart. This causes a
problem that data of current hw partition is cached before switching to
another hw partition. And the following read operation of the latter hw
partition will get wrong data when reading from the addresses that have
been cached previously.
To solve this problem, invalidate block cache after a successful
mmc_switch_part() operation.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Felix Brack <fb@ltec.ch>
This patch solves a watchdog reset issue during mmc erase command.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
host->mmc, host->mmc->dev and host->mmc->priv must be set
before calling sdhci_setup_cfg() to avoid hang during mmc
initialization.
Thanks to commit 3d296365e4
("mmc: sdhci: Add support for sdhci-caps-mask") which put
this issue into evidence.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Increase SDMMC_BUSYD0END_TIMEOUT_US from 1s to 2s to
avoid timeout error during blocks erase on some sdcard
Issue seen on Kingston 16GB :
Device: STM32 SDMMC2
Manufacturer ID: 27
OEM: 5048
Name: SD16G
Bus Speed: 50000000
Mode: SD High Speed (50MHz)
card capabilities: widths [4, 1] modes [SD Legacy, SD High Speed (50MHz)]
host capabilities: widths [4, 1] modes [MMC legacy, SD Legacy, MMC High Speed (26MHz), SD High Speed (50MHz), MMC High Speed (52MHz)]
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
Issue reproduced with following command:
STM32MP> mmc erase 0 100000
MMC erase: dev # 0, block # 0, count 1048576 ... mmc erase failed
16384 blocks erased: ERROR
By setting SDMMC_BUSYD0END_TIMEOUT_US at 2 seconds and by adding
time measurement in stm32_sdmmc2_end_cmd() as shown below:
+start = get_timer(0);
/* Polling status register */
ret = readl_poll_timeout(priv->base + SDMMC_STA,
status, status & mask,
SDMMC_BUSYD0END_TIMEOUT_US);
+printf("time = %ld ms\n", get_timer(start));
We get the following trace:
STM32MP> mmc erase 0 100000
MMC erase: dev # 0, block # 0, count 1048576 ...
time = 17 ms
time = 1 ms
time = 1025 ms
time = 54 ms
time = 56 ms
time = 1021 ms
time = 57 ms
time = 56 ms
time = 1020 ms
time = 53 ms
time = 57 ms
time = 1021 ms
time = 53 ms
time = 57 ms
time = 1313 ms
time = 54 ms
time = 56 ms
time = 1026 ms
time = 54 ms
time = 56 ms
time = 1036 ms
time = 54 ms
time = 56 ms
time = 1028 ms
time = 53 ms
time = 56 ms
time = 1027 ms
time = 54 ms
time = 56 ms
time = 1024 ms
time = 54 ms
time = 56 ms
time = 1020 ms
time = 54 ms
time = 57 ms
time = 1023 ms
time = 54 ms
time = 56 ms
time = 1033 ms
time = 53 ms
time = 57 ms
....
time = 53 ms
time = 57 ms
time = 1021 ms
time = 56 ms
time = 56 ms
time = 1026 ms
time = 54 ms
time = 56 ms
1048576 blocks erased: OK
We see that 1 second timeout is not enough, we also see one measurement
up to 1313 ms. Set the timeout to 2 second to keep a security margin.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This converts the following to Kconfig:
CONFIG_FSL_USDHC
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add IMX8M, TARGET_S32V234EVB to FSL_USDHC list]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit adds MMC driver support for HI3660 SoC reusing hi6220_dw_mmc
driver. Since HI3660 operates at different clock rate and uses fifo
mode now, let's introduce the platform data and utilize it for different
SoCs supported by this driver.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This is a configuration option specific to the tegra controller.
Doing it this way makes it show up directly under the tegra controller
option, indented one level, as "Disable external clock loopback".
The way it is now, it shows up at the end of the controller list, not
indented, as if it's some kind of generic MMC configuration option.
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
- Add rk3399 boards Khadas Edge/-V/-Captain
- Add fully souce code support for rk3328 including TPL/DRAM init
- Enable boot from eMMC for rk3399 rock960/ficus boards
- turn on the IO supply for dw_mmc
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.
Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.
Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.
Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.
Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.
Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Matthias Brugger <mbrugger@suse.com>
Cc: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.
Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Since commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field. Move the mmc field initialization before sdhci_setup_cfg()
call to avoid crash on mmc pointer dereference.
[this patch is based on commit 41a9fab8da ("mmc: mv_sdhci: fix
uninitialized pointer deref on probe") by Baruch Siach]
Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu102/zc706)
Select SPL_HS200_SUPPORT if SPL_HS400_SUPPORT is selected as is being
done for the U-boot case.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The comment about init op being NULL used to be next to the NULL check
code. Commit 8ca51e51c1 ("dm: mmc: Add a way to use driver model for
MMC operations") separated the comment from the code. Put them back
together.
Fixes: 8ca51e51c1 ("dm: mmc: Add a way to use driver model for MMC operations")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When reading large data in once (reading 512MiB is tested on MT7623), a
watchdog timeout is triggered due to watchdog not being fed.
This patch adds WATCHDOG_RESET() to msdc_start_data() so the watchdog will
be fed every 1024 blocks are read/written.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The standard property name for chip-detect gpio is "cd-gpios". All
in-tree DT files use only this name.
Fixes: 451931ea70 ("mmc: sdhci: Read cd-gpio from devicetree")
Cc: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field. Move the mmc field initialization before sdhci_setup_cfg()
call to avoid crash on mmc pointer dereference.
Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Fixes the microSD slot on the ASUS C201.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com<mailto:peng.fan@nxp.com>>
The j721e 4 bit instances don't have a hard DLL and therefore don't need
any DLL related configurations. Split the compatibles into an 8 bit and a
4 bit one. Add a private flags field which can be used to check if the
DLL is present and don't register the set_ios_post callback for the 4 bit
compatible instances.
Also update the compatibles in k3-j721e-main.dtsi to avoid breaking boot
with the new compatibles.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This patch fix mmc driver abort caused by below patch:
3d296365e4 mmc: sdhci: Add support for sdhci-caps-mask
After the patch sdhci_setup_cfg() access to host->mmc->dev,
so we have to do init before make the call to the function()
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Most DM based SPI host controller drivers use SPI_XFER_BEGIN and
SPI_XFER_END flags to enable/disable slave chip select.
This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when
MMC command is send at start and pass SPI_XFER_END flag using a
dummy transfer (of bitlen = 0) at the end of MMC command.
Suggested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
We would like to use the driver even without power domains being
specified for cases such as during early boot when the required power
domains have already gotten enabled by the SoC's boot ROM and such
explicit initialization is not needed and possible.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add a platform specific set_control_reg() callback to help switch to
UHS speed modes.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
to arasan/zynq controllers. Add the same to sdhci.h.
Also create a common API to set UHS timings in HOST_CONTROL2.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support in the driver for handling phy specific registers.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The am654_sdhci driver needs to switch the clock off
before disabling its phy dll and needs to re-enable
the clock before enabling the phy again.
Therefore, make the sdhci_set_clock() function accessible
in the am654_sdhci driver.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add Support for masking some bits in the capabilities
register of a host controller.
Also remove the redundant readl() into caps1.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The host controller works perfectly well without having to add any
quirks. Remove them.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sync the sdhci0 node from kernel. This changes the compatible that is
required to be there in the driver. Change the same for the SD card node
which is not yet supported in kernel. This also syncs the main_pmx0 node
as a side effect.
Also change the name of the driver to match the compatible in kernel.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
- mmc spi driver model support
- drop mmc_spi command
- enhanced Strobe mmc HS400 support
- minor mmc bug/fixes and optimization
- omap hsmmc and mvbeu update
- sdhci card detect support
Flash system partition with fastboot will earse the partition firstly
The 600ms timeout will fail on some SD Card. Enlarge it to 5s to make
it works for most of sdcard
Cc: guoyin.chen <guoyin.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Implement set_enhanced_strobe hook for fsl_esdhc_imx,
,in esdhc_set_timing and esdhc_change_pinstate, also handle HS400_ES.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
eMMC 5.1+ supports HS400 Enhances Strobe mode without the need for
tuning procedure.
The flow is as following:
- set HS_TIMIMG (Highspeed)
- Host change freq to <= 52Mhz
- set the bus width to Enhanced strobe and DDR8Bit(CMD6),
EXT_CSD[183] = 0x86 instead of 0x80
- set HS_TIMING to 0x3 (HS400)
- Host change freq to <= 200Mhz
- Host select HS400 enhanced strobe complete
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Should use CONFIG_IS_ENABLED not IS_ENABLED for clock and regulator drivers,
CONFIG_IS_ENABLED will check the CONFIG_SPL_CLK and CONFIG_SPL_DM_REGULATOR
when building SPL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch rewrites MMC SPI driver using U-Boot DM
framework and get it's working on SiFive Unleashed
board.
Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The MMC mode and width are fixed for MMC SPI host hence we skip
sd_select_mode_and_width() and mmc_select_mode_and_width() for
MMC SPI host.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Accessing the boot partition had been error prone with HS200 and HS400 and
was disabled. The driver first switched to a lesser mode and then switched
the partition access. It was mostly due to a bad handling of the switch and
has been fixed, so let's remove this 'feature'
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The switch operation can sometimes make the bus unreliable, in that case
the send_status parameter should be false to indicate not to poll using
CMD13. If polling on dat0 is possible, we should use it to detect the end
of the operation.
At the end of the operation it is safe to use CMD13 to get the status of
the card. It is important to do so because the operation may have failed.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The e-MMC spec allows the e-MMC to specify a timeout for the partition
switch command. It can take up to 2550 ms. There is no lower limit to this
value in the spec, but do as the the linux driver does and force it to be
at least 300ms.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Starting with rev 4.5, the eMMC can define a generic timeout for the
SWITCH command.
Following Linux Kernel code, the timeout also changed from 1000 -> 500
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Using the DAT0 line as a rdy/busy line is an alternative to reading the
status register of the card. It especially useful in situation where the
bus is not in a good shape, like when modes are switched.
This is also how the linux driver behaves.
Note of warning: As per the specification, while polling on DAT0 the CLK
must not turned off: "[...] Without a clock edge the Device (unless
previously disconnected by a deselect command (CMD7)) will force the DAT0
line down, forever. [...]"
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
mmc_send_status() is currently used to poll the card until it is ready, not
actually returning the status of the card.
Make it return the status and add another function to poll the card.
Also remove the 'extern' declaration in the mmc-private.h header to comply
with the coding standard.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This reverts commit 318a7a576b.
The last and only user of this callback had been the omap_hsmmc driver.
It is not used anymore. Removing the callback.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This is not required. The MMC core sends CMD0 right after the
initialization and it serves the same purpose.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
It sometimes happen that the PSTATE register does not indicate that the
bus is ready when it really is. This usually happens after a mode switch.
In that case it makes sense to reset the FSM handling the CMD and DATA
Also reset the FSMs if the STATE register cannot be cleared. This also
sometimes happens after a mode switch.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
The response type of CMD25 is R1 instead of R1b.
Signed-off-by: Akio Hirayama <hirayama.akio@socionext.com>
[masahiro: add log ]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Card detect function implemented for SDHCI framework.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch reads cd-gpio property from devicetree
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This patch reads card detect properties from device tree &
added mmc capability macros in mmc.h.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When MMC_TINY is enabled, support for only one MMC device
is provided. Boards that register more than one device,
will just write over mmc_static keeping only the last one
registered.
This commit prevents this, keeping only the first MMC
device created. A debug warning message is added, if nothing
else, as a hint/documentation for developers.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
The SPL_MMC_TINY implements feature-reduced MMC support
on SPL, and as such, it's more consistent and convenient
to find it as part of the SPL configuration.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
This patch solves warnings detected by setting W=1 when building.
Warnings type detected:
- [-Wmissing-prototypes]
- [-Wimplicit-fallthrough=]
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series PowerPC processors (which were
evolutions of MPC83XX/MPC85XX), QorIQ series ARM processors, and
i.MX series processors were using this driver for their eSDHCs too.
For the two series processors, the eSDHCs are becoming more and
more different. We should have split it into two drivers, like them
(sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel.
This patch is just to create a fsl_esdhc_imx driver which is a copy
of fsl_esdhc driver for i.MX processors. We will convert i.MX processors
to use fsl_esdhc_imx, and clean up the two drivers separately in the
future patches.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
u-boot is trying to make CONFIG_BLK as a hard requirement
for DM_MMC. But now it's still not.
config BLK
bool "Support block devices"
depends on DM
default y if DM_MMC
When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC
without CONFIG_BLK enabled wasn't considered. This patch is to
fix probe issue without CONFIG_BLK enabled.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
U-Boot code currently only applies this restriction to HS200 mode,
extend this to HS400 mode as well.
Currently U-Boot code not support accessing boot partition in HS200/400
mode. This needs more check.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
For bcm7445 and bcm7260, this patch enables CONFIG_DM_MMC and updates
the bcmstb SDHCI driver to use the new driver model. This allows
removal of SDHCI configuration handling from bcmstb.c, and eliminates
a board removal compile warning.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Reviewed-by: Stefan Roese <sr@denx.de>
- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.
PowerPC supports 32 bit address.
So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Since Gen3 SDHI has an internal DS signal AC-spec violation in HS400 mode,
CRC-error may occur in read command in HS400 mode. This phoenomenon occurs
at low/high temperature.
To fix this, after completion of HS400 tuning, enable manual calibration.
However, Gen3 M3 Ver.1.2 or earlier and H3 1.x does not support HS400.
These SoC forcibly use HS200 mode by SoC attribute.
The DT adjustment of the tuning parameters is not supported until the
DT property names become clear.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Adapted from a patch by Takeshi Saito <takeshi.saito.xv@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Peng Fan <peng.fan@nxp.com>
Clean up the whitespaces in macros, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Peng Fan <peng.fan@nxp.com>
This reverts commit 72a89e0da5, which
causes the imx53 HSC to hang as the eMMC is not working properly anymore.
The exact error message:
MMC write: dev # 0, block # 2, count 927 ... mmc write failed
0 blocks written: ERROR
imx53 is not using the DDR mode.
Debugging of pre_div and div generation showed that those values are
generated in a way, which is not matching the ones from working setup.
As the original patch was performing code refactoring, let's revert this
change, so all imx53 boards would work again.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This converts the following to Kconfig:
CONFIG_SUPPORT_EMMC_BOOT
As requested by Michal Simek <michal.simek@xilinx.com>, these boards
have no eMMC so CONFIG_SUPPORT_EMMC_BOOT has not been migrated:
xilinx_zynqmp_zc1275_revB
xilinx_zynqmp_zc1751_xm018_dc4
xilinx_zynqmp_zc1751_xm019_dc5
xilinx_zynqmp_zcu100_revC
xilinx_zynqmp_zcu102_rev1_0
xilinx_zynqmp_zcu102_revA
xilinx_zynqmp_zcu102_revB
xilinx_zynqmp_zcu104_revA
xilinx_zynqmp_zcu104_revC
xilinx_zynqmp_zcu106_revA
xilinx_zynqmp_zcu111_revA
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
The Standard Host Controller Interface (SDHCI) specification version
3.00 adds support for Advanced DMA (ADMA) for both 64 and 32 bit widths
of DMA. ADMA2 uses a table of descriptors for aggregating DMA requests.
This significantly improves read and write throughput.
Add Support for the same.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
In preparation for addition of ADMA2 support, cleanup SDMA handling by
moving it to a new sdhci_prepare_dma() function. Also add a flags field
in sdhci_host to indicate if DMA is enabled.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
The wp-gpios property is used for gpio, if this is set, the WP pin is muxed
to gpio function, can't be used as internal WP checking. However the codes
remain to use internal WP checking.
This patch changes to examine the "fsl,wp-controller" for enabling internal WP
checking, and "wp-gpios" for muxing to gpio.
Signed-off-by: Ye Li <ye.li@nxp.com>
When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the output clock rate is half of the internal clock rate.
This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The driver currently calculates the end address of cache flush operation
for the DMA descriptors by adding cacheline size to the start address of
the last DMA descriptor. This is not safe, as the cacheline size may be,
in some unlikely cases, smaller than the DMA descriptor size. Replace the
addition with roundup() applied on the end address of the last DMA
descriptor to round it up to the nearest cacheline size multiple.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
The bounce_buffer_start() can return -ENOMEM in case memory allocation
failed. However, in that case, the bounce buffer address is the same as
the possibly unaligned input address, and the cache maintenance operations
were not applied to this address. This could cause subtle problems. Add
handling for the bounce_buffer_start() return value to prevent such a
problem from happening.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
The current 4-minute data transfer timeout is misleading and broken.
Instead of such a long wait, calculate the timeout duration based on
the length of the data transfer. The current formula is the transfer
length in bits, divided by a multiplication of bus frequency in Hz,
bus width, DDR mode and converted the mSec. The value is bounded from
the bottom to 1000 mSec.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
The new DM implementation currently does not support the Sheeva
88SV331xV5 specific quirk present in the legacy implementation. The
legacy code is thus kept for this SoC and others not yet migrated to
DM_MMC.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO).
IS_ENABLE(FOO) will always return false.
This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO)
syntax.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Some MediaTek SoC need an additional clock "source_cg". Enable
this new clock. We reuse the same clock name as in the kernel.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
On response type r1b, if DTIME is not defined or too short,
the Datatimeout and DPSM flag occurs. Like the DPSM is
activated all next data transfer will be frozen.
To avoid this freeze:
-The driver must define a DTIME on all r1b response type.
-DTIME of SDMMC must be defined for alls stop transmission
(for read and write request) even if MMC_RSP_BUSY is not set.
-If busy timeout occur, an abort request must be sent to
reinitialize the DPSM.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Initially the compatible string was wrongly set to "st,stm32f4xx-sdio".
Use compatible string used by kernel instead and identify mmci variant
using "arm,primecell-periphid" property.
Currently, the DM part of mmci driver is only used by STM32 SoCs,
that's why the switch case gets only one entry. It will be populated
easily with new variant in the future.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add the DM_MMC-compatible DesignWare MMC driver support for Synopsys
ARC devboards. It is created to switch ARC devboards to use DM_MMC.
It required information such as clocks (Bus Interface Unit clock,
Card Interface Unit clock) and SDIO bus width.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Pbias voltage should match the IO voltage set for the SD card. With the
latest pbias change to 3.3V, update the capabilities and IO voltages
settings to 3.3V.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
After the commit b9a2a0e2e9 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.
During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true for two reasons. First,
make sure in the function mmc_set_card_speed(), after switch to HS
mode, first config the clock rate, then read the EXT_CSD, avoid
receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue
the MMC_CMD_SWITCH command, it need to wait a bit then switch bus
properties.
Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
On 16bit variants of the TMIO SD IP, the SECCNT register can only be
programmed to 16bit values, while on the 32bit and 64bit variants it
can be programmed to 32bit values. The SECCNT register indicates the
maximum number of blocks in a continuous transfer. Hence, limit the
maximum continuous transfer block count to 65535 blocks on 16bit
variants of the TMIO IP and to BIT(32)-1 blocks on 32bit and 64bit
variants.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Set MMCIF clock rate to 97.5 MHz, which is the default according
to Gen2 datasheet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
The tiny printf implementation only supports %x format specifier,
it does not support %X . Since it makes little difference whether
the debug output prints hex numbers in capitals or not, change it
to %x and make the MMC_TRACE output work with tiny printf too.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
According to latest specification rev.0026 and after confirmation with
HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on
H3 ES2.0 SoC. Make it so.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
According to latest specification rev.0026, when HOST_MODE bit 0
(WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear
HOST_MODE bit 8 in such case and align the code with Linux and
avoid possible unforeseen issues.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Poll for iDMAC TX/RX interrupt before disable DMA.
This to prevent disable DMA before data is transfer
completed.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
The DT2FF register must be configured differently for HS400 mode
and for HS200/SDR104 mode. Configure the DT2FF register according
to the recommended datasheet settings for each mode.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Set the HOST_MODE register WMODE bit according to the SDHI bus width,
that is 0 for 64bit bus and 1 for 16/32bit bus.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Older kernel versions or systems which do not connect eMMC reset line
properly may not be able to handle situations where either the eMMC
is left in HS200/HS400 mode or SD card in UHS modes by the bootloader
and may misbehave. Downgrade the eMMC to HS/HS52 mode and/or SD card
to non-UHS mode before booting the kernel to allow such older kernels
to work with modern U-Boot.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Common sound support
buildman environment support
of-platdata documentation improvements
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Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dm
Samsung sound patches (applied for Samsung maintainer)
Common sound support
buildman environment support
of-platdata documentation improvements
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while enabling io regulators. This way the driver doesn't see an error
when disabling an always-on regulator and when enabling is not supported.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remove those boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions
(SPRZ426D - November 2014 - Revised February 2018 [1]) mentions
unexpected tuning pattern errors. A small failure band may be present
in the tuning range which may be missed by the current algorithm.
Furthermore, the failure bands vary with temperature leading to
different optimum tuning values for different temperatures.
As suggested in the related Application Report (SPRACA9B - October 2017
- Revised July 2018 [2]), tuning should be done in two stages.
In stage 1, assign the optimum ratio in the maximum pass window for the
current temperature. In stage 2, if the chosen value is close to the
small failure band, move away from it in the appropriate direction.
References:
[1] http://www.ti.com/lit/pdf/sprz426
[2] http://www.ti.com/lit/pdf/SPRACA9
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.
Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
The internal DMAC asserts DMA transfer end bit too early on older
version of the TMIO IPs which use bit 17 for DTRAEND. Add 1uS
delay after the completion of DMA transfer and before invalidating
the cache to let the DMAC fully complete the transfer. Otherwise,
it could happen that the last few bytes of a transferred data are
not available.
A test case to trigger this behavior is the following command, ran
on the U-Boot command line, with Sandisk 16 GiB UHS-I card inserted
into SDHI slot 0 and with first partition being of type FAT:
=> while true ; do mmc rescan ; fstype mmc 0:1 ; done
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Different versions of the SDHI core use either bit 17 or bit 20 for the
DTRAEND indication, which can differ even between SoC revisions. Make
the DTRAEND bit position part of the driver private data, so that the
probe function can set this accordingly. Set this to 20 on Socionext
SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
If a board DT describes a cd-gpios property, but also marks the storage
as non-removable, we must ignore the GPIO (as Linux does).
Teach the DM_MMC part of the Allwinner MMC driver about the
non-removable DT property, to fix DM_MMC access on the SoPine and
Pine64-LTS board.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Now that we have the gate clocks and the reset gates in our new
Allwinner clock driver, let's make use of them in the MMC driver, when
DM_MMC is defined.
We treat the reset device as optional now, as the older SoCs don't
implement it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
A80 gates clock already be part of CLK framework, so just
add mod_clk offset with A80 compatible string.
Cc: Rask Ingemann Lambertsen <rask@formelder.dk>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset.
Connect that with the respective compatible string.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add MMC compatible strings for A83T, A64, H5.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This patch has been tested on the mcf54415-based stmark2
board. The eSDHC driver works reliably using DMA mode.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
It is not possible to link the SPL image when CONFIG_GPIO is enabled
but CONFIG_SPL_GPIO is not. Use the IS_ENABLED macro instead to
correctly check whether CONFIG_{SPL_}GPIO is enabled.
This commit fixes the following errors:
* undefined reference to `dm_gpio_get_value
* undefined reference to `gpio_request_by_name'
Signed-off-by: Fabien Parent <fparent@baylibre.com>
[trini: Move guard to fix warning in msdc_ops_get_wp()]
Signed-off-by: Tom Rini <trini@konsulko.com>
The code is checking for incomplete read when it see the INT_XFER_COMPL
flag, but it forget to first check whether there is anything left in the
FIFO to copy to the RX buffer. This means that sometimes we will get
errors because of erroneous incomplete read operation.
This commit fixes the driver re-ordering the code so that we first
check for data inside the RX fifo and only after check the status
of the INT_XFER_COMPL flag.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
This variable was incorrectly added by:
"mmc: zynq_sdhci: Add support for SD3.0"
(sha1: d1f4e39d58)
which had nothing to do with MMC power sequence provider.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The bounce buffer is used by a few drivers (most of the MMC drivers)
to overcome limitations in their respective DMA implementation.
This moves the configuration to Kconfig and makes it user-selectable
(even though it will be a required feature to make those drivers
work): the expected usage is for drivers depending on this to 'select'
it unconditionally from their respective Kconfig (see follow-up
patches).
This commit includes a full migration using moveconfig.py to ensure
that each commit compiles. To ensure bisectability we update
dependencies of various drivers to now select BOUNCE_BUFFER when needed.
[trini: Squash all patches to ensure bisectability]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br> [dw_mmc portion]
Reviewed-by: Fabio Estevam <festevam@gmail.com> [mxsmmc portion]
Reviewed-by: Simon Glass <sjg@chromium.org> [tegra portion]
Do not build write support, unless it's enabled.
In the SPL case, this change will typically remove
precious bytes (as write support is most often
not needed in SPL).
This is important on this platform, where the maximum
SPL size is 14 KiB.
With gcc v7.3, this change saves 144 bytes producing:
size spl/u-boot-spl
text data bss dec hex filename
9240 752 712 10704 29d0 spl/u-boot-spl
To make the code easier to compile-out and more
readable, a pair of read_data/write_data helpers are created.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Use CONFIG_IS_ENABLED(BLK) instead of CONFIG_BLK,
in order to fix the following build issues when
CONFIG_SPL_MMC_WRITE is selected:
drivers/mmc/mmc_write.c:69:7: error: conflicting types for 'mmc_berase'
ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
^~~~~~~~~~
In file included from drivers/mmc/mmc_write.c:15:0:
drivers/mmc/mmc_private.h:39:7: note: previous declaration of 'mmc_berase' was here
ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt);
^~~~~~~~~~
drivers/mmc/mmc_write.c:187:7: error: conflicting types for 'mmc_bwrite'
ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
^~~~~~~~~~
In file included from drivers/mmc/mmc_write.c:15:0:
drivers/mmc/mmc_private.h:37:7: note: previous declaration of 'mmc_bwrite' was here
ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
^~~~~~~~~~
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The mmc_select_mode_and_width() function can be called while the card
is in HS200/HS400 mode and can be used to downgrade the card to lower
mode, e.g. HS. This is used for example by mmc_boot_part_access_chk()
which cannot access the card in HS200/HS400 mode and which is in turn
called by saveenv if env is in the MMC.
In such case, forcing the card clock to legacy frequency cannot work.
Instead, the card must be switched to HS mode first, from which it can
then be reprogrammed as needed.
However, this procedure needs additional code changes, since the current
implementation checks whether the card correctly switched to HS mode in
mmc_set_card_speed(). The check only expects that the card will be going
to HS mode from lower modes, not from higher modes, hence add a parameter
which indicates that the HS200/HS400 to HS downgrade is happening. This
makes the code send the switch command first, reconfigure the controller
next and finally perform the EXT_CSD readback check. The last two steps
cannot be done in reverse order as the card is already in HS mode when
the clock are being switched on the controller side.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Convert HiSilicon HI6220 MMC driver based on DWMMC IP to driver
model.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Enable this on poplar]
Signed-off-by: Tom Rini <trini@konsulko.com>
The following hang is observed on a Hummingboard 2 MicroSOM
i2eX iMX6D - rev 1.3 with no eMMC populated on board:
U-Boot SPL 2018.11+gf6206f8587 (Nov 16 2018 - 00:56:34 +0000)
Trying to boot from MMC1
U-Boot 2018.11+gf6206f8587 (Nov 16 2018 - 00:56:34 +0000)
CPU: Freescale i.MX6D rev1.5 996 MHz (running at 792 MHz)
CPU: Extended Commercial temperature grade (-20C to 105C) at 33C
Reset cause: POR
Board: MX6 HummingBoard2
DRAM: 1 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment
No panel detected: default to HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
---> hangs
which is caused by the following infinite loop inside esdhc_send_cmd_common()
while (!(esdhc_read32(®s->irqstat) & flags))
;
Instead of looping forever, provide an exit path so that a timeout
error can be propagated in the case irqstat does not report
any interrupts, which may happen when no eMMC is populated on
board.
Reported-by: Ricardo Salveti <rsalveti@rsalveti.net>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Ricardo Salveti <rsalveti@rsalveti.net>
Existing clock configure code has been followed based on the
legacy MMC dt node definitions and it cannot work with recent
dts(i) sync from Linux.
So, add clock configure code for Allwinner platforms which support
DM_MMC and eventually this will drop once CLK support is in Mainline.
Fixes: 3c92cca3cd ("ARM: dts: sun4i: Update A10 dts(i) files from Linux-v4.18-rc3")
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Priit Laes <plaes@plaes.org> # Gemei G9 A10 Tablet
Tested-by: Marek Kraus <gamelasterv2@gmail.com> # A10-OLinuXino-Lime
Commit d0851c8937 ("blk: Call part_init() in the post_probe() method")
removed the call to part_init() in mmc.c, as this is done by the DM_MMC
framework.
However Allwinner is (still) relying on a non-DM MMC driver, so we are
now missing the implicit partition init, leading to failing MMC accesses
due to the missing partition information.
Bring the call back just for non-DM MMC driver to fix this regression.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Soeren Moch <smoch@web.de>
Add driver for the JZ47xx MSC controller.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure. Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
According to SD Specifications Part 1 Physical Layer Simplified Specification
Version 6.00 August 29, 2018, section 4.3.10 (Switch Function Command) and
section 5.6 (SCR register), SD cards version 1.00 and 1.01 do not support the
SD CMD 6.
Currently, U-Boot will issue CMD 6 unconditionally in sd_set_card_speed()
while configuring the bus for selected frequency. This will make SD cards
version 1.00 and 1.01 time out and thus fail detection altogether.
Fix this by not sending CMD 6 on such cards. Tested on Matsushita Electric
Industrial Co., Ltd. Japan RP-SD008B / Victor 8MB SD card, CU-SD008, which
is correctly detected with this patch as:
Device: sd@ee160000
Manufacturer ID: 1
OEM: 5041
Name: S008B
Bus Speed: 25000000
Mode : SD Legacy
Rd Block Len: 512
SD version 1.0
High Capacity: No
Capacity: 6.5 MiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add support for the HS400 mode to SDHI driver. This uses the up-tune
mechanism from already supported HS200 tuning.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Move the tap_pos variable, which is the HS200/HS400/SDR104 calibration
offset, into private data, so it can be passed around. This is done in
preparation for the HS400 mode, which needs to adjust this value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Filter out HS400 support on SoCs where HS400 is not supported yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Reorder the tmio_sd_set_clk_rate() function such that it handles all
of the clock requiests correctly. Specifically, before this patch,
clock request with (mmc->clock == 0 && mmc->clk_disable) could leave
the clock enabled, as the function would exit on if (!mmc->clock)
condition on top and will not handle the mmc->clk_disable at all.
Rather than band-aid fixing just that particular problem, reorder
the entire function to make it easier to understand and verify that
all the cases are covered. The function has three sections now:
First, if mmc->clock != 0, we calculate divider for the SD block.
Second, if mmc->clock != 0 and SD block clock are enabled and
current divider is not equal to the new divider, then
stop the clock and update the divider.
Third, if mmc->clk_disable is set, disable the clock, otherwise
enable the clock. This happens independently of divider
update now.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The TMIO core has a feature where it can automatically disable clock output
when the bus is not in use. While this is useful, it also interferes with
switching the bus to 1.8V and other background tasks of the SD/MMC cards,
which require clock to be enabled.
This patch respects the mmc->clk_disable and only disables the clock when
the MMC core requests it. Otherwise the clock are continuously generated
on the bus.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Switch the driver to using clk_get_rate()/clk_set_rate() instead of
caching the mclk frequency in it's private data. This is required on
the SDHI variant of the controller, where the upstream mclk need to
be adjusted when using UHS modes.
Platforms which do not support clock framework or do not support it
in eg. SPL default to 100 MHz clock.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
---
V2: - Fix build on certain platforms using SPL without clock framework
V3: - Turn clk_get_rate into a callback and fill it as needed on both
renesas and socionext platforms
Add HS400 properties parsing support to mmc_of_parse().
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Using new mode improves stability of eMMC and SD cards. Without
it SPL fails to load u-boot from SD on Pinebook.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@openedev.com>
Comment in Linux driver says that clock needs to be doubled only
if we use DDR modes, moreover divider has to be set accordingly.
U-boot driver doesn't declare support for any DDR modes and doesn't
set internal clock divider in CLKCR, so it doubles clock
unconditionally when new mode is used.
Some cards can't handle that and as result SPL fails to load u-boot.
Fixes: de9b1771c3 ("mmc: sunxi: Support new mode")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Allwinner A64 has new mode but doesn't have a mode switch in CCM,
and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails
if MMC_SUNXI_HAS_NEW_MODE is enabled
Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage
of CCM_MMC_CTRL_MODE_SEL_NEW
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: update commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.
To mitigate this potential impact, the following changes are
implemented:
- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
part_init() is currently called in every DM BLK driver, either
in its bind() or probe() method. However we can use the BLK
uclass driver's post_probe() method to do it automatically.
Update all DM BLK drivers to adopt this change.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
A64 and H6 support automatic delay calibration and Linux driver uses it
instead of hardcoded delays. Add support for it to u-boot driver.
Fixes eMMC instability on Pinebook
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch adds check for command response CRC failure. The driver
is currently ignoring CRC check failure on command resposes which
have CRC atteched to it, which can be potentially dangerous. Even
more grueling problem happens when the command response is followed
by data transfer though, as in that case, the dwmci_data_transfer()
function will spin until it reaches the 240s timeout.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
It is perfectly fine to write th DTCNTL TAP count and enable the
SCC sampling clock operation in the same write.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
When the bus switches to 1.8V mode of operation, it is necessary to
verify that the card correctly initiated and completed the voltage
switch. This is done by reading out the state of DATA0 line.
This patch implement support for reading out the state of the DATA0
line, so the MMC core code can correctly switch to 1.8V mode.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Make sure to clear HS400 configuration when resetting the SCC block.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add check to avoid touching the SCC tuning registers in case the IP
doesn't support them or if the support isn't in place yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Preinitialize the SD card signals regulator to 3.3V, which is the
default post-reset setting, to be sure the regulator is set to a
valid value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Configure the clock settings before reconfiguring any other IO settings.
This is required when the clock must be stopped before changing eg. the
pin configuration or any of the other properties of the bus. Running the
clock configuration first allows the MMC core to do just that.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
In case the controller performs card tuning, that is, sends MMC
command 19 or 21, silence possible CRC error warning prints. The
warnings are bound to happen, since the tuning will fail for some
settings while searching for the optimal configuration of the bus
and that is perfectly OK.
This patch passes around the MMC command structure and adds check
into tmio_sd_check_error() to avoid printing CRC error warning
when the tuning happens.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Properly handle return values and abort operations when they are
non-zero. This is a minor improvement, which fixes two remaining
unchecked return values.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400
modes all use 1.8V signaling, while all the legacy modes use 3.3V
signaling. While there are extra modes which use 1.2V signaling,
the existing hardware does not support those.
Simplify the pinmux such that 3.3V signaling implies legacy mode
pinmux and the rest implies UHS mode pinmux. This prevents the
massive case statement from growing further. Moreover, it fixes
an edge case where during SD 1.8V switch, the bus mode is still
set to default while the signaling is already set to 1.8V, which
results in an attempt to communicate with a 1.8V card using pins
in 3.3V mode and thus communication failure.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
When CONIFG_CLK is enabled, use uclass clk api to handle
the clock.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Add CONFIG_ARCH_IMX8 to use the 64bits support in usdhc driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.
The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The internal DMAC on Gen3 is 32bit only, limit the DMA address
range to 32bit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Pass the entire source data pointer to tmio_sd_addr_is_dmaable()
so we don't have to apply casts throughout the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Adds mmc_rpmb_route_frames() to route RPMB data frames from/to an
external entity.
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rk3188 works nicely with the rockchip mmc driver, so we just need
to add the different compatible for it - as used in the Linux kernel.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
While trying to enable the dw_mmc on rk3188 I managed to confuse
and hang the dw_mmc controller into not delivering further data.
The fifo state never became ready and the driver was iterating in
the while loop reading 0-byte packets forever.
So inspired by how other implementations handle this, check the fifo-
state beforhand and add a timeout to catch any glaring fifo issues
without hanging uboot altogether.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
With DM_GPIO and DM_MMC translating GPIO_ACTIVE_LOW, any boards
using the 'cd-invert' option will no longer need to do this. This
patch removes the support for 'invert' from the MMC driver.
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Fix warning over when !DM_GPIO]
Signed-off-by: Tom Rini <trini@konsulko.com>
The MMC card detect pin is connected to gpio127 on omap3_logic.
When setting up the pbias register for MMC, let's also enable
gpio_127 for the card detect. As part of the package deal,
gpio_126 and gpio_129 are also enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
When used with a device tree, this will extract the card detect
and write protect pins from the device tree and configure them
accordingly. This assumes the GPIO_ACTIVE_LOW/HIGH is supported
by da8xx_gpio.
Signed-off-by: Adam Ford <aford173@gmail.com>
With CONFIG_BLK becoming a requirement, the Davinci MMC driver
needs to be updated with DM_MMC support. Since SPL is tiny and
many boards do not support DM in SPL, this retains the backwards
compatibility for those boards who need to initialize MMC manually
in SPL.
Signed-off-by: Peter Howard <phoward@gme.net.au>
Signed-off-by: Adam Ford <aford173@gmail.com>
The getcd and getwp functions when DM_MMC is enabled are
assumming the DM_GPIO is enabled. In cases (like SPL) where
DM_GPIO may not be enabled, wrap these calls in an #ifdef
Signed-off-by: Adam Ford <aford173@gmail.com>
AM654 has an arasan sdhci controller and a mmc phy attached to it.
Add basic support for K3 specific arasan sdhci controller.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The strobe dll code is ported from Linux Kernel:
drivers/mmc/host/sdhci-esdhc-imx.c
The comments are from the above file,
"For HS400 eMMC, there is a data_strobe line. This signal is generated
by the device and used for data output and CRC status response output
in HS400 mode. The frequency of this signal follows the frequency of
CLK generated by host. The host receives the data which is aligned to the
edge of data_strobe line. Due to the time delay between CLK line and
data_strobe line, if the delay time is larger than one clock cycle,
then CLK and data_strobe line will be misaligned, read error shows up.
So when the CLK is higher than 100MHz, each clock cycle is short enough,
host should configure the delay target. "
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Add HS400 support.
Selecting HS400 needs first select HS200 according to spec, so use
a dedicated function for HS400.
Add HS400 related macros.
Remove the restriction of only using the low 6 bits of
EXT_CSD_CARD_TYPE, using all the 8 bits.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The dev_get_priv(dev) is used twice in the probe function.
Replace the second invocation with priv variable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add support for fetching the clock frequency both using the legacy
method in case clock framework is disabled as well as via the clock
framework if it is enabled. This allows for migration to the clock
framework on platforms which supports it while not breaking legacy
platforms. That said, the legacy method must be removed eventually.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
This commit enables support for Exynos Designware MMC driver based on DM.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
By convention for DM_MMC the host->priv is used to store struct udevice
*dev pointer.
Unfortunately, the legacy Exynos DW MMC code uses this field to
store pointer to dwmci_exynos_priv_data struct
Hence, we do need to get data in other way - namely by using container_of
when host pointer is present.
In this way the sdr_timing data is properly accessed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit prevents memory leak when this function is used with DM_MMC
as the struct dwmci_exynos_priv_data is already allocated by DM.
It is necessary for NON DM aware devices to allocate this struct first.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
As platform uses GPIOs for card detection, it's
simpler and more readable to use GPIO_ACTIVE_(LOW|HIGH)
in the gpio flags instead of using the cd-inverted
property.
Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add missing clk_free() call in case of failure
when enabling the clock.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Config flag CONFIG_BLK becomes mandatory, update arm_pl180_mmci
to support this config.
This driver is used by STM32Fx and by Vexpress platforms.
Only STM32Fx are DM ready. No DM code is isolated and will be
removed easily when wexpress will be converted to DM.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
the MMC2 come with the capability to do crypto by EMCE.
Add MMC support for H6. EMCE support is not added yet.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
This code is useful for testing the existance of devices that
do not have card detect capabilities. This breaks out the core
functionality and leaves the actual init logic and error reporting
in mmc_start_init().
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Correctly manage the SDMMC reset and card cycle power
to fully handle the power cycle added in the MMC uclass
and avoid issue with level-shifter with some uSDCARD.
3 states managed in driver:
1/ reset: SDMMC disable, signal HiZ
2/ power-cycle: SDMMC disable, signals drive to 0
3/ power-on: SDMMC enabled
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Commit dd27918c22 ("dm: mmc: sunxi: Add support for driver model")
only added the allwinner,sun5i-a13-mmc compatible string for this
driver. The DM initialisation code here also works with (at least) A10
and A20, so add the appropriate compatible strings as per Linux 4.17's
driver.
Tested on A10 Cubieboard and A20 pcDuino3 Nano with CONFIG_DM_MMC.
(A20 worked already, because sun7i-a20.dtsi specifies both the A13 and
A20 strings.)
Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Add support for loading U-Boot on the Broadcom 7445 SoC. This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Add code to reset all reset signals as in mmc DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Code around tuning_loop_counter variable expects to go below zero.
That's why this variable can't use unsigned type.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixes the mmc tuning command failures
when tuning pattern data needs to read back for
comparision against the expected bit pattern.
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add new compatible to the Uniphier SD driver for R8A77990 E3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds HS200 suuport for ZynqMP and enables
the same for ZC1751 DC1 board which has eMMC on it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The compatible string of ftsdc010_mci.c is different from
the mmc driver in Linux Kernel. Modify it for consistency.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
SDMMC_CMD_CPSMEN bit is wrongly check and set in
SDMMC_ARG register instead of SDMMC_CMD register.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Some minor fixes for the Raspberry Pi:
- Fix SD writes on new sdhost controller
- Sanitize default load addresses, allowing for better payload placement
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Merge tag 'signed-rpi-next' of git://github.com/agraf/u-boot
Patch queue for rpi - 2018-05-24
Some minor fixes for the Raspberry Pi:
- Fix SD writes on new sdhost controller
- Sanitize default load addresses, allowing for better payload placement
Convert CONFIG_SUPPORT_EMMC_RPMB to Kconfig. Split the command handling
from the underlying support and expose this through CMD_MMC_RPMB.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
The bcm2835 sdhost driver has a problem with "write multiple" commands.
It seems to boil down to the fact that the controller dislikes its FIFO
to get drained at the end of a block when a write multiple blocks command
is in flight.
The easy fix is to simply get rid of all the IRQ driven logic and make
the driver push as much data into the FIFO as it can. That way we never
drain and we never run into the problem.
Reported-by: Jan Leonhardt <jan@cyberdesigner.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
The check is necessary to avoid NULL pointer dereference.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Drop all the extra content from the MMC core, so that tiny MMC support
is really tiny, no fancy anything. That means the tiny MMC support does
only 1-bit transfers at default speed settings. Moreover, this patch
drops duplicate instance of struct mmc mmc_static, which wasted about
360 bytes. Furthermore, since MMC tiny supports only one controller
at all times, get rid of mallocating the ext csd backup and replace
it with static array. All in all, this patch saves ~4 kiB of bloat
from the MMC core, which on platforms with severe limitations can be
beneficial.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Fixup checkpatch.pl style warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds support of SD3.0 for ZynqMP.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch reads the capabilities register1 and update the host
caps accordingly for mmc layer usage. This patch mainly reads
for UHS capabilities inorder to support SD3.0.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support to invoke any platform specific tuning
and delay routines if available.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support to disable clock if clk_disable
was set and then enable or set clock if the clock was changed
or clock was disabled when clock needs to be enabled.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch changed the datatype of variable "start" from uint to ulong
to work properly on 64-bit machines as well. Also the return type of
get_timer() function is ulong.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
On a socfpga_cyclone5 based board the SD card, was never powered up. For
other dw_mmc based SoCs dwmci_probe() is called in the platform specific
probe(). It seems this call is missing for socfpga_dw_mmc.
With this change DWMCI_PWREN is set by dmwci_init().
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Add the debug message for checking the mmc clock status.
It's helpful to debug the controlling clock.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
mmc_set_clock() function has the disable argument as bool type.
When mmc_set_clock is called, it might be passed to "true" or "false".
But it's too confusion whether clock is enabled or disabled with only
"true" and "false".
To prevent the confusion, replace to MMC_CLK_ENABLE/DISABLE macro from
true/false.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
The 'SDHCI_QUIRK_NO_HISPD_BIT' is used wrong here. The purpose of this
quirk is to tell the sdhci-driver that the IP-core doesn't have a "high-
speed-enable" bit in its registers.
With this commit we change this to the correct quirk:
SDHCI_QUIRK_BROKEN_HISPD_MODE
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Some IP-core implementations of the SDHCI have different troubles on the
silicon where they are placed.
On ZYNQ platform for example Xilinx doesn't accept the hold timing of an
eMMC chip which operates in High-Speed mode and must be forced to
operate in non high-speed mode. To get rid of this
"SDHCI_QUIRK_BROKEN_HISPD_MODE" is introduced.
For more details about this refer to the Xilinx answer-recor #59999https://www.xilinx.com/support/answers/59999.html
This commit:
- doesn't set HISPD bit on the host-conroller
- reflects this fact within the host-controller capabilities
Upon this the layer above (mmc-driver) can setup the card correctly.
Otherwise the MMC card will be switched into high-speed mode and causes
possible timing violation on the host-controller side.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
sd_read_ssr returns 0, means no error.
Fixes: 5b2e72f32721484("mmc: read ssr only if MMC write support is enabled")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Throughput tests have shown the sunxi_mmc driver to take over 10s to
read 10MB from a fast eMMC device due to excessive delays in polling
loops.
This commit restructures the main polling loops to use get_timer(...)
to determine whether a (millisecond) timeout has expired. We choose
not to use the wait_bit function, as we don't need interruptability
with ctrl-c and have at least one case where two bits (one for an
error condition and another one for completion) need to be read and
using wait_bit would have not added to the clarity.
The observed speedup in testing on a A31 is greater than 10x (e.g. a
10MB write decreases from 9.302s to 0.884s).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Staticize the function since it's only used in mmc.c .
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Tom Rini <trini@konsulko.com>
The size of SPL is hitting the limit (64KB) for uniphier_v7_defconfig.
When booting from SD/eMMC, obviously its clock has been properly set up
by the boot ROM. Acutually, no need to re-initialize the clock in SPL.
Using a clock driver would generalize the SoC specific code, but
solving the memory footprint problem would win.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
I need to differentiate the clock handling for uniphier-sd. Move it
to each driver's probe function from the tmio common code so that
renesas-sdhi will not be affected.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Odroid C2 fails to read from mmc with U-Boot v2018.03.
The change avoids a division by zero.
The fix was suggested by Jaehoon in
https://lists.denx.de/pipermail/u-boot/2018-January/318577.html
Reported-by: Vagrant Cascadian <vagrant@debian.org>
Suggested-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where
PLL5 is used, with clock rates respectively 600MHz and 768MHz.
Thus there are different phase degree steps - 24 for the kernel and
30 for u-boot.
In the kernel driver the phase is set 90 deg for output and 120 for
sample. Dividing by 30 will result values 3 and 4. Those are the
values set in the u-boot driver.
However, the condition defining delays is wrong. MMC core driver
requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but
phase is set 30 deg for output and 120 deg for sample.
Apparently this works for most cards.
On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains
about it. Maybe there is other boards with similar problem?
So the fix is to match delays for both u-boot and kernel.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add MMC DM and DT probing support into the SH MMCIF driver.
This patch abstracts out the common bits of the send command
and set ios functions, so they can be used both by DM and non
DM setups and adds the DM probe support.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
The mv_sdhci driver was not zeroing the sdhci_host structure it
allocates causing random access violations in parts of the mmc core
where the "ops" member pointers are checked and called if not NULL.
Signed-off-by: Matt Pelland <mpelland@starry.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Synchronize the naming with Linux, call the common code TMIO.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The IP requires some time to recuperate after the IO pin
properties were changed. Add a delay to assure this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Fix minor rebase omission, the else was missing which triggered
two accesses to the register on 64bit variant of the IP.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Make sure to wait for the command to complete altogether, including
the trailing 8 clock cycles. This prevents the driver for accidentally
writing the CMD register too fast before the previous command fully
completed.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The HOST_MODE register must be set to 0 when the IP is operated in 16bit
mode, otherwise 16bit access to the data FIFO may fail.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
There are only a few registerse used in the 16bit mode which are
32bit internally. Special-case only those in the IO accessors and
always write both halves. Any other register access is protected
from accidentally overwriting neighboring register.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Export the matsu_sd_{read,write}l() common register access
functions, so that they can be used by other drivers sharing
the common code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Factor out the regulator handling into set_ios and add support for
selecting pin configuration based on the voltage to support UHS modes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Handle the controller version even if quirks are set. The controller in
Renesas Gen3 SoCs does provide the version register, which indicates a
controller v10 and the controller does support internal DMA and /1024
divider.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Handle bus width 0 as 1-bit bus to assure valid content of
MATSU_SD_OPTION register WIDTH field.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The DMA READ completion flag position differs on Socionext and Renesas
SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add a quirk to identify that the controller is Renesas RCar variant
of the Matsushita SD IP and another quirk indicating it can support
Renesas RCar HS200/HS400/SDR104 modes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Drop the ad-hoc DT caps parsing in favor of common framework function.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants
of the IP. There is no DT property which allows discerning those,
so what Linux does is it checks the size of the register area and
if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle
the distinction the same way.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Certain instances of the SD IP require more elaborate digging
in the DT to figure out which variant of the SD IP is in use.
Allow explicit passing of the quirks into the probe function.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add support for 16bit mutation of the Matsushita SD IP. Since some
registers are internally 32bit, the matsu_sd_{read,write}l() has
to special-case this 16bit variant a bit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Drop useless check in matsu_sd_{read,write}q(), this is only ever
called to read the data from FIFO and only when 64bit variant of
the block is used anyway.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add macros to generate the FIFO accessors, since the code is almost
the same with only minor differences. This is done in preparation
for adding 16bit variant of the IP.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add Kconfig entry for the Renesas SDHI variant of the controller
and split the Makefile entries accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Factor out common code from the uniphier SD driver, change the prefix
of the functions from uniphier_sd_ to matsu_sd_ and create separate
renesas-sdhi.c driver. Thus far, all the code is still compiled when
CONFIG_UNIPHIER_MMC is selected and there is no functional change.
This patch is a preparation for further split of the SoC specific
parts of the Matsushita SD driver, used both on Uniphier and R-Car.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
In raspberrypi-firmware 7fdcd00e00a42a1c91e8bd6f5eb8352fe9358557 and
later start.elf now sets the EMMC clock to 200 MHz.
According to Phil Elwell in
https://github.com/raspberrypi/firmware/issues/953
the SDHost controller shares the core/VPU clock and doesn't use
the EMMC clock.
Use the core clock id when determining the frequency to allow
U-Boot to work with recent versions of raspberrypi-firmware.
Otherwise U-Boot hangs at:
U-Boot 2018.03 (Mar 14 2018 - 20:36:00 +1100)
DRAM: 948 MiB
RPI 3 Model B (0xa02082)
MMC: mmc@7e202000: 0, sdhci@7e300000: 1
Loading Environment from FAT...
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Use dm_pci_map_bar function for BAR mapping. This has the advantage
of clearing BAR flags and and only accepting mapped memory.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
nsd32_mmc was created to support ftsdc010 dm.
It is not necessary to separate both, so merge it
to ftsdc010.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Convert CONFIG_FTSDC010_SDIO to Kconfig.
So CONFIG_FTSDC010_SDIO can also be
removed from config_whitelist.txt.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Only three defconfig(adp-ag101p_defconfig,
adp-ae3xx_defconfig, nx25-ae250_defconfig)
set CONFIG_FTSDC010=y. And they all also
enable CONFIG_DM_MMC. So the non-dm code
of ftsdc010 can be dropped now.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
ftsdc010 dm driver has been disable High-Speed mode
as default to work around Andes AE3XX platform's problem,
because of it does not support High-Speed mode in
commit id 73cd56b2df.
But other platforms or SoCs maybe support this function.
So High-Speed mode can be enabled from dts with
cap-mmc-highspeed or cap-sd-highspeed property.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
The Rockchip-specific SDHCI wrapper does not process the 'bus-width'
property in the SDHCI node. Consequently, the bus is always kept in
4bit mode, even if 8bit wide operation is available, supported and
requested in the DTS.
This change adds processing of the 'bus-width' property and sets the
host capability flag for an 8bit wide bus, if set to 8. As the logic
in sdhci.c does not support clearing the 4bit capability, we assume
that 4bit operation is always supported.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This patch adds "st,pin-ckin" support to activate sdmmc_ckin feature.
When using an external driver (a voltage switch transceiver),
it's advised to select SDMMC_CKIN feedback clock input to sample
the received data.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The hardware flow control functionality is used to avoid
FIFO underrun (TX mode) and overrun (RX mode) errors.
The behavior is to stop SDMMC_CK during data transfer and
freeze the SDMMC state machines.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
With CONFIG_DM_MMC the BananaPi does not detect SD cards.
The sunxi device trees use the cd-inverted property to indicate that
the card detect is inverted.
This property is documented in Linux kernel devicetree/bindings/mmc/mmc.txt
The property is not marked as deprecated.
A similar patch was posted by Tuomas but is in status "Changes Requested".
https://patchwork.ozlabs.org/patch/850377/
This patch is a stripped down version of his patch.
Suggested-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MIN_FREQ
and enabled it in respective defconfig.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ
and enabled it in respective defconfig.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mmc_of_parse() doesn't set a default value if none is available in DT.
In that case, use a default 52MHz clock rate.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Some platforms don't have ADMA controllers. For those platforms, compiling
it out reduces the size of the binary by about 600 bytes.
Leaving the support in doesn't break things as the driver checks at runtime
if the ADMA2 controller is present.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This reduces the size of the binary by about 196 bytes.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The area for struct mmc can be allocated dynamically. It greatly reduces
the size of struct omap_hsmmc_plat. This is useful in cases where the board
level code declares one or two struct omap_hsmmc_plat because it doesn't
use the Driver Model.
This saves around 740 bytes for the am335x_evm SPL.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
MMC card with EXT_CSD_REV value 9 will trigger off-by-one
bug while accessing mmc_versions array. The patch fix that.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Add DT compatible strings for RCar Gen2 SoCs, so that this driver
can bind with them. Unlike Gen3, which uses 64bit FIFO, the Gen2
uses 16bit FIFO.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
If some configs are disabled, number of freqs array will not assigned to
correct value with bus_mode.
Synchornize the ordering with enum bus_mode in mmc.h.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
When using omap_hsmmc without the device model then the allocation
of mmc->priv ends up uninitialised.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
The correspondence between mmc versions as used in u-boot and the version
numbers reported in register EXT_CSD_REV is wrong for versions above and
including MMC_VERSION_4_41. All those versions were shifted by one:
real 4.5 hardware appeared to be MMC_VERSION_5_0.
Fix this by adding the missing version in the correspondence table.
Reported-by: eil Eilmsteiner Heribert <eil@keba.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
