mirror of
https://github.com/AsahiLinux/u-boot
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mmc: ftsdc010: Merge nds32_mmc to ftsdc010
nsd32_mmc was created to support ftsdc010 dm. It is not necessary to separate both, so merge it to ftsdc010. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
This commit is contained in:
Rick Chen
Andes
parent
095c9f35d5
commit
bf9ba4dbb0
5 changed files with 133 additions and 165 deletions
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@ -523,13 +523,6 @@ config STM32_SDMMC2
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If you have a board based on such a SoC and with a SD/MMC slot,
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say Y or M here.
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config MMC_NDS32
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bool "Andestech SD/MMC controller support"
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depends on DM_MMC && OF_CONTROL && BLK && FTSDC010
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help
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This enables support for the Andestech SD/MMM controller, which is
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based on Faraday IP.
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config FTSDC010
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bool "Ftsdc010 SD/MMC controller Support"
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help
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@ -42,7 +42,6 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
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obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
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obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
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obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
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obj-$(CONFIG_MMC_NDS32) += nds32_mmc.o
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# SDHCI
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obj-$(CONFIG_MMC_SDHCI) += sdhci.o
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@ -4,23 +4,63 @@
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* (C) Copyright 2010 Faraday Technology
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* Dante Su <dantesu@faraday-tech.com>
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*
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* Copyright 2018 Andes Technology, Inc.
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* Author: Rick Chen (rick@andestech.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <malloc.h>
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#include <part.h>
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#include <mmc.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <asm/byteorder.h>
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#include <faraday/ftsdc010.h>
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#include "ftsdc010_mci.h"
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <mapmem.h>
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#include <pwrseq.h>
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#include <syscon.h>
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#include <linux/err.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
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#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct ftsdc010 {
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fdt32_t bus_width;
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bool cap_mmc_highspeed;
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bool cap_sd_highspeed;
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fdt32_t clock_freq_min_max[2];
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struct phandle_2_cell clocks[4];
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fdt32_t fifo_depth;
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fdt32_t reg[2];
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};
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#endif
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struct ftsdc010_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct ftsdc010 dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct ftsdc_priv {
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struct clk clk;
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struct ftsdc010_chip chip;
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int fifo_depth;
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bool fifo_mode;
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u32 minmax[2];
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};
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static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
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{
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struct ftsdc010_chip *chip = mmc->priv;
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@ -316,20 +356,20 @@ static int ftsdc010_init(struct mmc *mmc)
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return 0;
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}
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int ftsdc010_probe(struct udevice *dev)
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static int ftsdc010_probe(struct udevice *dev)
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{
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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return ftsdc010_init(mmc);
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}
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const struct dm_mmc_ops dm_ftsdc010_ops = {
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const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
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.send_cmd = ftsdc010_request,
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.set_ios = ftsdc010_set_ios,
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.get_cd = ftsdc010_get_cd,
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.get_wp = ftsdc010_get_wp,
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};
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void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
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static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
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uint caps, u32 max_clk, u32 min_clk)
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{
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cfg->name = name;
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@ -348,7 +388,94 @@ void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
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cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
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}
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int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
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static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
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{
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return mmc_bind(dev, mmc, cfg);
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct ftsdc_priv *priv = dev_get_priv(dev);
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struct ftsdc010_chip *chip = &priv->chip;
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chip->name = dev->name;
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chip->ioaddr = (void *)devfdt_get_addr(dev);
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chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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chip->priv = dev;
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priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"fifo-depth", 0);
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priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
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"fifo-mode");
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if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
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"clock-freq-min-max", priv->minmax, 2)) {
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int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"max-frequency", -EINVAL);
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if (val < 0)
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return val;
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priv->minmax[0] = 400000; /* 400 kHz */
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priv->minmax[1] = val;
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} else {
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debug("%s: 'clock-freq-min-max' property was deprecated.\n",
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__func__);
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}
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#endif
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chip->sclk = priv->minmax[1];
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chip->regs = chip->ioaddr;
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return 0;
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}
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static int ftsdc010_mmc_probe(struct udevice *dev)
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{
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struct ftsdc010_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct ftsdc_priv *priv = dev_get_priv(dev);
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struct ftsdc010_chip *chip = &priv->chip;
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struct udevice *pwr_dev __maybe_unused;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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int ret;
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struct ftsdc010 *dtplat = &plat->dtplat;
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chip->name = dev->name;
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chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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chip->buswidth = dtplat->bus_width;
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chip->priv = dev;
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chip->dev_index = 1;
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memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
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ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
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if (ret < 0)
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return ret;
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#endif
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if (dev_read_bool(dev, "cap-mmc-highspeed") || \
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dev_read_bool(dev, "cap-sd-highspeed"))
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chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
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ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
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priv->minmax[1] , priv->minmax[0]);
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chip->mmc = &plat->mmc;
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chip->mmc->priv = &priv->chip;
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chip->mmc->dev = dev;
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upriv->mmc = chip->mmc;
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return ftsdc010_probe(dev);
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}
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int ftsdc010_mmc_bind(struct udevice *dev)
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{
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struct ftsdc010_plat *plat = dev_get_platdata(dev);
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return mmc_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id ftsdc010_mmc_ids[] = {
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{ .compatible = "andestech,atsdc010" },
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{ }
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};
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U_BOOT_DRIVER(ftsdc010_mmc) = {
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.name = "ftsdc010_mmc",
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.id = UCLASS_MMC,
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.of_match = ftsdc010_mmc_ids,
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.ofdata_to_platdata = ftsdc010_mmc_ofdata_to_platdata,
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.ops = &dm_ftsdc010_mmc_ops,
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.bind = ftsdc010_mmc_bind,
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.probe = ftsdc010_mmc_probe,
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.priv_auto_alloc_size = sizeof(struct ftsdc_priv),
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.platdata_auto_alloc_size = sizeof(struct ftsdc010_plat),
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};
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@ -35,14 +35,4 @@ struct ftsdc010_chip {
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bool fifo_mode;
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};
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#ifdef CONFIG_DM_MMC
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/* Export the operations to drivers */
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int ftsdc010_probe(struct udevice *dev);
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extern const struct dm_mmc_ops dm_ftsdc010_ops;
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#endif
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void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
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uint caps, u32 max_clk, u32 min_clk);
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int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
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#endif /* __FTSDC010_MCI_H */
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@ -1,141 +0,0 @@
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/*
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* Andestech ATFSDC010 SD/MMC driver
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*
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* (C) Copyright 2017
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* Rick Chen, NDS32 Software Engineering, rick@andestech.com
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <mapmem.h>
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#include <mmc.h>
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#include <pwrseq.h>
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#include <syscon.h>
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#include <linux/err.h>
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#include <faraday/ftsdc010.h>
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#include "ftsdc010_mci.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct nds_mmc {
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fdt32_t bus_width;
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bool cap_mmc_highspeed;
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bool cap_sd_highspeed;
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fdt32_t clock_freq_min_max[2];
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struct phandle_2_cell clocks[4];
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fdt32_t fifo_depth;
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fdt32_t reg[2];
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};
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#endif
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struct nds_mmc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct nds_mmc dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct ftsdc_priv {
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struct clk clk;
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struct ftsdc010_chip chip;
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int fifo_depth;
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bool fifo_mode;
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u32 minmax[2];
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};
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static int nds32_mmc_ofdata_to_platdata(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct ftsdc_priv *priv = dev_get_priv(dev);
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struct ftsdc010_chip *chip = &priv->chip;
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chip->name = dev->name;
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chip->ioaddr = (void *)devfdt_get_addr(dev);
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chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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chip->priv = dev;
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priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"fifo-depth", 0);
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priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
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"fifo-mode");
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if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
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"clock-freq-min-max", priv->minmax, 2)) {
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int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"max-frequency", -EINVAL);
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if (val < 0)
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return val;
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priv->minmax[0] = 400000; /* 400 kHz */
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priv->minmax[1] = val;
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} else {
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debug("%s: 'clock-freq-min-max' property was deprecated.\n",
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__func__);
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}
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#endif
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chip->sclk = priv->minmax[1];
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chip->regs = chip->ioaddr;
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return 0;
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}
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static int nds32_mmc_probe(struct udevice *dev)
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{
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struct nds_mmc_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct ftsdc_priv *priv = dev_get_priv(dev);
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struct ftsdc010_chip *chip = &priv->chip;
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struct udevice *pwr_dev __maybe_unused;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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int ret;
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struct nds_mmc *dtplat = &plat->dtplat;
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chip->name = dev->name;
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chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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chip->buswidth = dtplat->bus_width;
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chip->priv = dev;
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chip->dev_index = 1;
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memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
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ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
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if (ret < 0)
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return ret;
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#endif
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if (dev_read_bool(dev, "cap-mmc-highspeed") || \
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dev_read_bool(dev, "cap-sd-highspeed"))
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chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
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ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
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priv->minmax[1] , priv->minmax[0]);
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chip->mmc = &plat->mmc;
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chip->mmc->priv = &priv->chip;
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chip->mmc->dev = dev;
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upriv->mmc = chip->mmc;
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return ftsdc010_probe(dev);
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}
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static int nds32_mmc_bind(struct udevice *dev)
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{
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struct nds_mmc_plat *plat = dev_get_platdata(dev);
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return ftsdc010_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id nds32_mmc_ids[] = {
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{ .compatible = "andestech,atsdc010" },
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{ }
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};
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U_BOOT_DRIVER(nds32_mmc_drv) = {
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.name = "nds32_mmc",
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.id = UCLASS_MMC,
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.of_match = nds32_mmc_ids,
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.ofdata_to_platdata = nds32_mmc_ofdata_to_platdata,
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.ops = &dm_ftsdc010_ops,
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.bind = nds32_mmc_bind,
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.probe = nds32_mmc_probe,
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.priv_auto_alloc_size = sizeof(struct ftsdc_priv),
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.platdata_auto_alloc_size = sizeof(struct nds_mmc_plat),
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};
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