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mmc: tmio: renesas: Add 1uS delay after DMA completion on older IPs

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The internal DMAC asserts DMA transfer end bit too early on older
version of the TMIO IPs which use bit 17 for DTRAEND. Add 1uS
delay after the completion of DMA transfer and before invalidating
the cache to let the DMAC fully complete the transfer. Otherwise,
it could happen that the last few bytes of a transferred data are
not available.

A test case to trigger this behavior is the following command, ran
on the U-Boot command line, with Sandisk 16 GiB UHS-I card inserted
into SDHI slot 0 and with first partition being of type FAT:
=> while true ; do mmc rescan ; fstype mmc 0:1 ; done

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Marek Vasut 2019-01-11 23:38:07 +01:00 committed by Marek Vasut
parent 992bcf4f27
commit cbbe69483e
1 changed files with 3 additions and 0 deletions
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3
drivers/mmc/tmio-common.c
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@ -367,6 +367,9 @@ static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
udelay(1);
__dma_unmap_single(dma_addr, len, dir);
return ret;