Commit graph

21485 commits

Author SHA1 Message Date
Tom Rini
7675a526e0 Convert CONFIG_SYS_UNIFY_CACHE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_UNIFY_CACHE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
dea25842ab usb: ohci-hcd: Remove some unused legacy code
At this point, the only user of ohci-hcd that also uses PCI is using DM,
so we can drop CONFIG_PCI_OHCI* usage.  No platforms set either of
CONFIG_SYS_USB_OHCI_BOARD_INIT or CONFIG_SYS_USB_OHCI_CPU_INIT so those
hooks can be removed as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
cd6a45a41f Convert CONFIG_USB_OHCI_NEW et al to Kconfig
This converts the following to Kconfig:
    CONFIG_SYS_OHCI_SWAP_REG_ACCESS
    CONFIG_SYS_USB_OHCI_CPU_INIT
    CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
    CONFIG_SYS_USB_OHCI_SLOT_NAME
    CONFIG_USB_ATMEL
    CONFIG_USB_ATMEL_CLK_SEL_PLLB
    CONFIG_USB_ATMEL_CLK_SEL_UPLL
    CONFIG_USB_OHCI_LPC32XX
    CONFIG_USB_OHCI_NEW

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
b340199f82 spl: Ensure all SPL symbols in Kconfig have some SPL dependency
Tighten up symbol dependencies in a number of places.  Ensure that a SPL
specific option has at least a direct dependency on SPL.  In places
where it's clear that we depend on something more specific, use that
dependency instead.  This means in a very small number of places we can
drop redundant dependencies.

Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Tom Rini
abba59f115 Convert CONFIG_USB_XHCI_EXYNOS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_XHCI_EXYNOS
   CONFIG_USB_EHCI_EXYNOS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-07 09:29:08 -04:00
Jim Liu
847505a3ee misc: nuvoton: Add host interface configuration driver
add nuvoton BMC npcm750 host configuration driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-07-06 18:34:16 -04:00
Joel Stanley
a7d606ff61 mmc/aspeed: Enable controller clocks
Request and enable the controller level clocks.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
66900bc254 mmc/aspeed: Probe from controller
The Aspeed SDHCI controller is arranged with some shared control
registers, followed by one or two sets of actual SDHCI registers.

Adjust the driver to probe this controller device first. The driver then
wants to iterate over the child nodes to probe the SDHCI proper:

    ofnode node;

    dev_for_each_subnode(node, parent) {
    	struct udevice *dev;
    	int ret;

    	ret = device_bind_driver_to_node(parent, "aspeed_sdhci",
    					 ofnode_get_name(node),
    					 node, &dev);
    	if (ret)
    		return ret;
    }

However if we did this the sdhci driver would probe twice; once
"naturally" from the device tree and a second time due to this code.

Instead of doing this we can rely on the probe order, where the
controller will be set up before the sdhci devices. A better solution is
preferred.

Select MISC as the controller driver is implemented as a misc device.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
f49a7a160d mmc/aspeed: Add debuging for clock probe failures
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
50204533dc clk/ast2500: Add SD clock
In order to use the clock from the sdhci driver, add the SD clock.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
85bb3a4eee clk/ast2600: Adjust eMMC clock names
Adjust clock to stay compatible with those used by the Linux kernel
device tree.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
67e20f9d65 clk/aspeed: Add debug message when clock fails
A common message across platforms that prints the clock number.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
50b23b1c5b i2c/aspeed: Add AST2600 compatible
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
453fe1eece i2c/aspeed: Fix reset control
The reset control was written for the ast2500 and directly programs the
clocking register.

So we can share the code with other SoC generations use the reset device
to deassert the I2C reset line.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
0a8bd97f88 reset/aspeed: Implement status callback
The I2C driver shares a reset line between buses, so allow it to test
the state of the reset line before resetting it.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Bryan Brattlof
10c8bafbc3 soc: soc_ti_k3: identify j7200 SR2.0 SoCs
Anytime a new revision of a chip is produced, Texas Instruments
will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID
register by one. Typically this will be decoded as SR1.0 -> SR2.0 ...
however a few TI SoCs do not follow this convention.

Rather than defining a revision string array for each SoC, use a
default revision string array for all TI SoCs that continue to follow
the typical 1.0 -> 2.0 revision scheme.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-07-06 14:30:51 -04:00
Jim Liu
fdd08f896b phy: nuvoton: add NPCM7xx phy control driver
add BMC NPCM750 phy control driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-07-06 14:30:51 -04:00
Vignesh Raghavendra
e4b4501ede firmware: ti_sci_static_data: Make file board agnostic
Static DMA channel data for R5 SPL is mostly board agnostic so use SOC
configs instead of EVM specific config to ease adding new board support.

Drop J7200 EVM specific settings as its same as J721e

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2022-07-06 14:30:08 -04:00
Tom Rini
6bb74fe19b Convert CONFIG_SYS_FSL_PCI_VER_3_X to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_PCI_VER_3_X

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
363397ae1a Convert CONFIG_PCI_MSC01 to Kconfig
This converts the following to Kconfig:
   CONFIG_PCI_MSC01

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
31a8f5545e Convert CONFIG_SH7751_PCI to Kconfig
This converts the following to Kconfig:
   CONFIG_SH7751_PCI

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
e58eebb514 Convert CONFIG_PCI_CONFIG_HOST_BRIDGE to Kconfig
This converts the following to Kconfig:
   CONFIG_PCI_CONFIG_HOST_BRIDGE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00
Tom Rini
bf2c48fa1a Convert CONFIG_PCI_GT64120 to Kconfig
This converts the following to Kconfig:
   CONFIG_PCI_GT64120

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00
Tom Rini
f27bca4c27 Convert CONFIG_PCI_SCAN_SHOW to Kconfig
This converts the following to Kconfig:
   CONFIG_PCI_SCAN_SHOW

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00
Tom Rini
4e7860288c pci: Remove pci_sh4 and related defines.
This driver is not enabled anywhere, remove it.  Also remove definitions
of symbols only used in this driver, on platforms that did not enable
it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00
Tom Rini
4547a1bc92 Convert CONFIG_PCIE_IMX to Kconfig
This converts the following to Kconfig:
   CONFIG_PCIE_IMX

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00
Tom Rini
c9f85187e2 Convert CONFIG_SYS_FSL_SEC_MON et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_SEC_MON
   CONFIG_SYS_FSL_SEC_MON_BE
   CONFIG_SYS_FSL_SEC_MON_LE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:00 -04:00
Tom Rini
7e7d04aecb Convert CONFIG_ESDHC_DETECT_QUIRK to Kconfig
This converts the following to Kconfig:
   CONFIG_ESDHC_DETECT_QUIRK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:46 -04:00
Tom Rini
c24e8e2bb3 Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_DDR_RAW_TIMING

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
bca4509d57 Convert CONFIG_SYS_SPD_BUS_NUM to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_SPD_BUS_NUM

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
b68ba0e0eb Convert CONFIG_USB_GADGET_DWC2_OTG_PHY to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_GADGET_DWC2_OTG_PHY

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
ddd39d0cc1 Convert CONFIG_SAMSUNG_ONENAND to Kconfig
This converts the following to Kconfig:
   CONFIG_SAMSUNG_ONENAND

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-07-05 17:03:01 -04:00
Tom Rini
de0a732915 Rename CONFIG_PWM to CONFIG_PWM_S5P and move to Kconfig
We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to
Kconfig.  Given the usage of CONFIG_PWM_NX, we have that select this new
symbol.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-07-05 17:03:01 -04:00
Tom Rini
140f0aa0de nxp: Cleanup some emulator related options.
- Drop the emulator CONFIG test from include/configs/ls1088ardb.h
- Migrate CONFIG_SYS_FSL_DDR_EMU to a select'able option in
  drivers/ddr/fsl/Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
0285455d90 watchdog: designware: Make this depend on WDT
As this driver can dynamically determine the values set in
CONFIG_DW_WDT_BASE when using WDT, so make this depend on WDT rather
than migrate CONFIG_DW_WDT_BASE to Kconfig.

Cc: Chee Tien Fong <tien.fong.chee@intel.com>
Cc: Chin-Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinh.nguyen@intel.com>
Cc: Holger Brunck <holger.brunck@hitachienergy.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Stefan Roese <sr@denx.de>
Cc: hee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-07-05 17:03:01 -04:00
Tom Rini
69a2bb6321 net: designware: Rename CONFIG_DW_GMAC_DEFAULT_DMA_PBL to GMAC_DEFAULT_DMA_PBL
This value is always used at the default, rename it for now.  This
likely should come from the device tree if non-default, moving forward.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
89d888ed6d Convert CONFIG_DW_ALTDESCRIPTOR to Kconfig
This converts the following to Kconfig:
   CONFIG_DW_ALTDESCRIPTOR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Andre Przywara
9125b4b021 usb: host: ehci-generic: Fix error check
Commit 81755b8c20 ("usb: host: ehci-generic: Make resets and clocks
optional") improved the error check to cover the reset property being
optional. However this was using the wrong error variable for the
check, so would now never fail.

Use the correct error variable for checking the result of
reset_get_bulk(), to actually report genuine errors.

Fixes: 81755b8c20 ("usb: host: ehci-generic: Make resets and clocks optional")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-04 08:00:36 -04:00
Pali Rohár
712a172499 mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not selected ecc.mode
ecc.mode is set to 0 (aliased to NAND_ECC_NONE) either when function
nand_scan_ident() has not selected ecc.mode or when it selected it to none
ecc mode.

Distinguish between these two states by checking of node property
"nand-ecc-mode" which function nand_scan_ident() uses for filling ecc.mode.

This change fixes usage of none ecc mode if it is specified in DTS file.

Fixes: c9ea9019c5 ("mtd: rawnand: fsl_elbc: Use ECC configuration from device tree")
Signed-off-by: Pali Rohár <pali@kernel.org>
2022-07-03 15:13:51 +08:00
Tom Rini
9fcc2fb3fe Merge commit 'ef5ba2cef4a08b68caaa9215fcac142d3025bbf7' of https://github.com/tienfong/uboot_mainline 2022-07-01 09:14:32 -04:00
Teik Heng Chong
ef5ba2cef4 drivers: clk: Update license for Intel N5X device
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel,
update the license to use both GPL2.0 and BSD-3 Clause because this
copy of code may used for open source and internal project.

Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-07-01 15:00:39 +08:00
Paweł Anikiel
5c53d9c0d9 socfpga: arria10: Wait for fifo empty after writing bitstream
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
8b1eee3730 socfpga: arria10: Improve bitstream loading speed
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):

 * Change the size of the first fs read, so that all the subsequent
   reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
   This value was chosen so that in subsequent reads the fat fs driver
   doesn't have to allocate a temporary buffer in get_contents
   (assuming 8KiB clusters).

 * Change the buffer size to a larger value when reading to ddr
   (but not too large, because large transfers cause a stack overflow
   in the dwmmc driver).

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
9ebca7095b sysreset: socfpga: Use parent device for reading base address
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
73d88cf971 misc: atsha204a: Increase wake delay by tWHI
From the ATSHA204A datasheet (document DS40002025A):

Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.

tWHI value can be found in table 7-2.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Tom Rini
33938636f0 Merge tag 'u-boot-rockchip-20220630' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Fix for rk3328 nonopi-r2s boot env;
- Fix for rk8xx pmic boot on power plug-in;
- Fix for tee.bin support in fit image;
- rk3288 board dts update or fix;
- Some rk3399 board fix;
2022-06-30 22:36:41 -04:00
Tom Rini
284c1a9b4b First set of u-boot-at91 features for the 2022.10 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmK9nEUcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyEu0B/4v1EQOMBL+VXns8Ipo
 Xeq+RDUX/24XcB5s6sTcNlWzvYuX6Z7DCGJ0loK5JxelrOy+YNkRbTRMom1eW9Kn
 9dmKa0bcO7auJEww3Nln1IFyx+FXQFGR1V3g1U4535l8b7urTioIK0MUSrG/GLpe
 Rlbh31GAYtrGvl06W1F7mwhg7/0AT8IhUFaY9G7s7gKA5muGQQ7ED4nKVoZPeTAl
 lrQ/Ecym1ND7aOhd/vuEBtgoGxDWzwf8piT8qykJluJKzBV1Hic0RXCNBmtrTORz
 b1GOOpRUgcnTv9U8j4PRyYGKDnmS2OmV2AwL8+V9UJfJgQrkcRlbgpCysIPmMBzo
 YPRt
 =D79P
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-2022.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2022.10 cycle:

This feature set includes mostly fixes and alignments: DT alignment with
Linux for sama7g5, removal of invalid eeprom compatibles, removal of
extra debug_uart_init calls for all at91 boards, support for pio4 driver
pioE bank, and other minor fixes and enhancements for sam9x60 and
sama5d2_icp boards.
2022-06-30 15:21:52 -04:00
Tom Rini
c5e7003aa8 Versal QSPI/OSPI changes for v2022.10
- Add new flash types
 - Add cadence ospi driver for Xilinx Versal
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYr2hGQAKCRDKSWXLKUoM
 IabDAJ9oyJ+Z84pDMbegg3uiFp2hQZfx+wCfaX1PXklNCaHIcnnq3ZZAMV2SYds=
 =lU1M
 -----END PGP SIGNATURE-----

Merge tag 'versal-qspi-for-v2022.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Versal QSPI/OSPI changes for v2022.10

- Add new flash types
- Add cadence ospi driver for Xilinx Versal
2022-06-30 09:32:15 -04:00
Mihai Sain
c1cadac793 gpio: atmel_pio4: add support for PIO_PORTE
Add support for gpio PORT E, which is available on e.g. sama7g5 SoC.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-06-30 15:49:00 +03:00
T Karthik Reddy
2c27fdc070 spi: cadence-qspi: Fix programming ospi flash speed
When the requested flash speed is 0, the baudrate division for the
requested speed causing drop in the performance. So set the ospi flash
to operate at max frequency when requested speed is zero.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-6-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 16:00:31 +02:00
T Karthik Reddy
248fe9f302 spi: cadence_qspi: Enable apb linear mode for apb read & write operations
On versal platform, enable apb linear mode for apb read and write
execute operations amd disable it when using dma reads. This is done by
xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled,
else we use direct raw reads and writes in case of mini U-Boot.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 16:00:31 +02:00
T Karthik Reddy
bf8dae5fcf spi: cadence-qspi: reset qspi flash for versal platform
When flash operated at non default mode like DDR, flash need to be reset
to operate in SDR mode to read flash ids by spi-nor framework. Reset the
flash to the default state before using the flash. This reset is handled
by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we
do raw read and write access by the registers.
Versal platform utilizes spi calibration for read delay programming, so
incase by default read delay property is set in DT. We make sure not to
use read delay from DT by overwriting read_delay with -1.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 16:00:31 +02:00
T Karthik Reddy
cf553bf20e arm64: versal: Add versal specific cadence ospi driver
Add support for cadence ospi driver for Versal platform. This driver
provides support for DMA read operation which utilizes cadence qspi
driver.
If "cdns,is-dma" DT property is specified use dma for read operation
from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in
cadence_ospi_versal driver add a weak function defination in
cadence_qspi driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 15:58:48 +02:00
T Karthik Reddy
1e2b8139d9 spi: cadence-qspi: move cadence qspi macros to header file
Move all the cadence macros from cadence_qspi_apb.c to cadence_qspi.h
file.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 15:58:48 +02:00
Ashok Reddy Soma
baef13ec9d mtd: spi-nor-ids: Add support for flashes tested by xilinx
Add support for various flashes from below manufacturers which are tested
by xilinx for years.

EON:
	en25q128b
GIGA:
	gd25lx256e
ISSI:
	is25lp008
	is25lp016
	is25lp01g
	is25wp008
	is25wp016
	is25wp01g
	is25wx256
MACRONIX:
	mx25u51245f
	mx66u1g45g
	mx66l2g45g
MICRON:
	mt35xl512aba
	mt35xu01g
SPANSION:
	s70fs01gs_256k
SST:
	sst26wf016b
WINBOND:
	w25q16dw
	w25q16jv
	w25q512jv
	w25q32bv
	w25h02jv

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1653455832-14763-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-29 15:32:48 +02:00
Andrea Scian
05dcb5be50 mtd: mxs_nand_spl: fix nand_command protocol violation
mxs_nand_command() implementation assume that it's working with a
LP NAND, which is a common case nowadays and thus uses two bytes
for column address.

However this is wrong for NAND_CMD_READID and NAND_CMD_PARAM, which
expects only one byte of column address, even for LP NANDs.
This leads to ONFI detection problem with some NAND manufacturer (like
Winbond) but not with others (like Samsung and Spansion)

We fix this with a simple workaround to avoid the 2nd byte column address
for those two commands.

Also align the code with nand_base to support 16 bit devices.

Tested on an iMX6SX device with:
* Winbond W29N04GVSIAA
* Spansion S34ML04G100TF100
* Samsung K9F4G08U00

Tested on imx8mn device with:
* Windbond W29N04GV

Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
CC: Stefano Babic <sbabic@denx.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-29 09:26:44 -04:00
Chris Morgan
30975fb73d rockchip: Add option to prevent booting on power plug-in
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.

This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przywara@arm.com/

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-29 11:42:10 +08:00
Chris Morgan
ad607512f5 power: pmic: rk8xx: Support sysreset shutdown method
Add support for sysreset shutdown for this PMIC. The values were pulled
from the various datasheets, but for now it has only been tested on
the rk817 (for an Odroid Go Advance).

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:42:10 +08:00
Johan Jonker
42a2f7a46d rockchip: usb: phy: add rk3066/rk3188 support
Add rk3066a/rk3188 support to rockchip_usb2_phy.c
They don't have completely identical usb phy registers,
so separate comapatible strings and data.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:15 +08:00
Paweł Jarosz
8fb5595525 rockchip: usb: gadget: add rk3066 product id
Product id of rk3066 usb otg is 0x300a.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:15 +08:00
Tom Rini
3371eddaa1 Convert CONFIG_USB_MAX_CONTROLLER_COUNT to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_MAX_CONTROLLER_COUNT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:11:48 -04:00
Tom Rini
a89a4538a1 usb: Remove non-DM code in ehci-fsl and xhci
The DM_USB migration deadline has passed and this is not used in SPL.
Remove this now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:11:48 -04:00
Tom Rini
6e52cb259b Convert CONFIG_FPGA_STRATIX_V to Kconfig
This converts the following to Kconfig:
   CONFIG_FPGA_STRATIX_V

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:11:48 -04:00
Tom Rini
4d2cab33d4 video: Migrate exynos display options to Kconfig
Following how it's done for the majority of drivers, add a new
VIDEO_EXYNOS option and Kconfig file under drivers/video/exynos and list
the current options there.

Cc: Anatolij Gustschin <agust@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28 17:04:38 -04:00
Tom Rini
24ec3dea4b arm: samsung: Migrate a number of symbols to Kconfig
- In a number of cases, use CONFIG_ARCH_EXYNOS[45] rather than
  CONFIG_EXYNOS[45]
- In other cases, test for CONFIG_ARCH_EXYNOS or CONFIG_ARCH_S5PC1XX
- Migrate specific SoC CONFIG values to Kconfig
- Use CONFIG_TARGET_x rather than CONFIG_x
- Migrate other CONFIG_EXYNOS_x symbols to Kconfig
- Reference CONFIG_EXYNOS_RELOCATE_CODE_BASE directly as EXYNOS_RELOCATE_CODE_BASE
- Rename CONFIG_S5P_PA_SYSRAM to CONFIG_SMP_PEN_ADDR to match the rest
  of U-Boot usage.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:04:37 -04:00
Tom Rini
1e03e03d03 arm: exynos: Remove old pwm backlight driver
Remove the unused older exynos pwm backlight driver.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28 17:03:32 -04:00
Tom Rini
dc2d27ae72 arm: samsung: Remove dead LCD code
Since bb5930d5c9 ("exynos: video: Convert several boards to driver
model for video") there have been no callers of any of the exynos_lcd_*
family of functions.  Remove these from the boards, and then remove
unused logo and related code as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-06-28 17:03:32 -04:00
Tom Rini
713a8cbb94 block: ide: Remove ide_preinit function
The only platform currently that defines an ide_preinit function has an
empty one that immediately returns.  Remove this hook.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:32 -04:00
Tom Rini
9836c43309 ata: sata_sil: Remove useless BLK guard in sata_sil.h
Now that the driver only supports CONFIG_BLK, remove the useless guard
in sata_sil.h.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:32 -04:00
Tom Rini
aca1f6789a Convert CONFIG_LBA48 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_LBA48
   CONFIG_SYS_64BIT_LBA

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:32 -04:00
Tom Rini
0a816d92d5 Convert CONFIG_FSL_SATA_V2 to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_SATA_V2

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
21af94f882 ata: fsl_sata: Remove legacy non-BLK code
The migration deadline for this has passed and all boards have been
updated, remove this legacy code and references for it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
7b976f7a0b ata: dwc_ahsata: Remove legacy non-CONFIG_AHCI code
The migration deadline for this has passed and all boards have been
updated, remove this legacy code and references for it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
8bea4bf7d3 tpl: Ensure all TPL symbols in Kconfig have some TPL dependency
Tighten up symbol dependencies in a number of places.  Ensure that a TPL
specific option has at least a direct dependency on TPL.  In places
where it's clear that we depend on something more specific, use that
dependency instead.

Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
49958813e2 usb: ehci-mx5: Remove non-DM code
The deadline for DM_USB migration has passed and all users have been
migrated.  Remove now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
13750af038 usb: ehci-mxc: Remove
There are no platforms enabling this driver, remove.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
cbee8c1ac2 usb: xhci-fsl: Remove non-DM code
The deadline for DM_USB migration has passed and all users have been
migrated.  Remove now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
d4ae15260b Convert CONFIG_USB_EHCI_TXFIFO_THRESH to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_EHCI_TXFIFO_THRESH

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
093044735f usb: ehci-fsl: Remove non-DM code
The deadline for DM_USB migration has passed and all users have been
migrated.  Remove now unused code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
e78e880da9 Convert CONFIG_EHCI_HCD_INIT_AFTER_RESET to Kconfig
This converts the following to Kconfig:
   CONFIG_EHCI_HCD_INIT_AFTER_RESET

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
879b0b16de Convert CONFIG_EHCI_DESC_BIG_ENDIAN et al to Kconfig
This converts the following to Kconfig:
   CONFIG_EHCI_DESC_BIG_ENDIAN
   CONFIG_EHCI_MMIO_BIG_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Tom Rini
90bb5c08c8 ehci-mxs: Remove non-DM code
This code is not enabled anywhere, drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:30 -04:00
Tom Rini
5c511ea936 Convert CONFIG_E1000_NO_NVM to Kconfig
This converts the following to Kconfig:
   CONFIG_E1000_NO_NVM

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:30 -04:00
Frieder Schrempf
2add051175 pmic: pca9450: Add optional SD_VSEL GPIO for LDO5
LDO5 has two separate control registers. LDO5CTRL_L is used if the
input signal SD_VSEL is low and LDO5CTRL_H if it is high.
The current driver implementation only uses LDO5CTRL_H. To make this
work on boards that have SD_VSEL connected to a GPIO, we add support
for specifying an optional GPIO and setting it to high at probe time.

In the future we might also want to add support for boards that have
SD_VSEL set to a fixed low level. In this case we need to change the
driver to be able to use the LDO5CTRL_L register.

This is a port of the same change in the Linux kernel:
8c67a11bae88 ("regulator: pca9450: Add SD_VSEL GPIO for LDO5")

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Fabio Estevam <festevam@denx.de>
2022-06-28 15:24:31 +02:00
Eugen Hristev
73a9616c21 misc: i2c_eeprom: remove 24aa02e48
This compatible does not exist in the bindings.
All occurences in DT have been replaced by at24c02 which is equivalent.

Fixes: 7264066707 ("misc: i2c_eeprom: Add compatible for 24AA02E48")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-06-28 10:09:45 +03:00
Heinrich Schuchardt
d4462ba044 sandbox: cast to pointer from integer of different size
Building sandbox_defconfig on ARMv7 with HOST_32BIT=y results in:

drivers/misc/qfw_sandbox.c:51:25: warning:
cast to pointer from integer of different size [-Wint-to-pointer-cast]
   51 |         void *address = (void *)be64_to_cpu(dma->address);

Add the missing type conversion.

Fixes: 69512551aa ("test: qemu: add qfw sandbox driver, dm tests, qemu tests")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-06-28 03:09:52 +01:00
Simon Glass
4f6500aa1a dm: spl: Allow SPL to show memory usage
Add an option to tell SPL to show memory usage for driver model just
before it boots into the next phase.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-06-28 03:09:52 +01:00
Simon Glass
2cb4ddb91e dm: core: Add a command to show driver model statistics
This command shows the memory used by driver model along with various
hints as to what it might be if some 'core' tags were moved to use the
tag list instead of a core (i.e. always-there) pointer.

This may help with future work to reduce memory usage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-06-28 03:09:52 +01:00
Simon Glass
0dfda34ca5 dm: core: Add a way to collect memory usage
Add a function for collecting the amount of memory used by driver model,
including devices, uclasses and attached data and tags.

This information can provide insights into how to reduce the memory
required by driver model. Future work may look at execution speed also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-06-28 03:09:52 +01:00
Simon Glass
930a3ddade dm: core: Support accessing core tags
At present tag numbers are only allocated for non-core data, meaning that
the 'core' data, like priv and plat, are accessed through dedicated
functions.

For debugging and consistency it is convenient to use tags for this 'core'
data too. Add support for this, with new tag numbers and functions to
access the pointer and size for each.

Update one of the test drivers so that the uclass-private data can be
tested here.

There is some code duplication with functions like device_alloc_priv() but
this is not addressed for now. At some point, some rationalisation may
help to reduce code size, but more thought it needed on that.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-06-28 03:09:52 +01:00
Simon Glass
53c20bebb2 dm: core: Switch the testbus driver to use a new struct
At present this driver uses 'priv' struct to hold 'plat' data, which is
confusing. The contents of the strct don't matter, since only dtoc is
using it. Create a new struct with the correct name.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-06-28 03:09:52 +01:00
Simon Glass
c625666ea1 dm: core: Fix addresses in the dm static command
This command converts pointers to addresses, but the pointers being
converted are in the image's rodata region. For sandbox this means it
is not in DRAM so it does not make sense to do this conversion.

Fix this by showing a simple pointer instead. Drop the unnecessary
@ and hex prefixes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-06-28 03:09:52 +01:00
Simon Glass
1452870404 dm: core: Rename dm_dump_all()
This is not a good name anymore as it does not dump everything. Rename it
to dm_dump_tree() to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-06-28 03:09:52 +01:00
Heinrich Schuchardt
d3eb1bf7cf dm: fix formatting of uclass dump
Insert an empty line after each uclass independent of whether it has
devices or not.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-28 03:09:51 +01:00
Sean Anderson
501a9a7ed8 dm: core: Use device_foreach_child where possible
We have some nice macros for iterating over devices in device.h, but they
are not used by the driver core. Convert all the users I could find.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-06-28 03:09:51 +01:00
Sean Anderson
24057fe0a8 sandbox: usb: Fix out-of-bounds read when fd=-1
sandbox_flash_bulk uses priv->read_len to determine if priv->buff contains
the response data (such as from SCSI_INQUIRY). However, if priv->fd=-1 in
handle_read, then priv->read_len is not set even though we are going to
PHASE_DATA. This causes sandbox_flash_bulk to try and read len bytes from
priv->buff, which likely goes past the end of the buffer. Fix this by always
setting priv->read_len even if we aren't going to read anything.

Fixes: f4f715360c ("dm: usb: sandbox: Add an emulator for USB flash devices")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-06-28 03:09:51 +01:00
Tom Rini
c316ee674f Xilinx changes for v2022.10
cpu:
 - Add driver for microblaze cpu
 
 net:
 - Add support for DM_ETH_PHY to AXI emac and emaclite
 
 xilinx:
 - Switch platforms to DM_ETH_PHY
 - DT chagnes in ZynqMP and Zynq
 - Enable support for SquashFS
 
 zynqmp:
 - Add support for KR260 boards
 - Move BSS from address 0
 - Move platform identification from board code to soc driver
 - Improve zynqmp_psu_init_minimize
 
 versal:
 - Enable loading app at EL1
 
 serial:
 - Setup default address and clock rates for DEBUG uarts
 
 pinctrl:
 - Add support for tri state and output enable properties
 
 relocate-rela:
 - Clean relocate-rela implementation for ARM64
 - Add support for Microblaze
 
 microblaze:
 - Add support for runtime relocation
 - Rework cache handling (wiring, Kconfig) based on cpuinfo
 - Remove interrupt support
 
 timer:
 - Extract axi timer driver from Microblaze to generic location
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYrlYngAKCRDKSWXLKUoM
 ITgbAJ9S9xO2QqxtuodWAYMtJfvZ14c7mgCeKnyFTrrBnJkC0wPsGqE71oNJ49o=
 =3gGm
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location
2022-06-27 10:15:50 -04:00
Michal Simek
728a86edb6 timer: Add SPL_REGMAP dependency for Xilinx timer
Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation
issues if timer is selected but SPL_REGMAP not.

Reported-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8f6c187e04cb3127bf5148ae2dbbdf55b25ea544.1655982509.git.michal.simek@amd.com
2022-06-27 09:03:54 +02:00
Samuel Holland
33112ae021 clk: sunxi: Add additional RTC compatible strings
Compatible strings for some new RTC hardware variants were added to
the binding. Add them to the driver in preparation for supporting
those new SoCs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:53 +01:00
Samuel Holland
957a3b9820 gpio: sunxi: Fix build with CONFIG_SPL_SERIAL=n
This driver uses simple_strtol(), so it needs SPL_STRTO. Before commit
88ca8e2695 ("disk: Add an option for partitions in SPL"), SPL_STRTO
was always selected indirectly. Now it is not, so select it here.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:53 +01:00
Andre Przywara
3c0b9adb89 sunxi: usb: convert PHY GPIO functions to DM
The Allwinner USB PHY driver is still using the legacy GPIO interface,
which is now implemented by the DM_GPIO compat functions.
Those seem to have some design flaws, as setting the direction, then
later setting the value will not work, if the DM_GPIO driver is
implementing set_flags.

Fix this by using the dm_ version of the direct GPIO interface, which
uses struct gpio_desc structs to handle requested GPIOs, and actually
keeps the flags we set earlier.

This fixes USB operation on boards which need to toggle the VBUS supply
via a GPIO, like the Teres-I laptop or the BananaPi M2 Berry board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-06-26 11:22:53 +01:00
Patrick Delaunay
5bc6f8c2a9 video: stm32: remove test on CONFIG_DM_REGULATOR
The tests on CONFIG_DM_REGULATOR, added to avoid compilation issues, can
now be removed, they are no more needed since the commit 16cc5ad0b4
("power: regulator: add dummy helper").

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-25 08:18:42 +02:00
Bin Meng
5f71b2f105 driver: video: Check allocated pointers
The codes that call STBTT_malloc() / stbtt__new_active() do not check
the return value at present which may cause segfault.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-06-25 08:10:21 +02:00
Stefan Herbrechtsmeier
a1e618a1b9 soc: xilinx: zynqmp: Add machine identification support
Add machine identification support based on the
zynqmp_get_silicon_idcode_name function and use the soc_get_machine
function of the soc uclass to get silicon idcode name for the fpga init.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-8-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:37:27 +02:00
Stefan Herbrechtsmeier
18fcb49db5 soc: xilinx: zynqmp: Remove redundant checks for zynqmp_mmio_read
Remove the redundant SPL and CurrentEL checks for the zynqmp_mmio_read
function call because the function itself runs the same checks.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-7-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:37:27 +02:00
Stefan Herbrechtsmeier
f851be15f4 firmware: zynqmp: Probe driver before use
Probe the driver before use to ensure that the driver is always
available and the global data are valid. Initialize the global data
with zero and probe the driver if the global data are still zero. This
allows a usage of the firmware functions from other drivers with
arbitrary order between the drivers.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-2-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:37:27 +02:00
Stefan Herbrechtsmeier
fe7090c702 firmware: zynqmp: Check if rx channel dev pointer is valid
Check if rx channel dev pointer is valid and not if the address of the
pointer is valid.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:37:27 +02:00
Michal Simek
a36d86720f microblaze: Convert axi timer to DM driver
Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.

CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24 14:16:32 +02:00
Ovidiu Panait
816226d27e cpu: add CPU driver for microblaze
Add a basic CPU driver that retrieves information about the microblaze CPU
core. cpu_ops handlers are implemented so that the "cpu" command can work
properly:

U-Boot-mONStR> cpu list
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
U-Boot-mONStR> cpu detail
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
        ID = 0, freq = 50 MHz: L1 cache, MMU

Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from
linux.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
10f6508c07 microblaze: cache: introduce flush_dcache_range()
Align microblaze with the other architectures and provide an
implementation for flush_dcache_range(). Also, remove the microblaze
exception in drivers/core/device.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-11-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ovidiu Panait
b391b915bb cpu-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC
Relocate cpu_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.

The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24 14:16:00 +02:00
Ashok Reddy Soma
123462e5e5 pinctrl: zynqmp: Add support for output-enable and bias-high-impedance
Add support to handle 'output-enable' and 'bias-high-impedance'
configurations. DT property output-enable brings out the pins from
tri-state, whereas bias-high-impedance changes the pins state to
tri-state.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1a02cd41d183d397ebce23c497178281c7286692.1655286745.git.michal.simek@amd.com
2022-06-24 14:14:29 +02:00
Michal Simek
ad55d99e3c serial: Setup serial base and freq for zynq/zynqmp
Setup default values for debug console, base address and frequency.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ce93efd3ed67aa6390810ce0b79e0d00e7c36b4b.1652871485.git.michal.simek@amd.com
2022-06-24 14:11:05 +02:00
T Karthik Reddy
8faeb023e9 net: xilinx: axi_emaclite: Use shared MDIO bus support for axi emaclite driver
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/93e11ccca56b6e52b2dcc283d08d5042537f828f.1652181968.git.michal.simek@amd.com
2022-06-24 14:11:05 +02:00
T Karthik Reddy
935e3625ce net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/ecfec78234233fefdc172c141c207b2d78ef70c5.1652181968.git.michal.simek@amd.com
2022-06-24 14:11:05 +02:00
Tom Rini
31016a5a85 Merge branch '2022-06-23-scmi-optee-and-smccc-updates' into next
This consists of two slightly related series.  For the first, to quote
the author:
This series implements 2 features in driver/firmware/scmi.

First, a single change adds support for SCMI OP-TEE transport to
use OP-TEE native shared memory. See the 1st patch in this series:
"firmware: scmi: optee: use TEE shared memory for SCMI messages".

Then come changes for supporting multi-channel in the SCMI drivers.
I've split the implementation in 11 several small incremental changes
in the hope it helps the review. Few minor fixup commits are also
inserted in the series.

And the second series implements some smccc improvements.
2022-06-23 14:30:27 -04:00
Etienne Carriere
53355bb86c drivers: rng: add smccc trng driver
Adds random number generator driver using Arm SMCCC TRNG interface to
get entropy bytes from secure monitor. The driver registers as an
Arm SMCCC feature driver to allow PSCI driver to bind a device for
when secure monitor exposes RNG support from Arm SMCCC TRNG interface.

Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:56 -04:00
Etienne Carriere
2fbe47b7e7 firmware: psci: bind arm smccc features when discovered
Use PSCI device to query Arm SMCCC v1.1 support from secure monitor
and if so, bind drivers for the SMCCC features that monitor supports.

Drivers willing to be bound from Arm SMCCC features discovery can use
macro ARM_SMCCC_FEATURE_DRIVER() to register to smccc feature discovery,
providing target driver name and a callback function that returns
whether or not the SMCCC feature is supported by the system.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:56 -04:00
Etienne Carriere
b1ff399c6e firmware: psci: reorder header files inclusion
Fixes ordering of header files inclusion in PSCI firmware driver.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:56 -04:00
Etienne Carriere
c08decd29e firmware: scmi: use multi channel in mailbox, optee and smccc agents
Updates .process_msg operators of the SCMI transport drivers that
supports multi-channel to use it now that drivers do provide
the reference through channel argument. These are the mailbox
agent, the optee agent and the smccc agent.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:56 -04:00
Etienne Carriere
db59fef0f8 power: regulator: scmi: simplify scmi_voltd_set_enable()
Simplify scmi_voltd_set_enable() exit sequence.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-23 13:12:56 -04:00
Etienne Carriere
ff33ed32b6 power: regulator: scmi: support SCMI multi-channel
Update SCMI regulator controller driver to get its assigned SCMI channel
during initialization. This change allows SCMI voltage domain protocol
to use a dedicated channel when defined in the DT. The reference is
saved in SCMI regulator controller driver private data.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-23 13:12:55 -04:00
Etienne Carriere
f487a88c64 reset: scmi: support SCMI multi-channel
Update SCMI reset controller driver to get its assigned SCMI channel
during initialization. This change allows SCMI reset domain protocol
to use a dedicated channel when defined in the DT. The reference is
saved in SCMI reset controller driver private data.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
38a905ecf9 clk: scmi: support SCMI multi-channel
Update SCMI clock driver to get its assigned SCMI channel during
initialization. This change allows SCMI clock protocol to use a
dedicated channel when defined in the DT. The reference is saved
in SCMI clock driver private data.

Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
965d606d60 firmware: scmi: optee transport: implement multi-channel
Implements multi SCMI channel support in OP-TEE SCMI transport. An
SCMI protocol may use a dedicated channel, specified by the DT.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
57b812fc8f firmware: scmi: smccc transport: implement multi-channel
Updates SCMI SMCCC transport driver to get SCMI channel reference
at initialization and use when posting SCMI messages.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
b5d32ea42b firmware: scmi: mailbox transport: implement multi-channel
Updates SCMI mailbox transport driver to get SCMI channel reference
at initialization and use when posting SCMI messages.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
8e96801aa6 firmware: scmi: add multi-channel support
Adds resources for SCMI protocols to possibly use a dedicated SCMI
channel instead of the default channel allocated by the SCMI agent
during initialization. As per DT binding documentation, some SCMI
transports can define a specific SCMI communication channel for
given SCMI protocols. It allows SCMI protocols to pass messages
concurrently each other.

This change introduces new scmi agent uclass API function
devm_scmi_of_get_channel() for SCMI drivers probe sequences to get
a reference to the SCMI channel assigned to its related SCMI protocol.
The function queries the channel reference to its SCMI transport driver
through new scmi agent uclass operator .of_get_channel that uses Device
Tree information from related SCMI agent node.

Operator .of_get_channel returns a reference to the SCMI channel
assigned to SCMI protocol used by the caller device. SCMI transport
drivers that do not support multi-channel are not mandated to register
this operator. When so, API function devm_scmi_of_get_channel() returns
NULL and SCMI transport driver are expected to retrieve by their own
means the reference to the unique SCMI channel, for example using
platform data as these drivers currently do in U-Boot source tree.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
5a11df381a firmware: scmi: factorize scmi transport look up
Defines local helper function find_scmi_transport_device() with the
instructions to find the SCMI transport device from a SCMI protocol
device.

Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
85dc582892 firmware: scmi: prepare uclass to pass channel reference
Changes SCMI transport operator ::process_msg to pass the SCMI channel
reference provided by caller SCMI protocol device.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
8bcb1b4898 firmware: scmi: prepare scmi uclass API to multi-channel
Changes SCMI driver API function devm_scmi_process_msg() to add
an SCMI channel reference argument for when SCMI agent supports
SCMI protocol specific channels. First argument of devm_scmi_process_msg()
is also change to point to the caller SCMI protocol device rather
than its parent device (the SCMI agent device).

The argument is a pointer to opaque struct scmi_channel known from
the SCMI transport drivers. It is currently unused and caller a pass
NULL value. A later change will enable such support once SCMI protocol
drivers have means to get the channel reference during initialization.

Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
5d8eb4ce33 firmware: scmi: optee: fix inline description of PTA_SCMI_CMD_GET_CHANNEL
Removes inaccurate inline description of OP-TEE SCMI PTA command
PTA_SCMI_CMD_GET_CHANNEL.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Etienne Carriere
593eac9805 firmware: scmi: optee: use TEE shared memory for SCMI messages
Changes implementation when using TEE dynamically allocated shared
memory to synchronize with the Linux implementation where the legacy
SMT protocol cannot be used with such memory since it is expected from
device mapped memory whereas OP-TEE shared memory is cached and
hence should not be accessed using memcpy_toio()/memcpy_fromio().

This change implements the MSG shared memory protocol introduced
in Linux [1]. The protocol uses a simplified SMT header of 32bit
named MSG_SMT to carry SCMI protocol information and uses side channel
means to carry exchanged buffer size information, as TEE invocation API
parameters when used in the SCMI OP-TEE transport.

Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f301bba0ca7392d16a6ea4f1d264a91f1fadea1a
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-23 13:12:55 -04:00
Andrew Scull
0518e7a28f sandbox: Implement fuzzing engine driver
Add a fuzzing engine driver for the sandbox to take inputs from
libfuzzer and expose them to the fuzz tests.

Signed-off-by: Andrew Scull <ascull@google.com>
2022-06-23 12:58:19 -04:00
Andrew Scull
3f807c6b81 fuzzing_engine: Add fuzzing engine uclass
This new class of device will provide fuzzing inputs from a fuzzing
engine.

Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-06-23 12:58:18 -04:00
Andrew Scull
337b26e468 serial: sandbox: Fix buffer underflow in puts
Fix the buffer underflow that would occur if puts is called with length
of zero.

Fixes: efa51f2bd6 ("serial: sandbox: Implement puts")
Cc: Sean Anderson <sean.anderson@seco.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2022-06-23 12:58:18 -04:00
Janne Grunau
e44d59c6ad arm: apple: nvme: Add SART support and RTKit buffer management
The NVMe firmware in the macOS 13 beta blocks or crashes with u-boot's
current minimal RTKit implementation. It does not provide buffers for
the firmware's buffer requests. The ANS2 firmware included in macOS 11
and 12 tolerates this. The firmware included in the first macOS 13 beta
requires buffers for the crashlog and ioreport endpoints to function.

In the case of the NVMe the buffers are physical memory. Access to
physical memory is guarded by what Apple calls SART.
Import m1n1's SART driver (exclusively used for the NVMe controller).
Implement buffer management helpers for RTKit. These are generic since
other devices (none in u-boot so far) require different handling.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-23 08:24:49 -04:00
Jim Liu
0ae1c77199 misc: nuvoton: Add NPCM7xx otp controller driver
Add Nuvoton BMC npcm750 otp driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Jim Liu
2eeb4ee97e crypto: nuvoton: Add NPCM7xx SHA driver
add nuvoton BMC npcm750 SHA driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Jim Liu
9e03b48dfa crypto: nuvoton: Add NPCM7xx AES driver
add nuvoton BMC npcm750 AES driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Nick Hawkins
4f689b3d86 spi: gxp_spi: Add GXP SPI controller driver
The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22 21:30:05 -04:00
Nick Hawkins
b25913b40e timer: gxp: Add HPE GXP timer support
Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-22 21:30:04 -04:00
Tom Rini
52af0101be Merge branch 'master' into next
Merge in v2022.07-rc5.
2022-06-20 14:40:59 -04:00
Tom Rini
2f7821a927 - Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
 - Activate livetree for stm32mp15 DHSOM boards
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAmKsehgACgkQ4rK92eCq
 k3UexAf+JThCd7FlN3OkTVKIdZKeNm2KpQxrqt20whiqp/nSUzxXrjdlCTKZEER2
 lLJoVnwr+bkmdlqsa6gAZXSsd0lUv37XnLsLA5or278tFNlKp6gzYrz49FR59mVC
 ie7/NlY5FgM5qmKGCob7tjwJ78r2/S3T2EaLiAMWUmw2UB5KZU6h3napHZ+1T0se
 vaEAVRzAaZeYzKU3k6RBSv2tXQ6ssvfpp9RcXpRGtrN908AqDhHiOfntuOrnsEe0
 9rjY1DSXO9a5WqHRm2KQ3FrA/By2layQ+4WH/HgIPHasisnmo3E/euVWmhtTaiT/
 g5bOLwyFQ2/RvdMlMxXlKUcuMfNwRA==
 =Hhzj
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
2022-06-20 08:09:24 -04:00
Pali Rohár
8f3f8ba945 mmc: fsl_esdhc: Add new config option for default fallback mode
Currently default fallback SDHC mode is 1-bit. Add new config option
CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback
mode. This is useful e.g. for SPL builds which loads other parts from SD
card during boot process.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-20 15:52:45 +08:00
Pali Rohár
a29eb319a3 mmc: fsl_esdhc: Set fallback mode to 1-bit
8-bit mode is not supported by SD cards and on P2020 are four SDHC pins
shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode
is provided). So 8-bit SDHC mode is really bad default.

When max bus width is not provided then set mode to 1-bit. This mode is
supported by all cards, so it is the best option for fallback mode.

Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-20 15:52:44 +08:00
Pali Rohár
26153d0b05 mtd: rawnand: fsl_elbc: Fix DM support in DTS code path
For proper DM support it is required to fill also mtd->dev member.
Otherwise DM would not see nand device at all.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-20 09:18:26 +08:00
Sean Anderson
2645bc0e12 arm: layerscape: Add sfp driver
This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.

The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.

The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.

I suggest using the following procedure for programming:

1. Override the fuses you wish to program
   => fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
   => fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
   write-protect bit you will usually want to write it last anyway.
   => fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
   => fuse read 0 2 4

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-06-20 09:18:25 +08:00
Tom Rini
f0843e0c0a Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfong/uboot_mainline 2022-06-17 09:35:28 -04:00
Patrick Delaunay
eae488b779 stm32mp1: fix reference for STMicroelectronics
Replace reference to the correct name STMicroelectronics

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 14:12:27 +02:00