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clk/ast2500: Add SD clock

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In order to use the clock from the sdhci driver, add the SD clock.

Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Joel Stanley 2022-06-23 18:35:32 +09:30 committed by Tom Rini
parent 85bb3a4eee
commit 50204533dc
1 changed files with 23 additions and 0 deletions
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23
drivers/clk/aspeed/clk_ast2500.c
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@ -12,6 +12,7 @@
#include <asm/arch/scu_ast2500.h>
#include <dm/lists.h>
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/reset/ast2500-reset.h>
#include <linux/delay.h>
#include <linux/err.h>
@ -426,6 +427,25 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
return new_rate;
}
#define SCU_CLKSTOP_SDIO 27
static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)
{
u32 reset_bit;
u32 clkstop_bit;
reset_bit = BIT(ASPEED_RESET_SDIO);
clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
setbits_le32(&scu->sysreset_ctrl1, reset_bit);
udelay(100);
//enable clk
clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
mdelay(10);
clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
return 0;
}
static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
{
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
@ -481,6 +501,9 @@ static int ast2500_clk_enable(struct clk *clk)
case ASPEED_CLK_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break;
case ASPEED_CLK_GATE_SDCLK:
ast2500_enable_sdclk(priv->scu);
break;
default:
debug("%s: unknown clk %ld\n", __func__, clk->id);
return -ENOENT;