mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-16 23:07:00 +00:00
Merge tag 'u-boot-rockchip-20220630' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Fix for rk3328 nonopi-r2s boot env; - Fix for rk8xx pmic boot on power plug-in; - Fix for tee.bin support in fit image; - rk3288 board dts update or fix; - Some rk3399 board fix;
This commit is contained in:
Tom Rini
commit
33938636f0
18 changed files with 380 additions and 264 deletions
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|
@ -642,8 +642,7 @@
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|||
compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
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||||
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||||
usbphy: usbphy {
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||||
compatible = "rockchip,rk3188-usb-phy",
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"rockchip,rk3288-usb-phy";
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||||
compatible = "rockchip,rk3188-usb-phy";
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||||
#address-cells = <1>;
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||||
#size-cells = <0>;
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status = "disabled";
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||||
|
|
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|||
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@ -448,7 +448,7 @@
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status = "okay";
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};
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&mipi_dsi0 {
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&mipi_dsi {
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status = "disabled";
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rockchip,panel = <&panel>;
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display-timings {
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|
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|||
|
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@ -86,47 +86,6 @@
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};
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dmac_peri: dma-controller@ff250000 {
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compatible = "arm,pl330", "arm,primecell";
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broken-no-flushp;
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reg = <0xff250000 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC2>;
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clock-names = "apb_pclk";
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};
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dmac_bus_ns: dma-controller@ff600000 {
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compatible = "arm,pl330", "arm,primecell";
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broken-no-flushp;
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reg = <0xff600000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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dmac_bus_s: dma-controller@ffb20000 {
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compatible = "arm,pl330", "arm,primecell";
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broken-no-flushp;
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reg = <0xffb20000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC1>;
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clock-names = "apb_pclk";
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};
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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@ -367,6 +326,18 @@
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pinctrl-0 = <&uart4_xfer>;
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status = "disabled";
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};
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dmac_peri: dma-controller@ff250000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xff250000 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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broken-no-flushp;
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clocks = <&cru ACLK_DMAC2>;
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clock-names = "apb_pclk";
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};
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thermal: thermal-zones {
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#include "rk3288-thermal.dtsi"
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};
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@ -458,6 +429,18 @@
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status = "disabled";
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};
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dmac_bus_ns: dma-controller@ff600000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xff600000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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broken-no-flushp;
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clocks = <&cru ACLK_DMAC1>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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i2c0: i2c@ff650000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff650000 0x1000>;
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@ -709,7 +692,63 @@
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status = "disabled";
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};
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edp: edp@ff970000 {
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mipi_dsi: mipi@ff960000 {
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compatible = "rockchip,rk3288_mipi_dsi";
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reg = <0xff960000 0x4000>;
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clocks = <&cru PCLK_MIPI_DSI0>;
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clock-names = "pclk_mipi";
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/*pinctrl-names = "default";
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pinctrl-0 = <&lcdc0_ctl>;*/
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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reg = <1>;
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mipi_in: port {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_mipi>;
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};
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mipi_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_mipi>;
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};
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};
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};
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};
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lvds: lvds@ff96c000 {
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compatible = "rockchip,rk3288-lvds";
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reg = <0xff96c000 0x4000>;
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clocks = <&cru PCLK_LVDS_PHY>;
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clock-names = "pclk_lvds";
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pinctrl-names = "default";
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pinctrl-0 = <&lcdc0_ctl>;
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rockchip,grf = <&grf>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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lvds_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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lvds_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_lvds>;
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};
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lvds_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_lvds>;
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};
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};
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};
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};
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edp: dp@ff970000 {
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compatible = "rockchip,rk3288-edp";
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reg = <0xff970000 0x4000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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@ -762,62 +801,6 @@
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};
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};
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lvds: lvds@ff96c000 {
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compatible = "rockchip,rk3288-lvds";
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reg = <0xff96c000 0x4000>;
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clocks = <&cru PCLK_LVDS_PHY>;
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clock-names = "pclk_lvds";
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pinctrl-names = "default";
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pinctrl-0 = <&lcdc0_ctl>;
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rockchip,grf = <&grf>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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lvds_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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lvds_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_lvds>;
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};
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lvds_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_lvds>;
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};
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};
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};
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};
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mipi_dsi0: mipi@ff960000 {
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compatible = "rockchip,rk3288_mipi_dsi";
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reg = <0xff960000 0x4000>;
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clocks = <&cru PCLK_MIPI_DSI0>;
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clock-names = "pclk_mipi";
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/*pinctrl-names = "default";
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pinctrl-0 = <&lcdc0_ctl>;*/
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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reg = <1>;
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mipi_in: port {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_mipi>;
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};
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mipi_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_mipi>;
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};
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};
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};
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};
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hdmi_audio: hdmi_audio {
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compatible = "rockchip,rk3288-hdmi-audio";
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i2s-controller = <&i2s>;
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@ -870,6 +853,17 @@
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status = "disabled";
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};
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dmac_bus_s: dma-controller@ffb20000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffb20000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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broken-no-flushp;
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clocks = <&cru ACLK_DMAC1>;
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clock-names = "apb_pclk";
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};
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efuse: efuse@ffb40000 {
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compatible = "rockchip,rk3288-efuse";
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reg = <0xffb40000 0x10000>;
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@ -1072,411 +1066,411 @@
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sleep {
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global_pwroff: global-pwroff {
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rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
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rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
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};
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ddrio_pwroff: ddrio-pwroff {
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rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
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rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
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};
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ddr0_retention: ddr0-retention {
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rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
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rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
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};
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ddr1_retention: ddr1-retention {
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rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
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rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
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};
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
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<0 16 RK_FUNC_1 &pcfg_pull_none>;
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rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
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<0 RK_PC0 1 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
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<8 5 RK_FUNC_1 &pcfg_pull_none>;
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rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
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<8 RK_PA5 1 &pcfg_pull_none>;
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};
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};
|
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|
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i2c2 {
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i2c2_xfer: i2c2-xfer {
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rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
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<6 10 RK_FUNC_1 &pcfg_pull_none>;
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rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
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<6 RK_PB2 1 &pcfg_pull_none>;
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};
|
||||
};
|
||||
|
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i2c3 {
|
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i2c3_xfer: i2c3-xfer {
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rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
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<2 17 RK_FUNC_1 &pcfg_pull_none>;
|
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rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
|
||||
<2 RK_PC1 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4 {
|
||||
i2c4_xfer: i2c4-xfer {
|
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rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<7 18 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
|
||||
<7 RK_PC2 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5 {
|
||||
i2c5_xfer: i2c5-xfer {
|
||||
rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<7 20 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
|
||||
<7 RK_PC4 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s0 {
|
||||
i2s0_bus: i2s0-bus {
|
||||
rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<6 1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<6 2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<6 3 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<6 4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<6 8 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
|
||||
<6 RK_PA1 1 &pcfg_pull_none>,
|
||||
<6 RK_PA2 1 &pcfg_pull_none>,
|
||||
<6 RK_PA3 1 &pcfg_pull_none>,
|
||||
<6 RK_PA4 1 &pcfg_pull_none>,
|
||||
<6 RK_PB0 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
lcdc0 {
|
||||
lcdc0_ctl: lcdc0-ctl {
|
||||
rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 25 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 26 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 27 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
|
||||
<1 RK_PD1 1 &pcfg_pull_none>,
|
||||
<1 RK_PD2 1 &pcfg_pull_none>,
|
||||
<1 RK_PD3 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdmmc_cd: sdmcc-cd {
|
||||
rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdmmc_bus1: sdmmc-bus1 {
|
||||
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<6 17 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<6 18 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<6 19 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
|
||||
<6 RK_PC1 1 &pcfg_pull_up>,
|
||||
<6 RK_PC2 1 &pcfg_pull_up>,
|
||||
<6 RK_PC3 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio0 {
|
||||
sdio0_bus1: sdio0-bus1 {
|
||||
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio0_bus4: sdio0-bus4 {
|
||||
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<4 21 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<4 22 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<4 23 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
|
||||
<4 RK_PC5 1 &pcfg_pull_up>,
|
||||
<4 RK_PC6 1 &pcfg_pull_up>,
|
||||
<4 RK_PC7 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio0_cmd: sdio0-cmd {
|
||||
rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio0_clk: sdio0-clk {
|
||||
rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sdio0_cd: sdio0-cd {
|
||||
rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio0_wp: sdio0-wp {
|
||||
rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio0_pwr: sdio0-pwr {
|
||||
rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio0_bkpwr: sdio0-bkpwr {
|
||||
rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio0_int: sdio0-int {
|
||||
rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio1 {
|
||||
sdio1_bus1: sdio1-bus1 {
|
||||
rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio1_bus4: sdio1-bus4 {
|
||||
rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
|
||||
<3 25 RK_FUNC_4 &pcfg_pull_up>,
|
||||
<3 26 RK_FUNC_4 &pcfg_pull_up>,
|
||||
<3 27 RK_FUNC_4 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
|
||||
<3 RK_PD1 4 &pcfg_pull_up>,
|
||||
<3 RK_PD2 4 &pcfg_pull_up>,
|
||||
<3 RK_PD3 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio1_cd: sdio1-cd {
|
||||
rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio1_wp: sdio1-wp {
|
||||
rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio1_bkpwr: sdio1-bkpwr {
|
||||
rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio1_int: sdio1-int {
|
||||
rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio1_cmd: sdio1-cmd {
|
||||
rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdio1_clk: sdio1-clk {
|
||||
rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
|
||||
rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sdio1_pwr: sdio1-pwr {
|
||||
rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
|
||||
rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
|
||||
rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_pwr: emmc-pwr {
|
||||
rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus1: emmc-bus1 {
|
||||
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus4: emmc-bus4 {
|
||||
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 1 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 2 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 3 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
|
||||
<3 RK_PA1 2 &pcfg_pull_up>,
|
||||
<3 RK_PA2 2 &pcfg_pull_up>,
|
||||
<3 RK_PA3 2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 1 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 2 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 3 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 4 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 5 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 6 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 7 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
|
||||
<3 RK_PA1 2 &pcfg_pull_up>,
|
||||
<3 RK_PA2 2 &pcfg_pull_up>,
|
||||
<3 RK_PA3 2 &pcfg_pull_up>,
|
||||
<3 RK_PA4 2 &pcfg_pull_up>,
|
||||
<3 RK_PA5 2 &pcfg_pull_up>,
|
||||
<3 RK_PA6 2 &pcfg_pull_up>,
|
||||
<3 RK_PA7 2 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0 {
|
||||
spi0_clk: spi0-clk {
|
||||
rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_cs0: spi0-cs0 {
|
||||
rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_tx: spi0-tx {
|
||||
rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_rx: spi0-rx {
|
||||
rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi0_cs1: spi0-cs1 {
|
||||
rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
spi1 {
|
||||
spi1_clk: spi1-clk {
|
||||
rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_cs0: spi1-cs0 {
|
||||
rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_rx: spi1-rx {
|
||||
rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
|
||||
};
|
||||
spi1_tx: spi1-tx {
|
||||
rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
|
||||
rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
spi2 {
|
||||
spi2_cs1: spi2-cs1 {
|
||||
rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi2_clk: spi2-clk {
|
||||
rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi2_cs0: spi2-cs0 {
|
||||
rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi2_rx: spi2-rx {
|
||||
rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
|
||||
};
|
||||
spi2_tx: spi2-tx {
|
||||
rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<4 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
|
||||
<4 RK_PC1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <4 RK_PC2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<5 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
|
||||
<5 RK_PB1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <5 RK_PB2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<7 23 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
|
||||
<7 RK_PC7 1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<7 8 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
|
||||
<7 RK_PB0 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_cts: uart3-cts {
|
||||
rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PB1 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_rts: uart3-rts {
|
||||
rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
uart4_xfer: uart4-xfer {
|
||||
rockchip,pins = <5 12 3 &pcfg_pull_up>,
|
||||
<5 13 3 &pcfg_pull_none>;
|
||||
rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>,
|
||||
<5 RK_PB5 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart4_cts: uart4-cts {
|
||||
rockchip,pins = <5 14 3 &pcfg_pull_none>;
|
||||
rockchip,pins = <5 RK_PB6 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart4_rts: uart4-rts {
|
||||
rockchip,pins = <5 15 3 &pcfg_pull_none>;
|
||||
rockchip,pins = <5 RK_PB7 3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
tsadc {
|
||||
otp_out: otp-out {
|
||||
rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pwm0_pin: pwm0-pin {
|
||||
rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pwm1_pin: pwm1-pin {
|
||||
rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pwm2_pin: pwm2-pin {
|
||||
rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pwm3_pin: pwm3-pin {
|
||||
rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
|
||||
rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
rgmii_pins: rgmii-pins {
|
||||
rockchip,pins = <3 30 3 &pcfg_pull_none>,
|
||||
<3 31 3 &pcfg_pull_none>,
|
||||
<3 26 3 &pcfg_pull_none>,
|
||||
<3 27 3 &pcfg_pull_none>,
|
||||
<3 28 3 &pcfg_pull_none_12ma>,
|
||||
<3 29 3 &pcfg_pull_none_12ma>,
|
||||
<3 24 3 &pcfg_pull_none_12ma>,
|
||||
<3 25 3 &pcfg_pull_none_12ma>,
|
||||
<4 0 3 &pcfg_pull_none>,
|
||||
<4 5 3 &pcfg_pull_none>,
|
||||
<4 6 3 &pcfg_pull_none>,
|
||||
<4 9 3 &pcfg_pull_none_12ma>,
|
||||
<4 4 3 &pcfg_pull_none_12ma>,
|
||||
<4 1 3 &pcfg_pull_none>,
|
||||
<4 3 3 &pcfg_pull_none>;
|
||||
rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
|
||||
<3 RK_PD7 3 &pcfg_pull_none>,
|
||||
<3 RK_PD2 3 &pcfg_pull_none>,
|
||||
<3 RK_PD3 3 &pcfg_pull_none>,
|
||||
<3 RK_PD4 3 &pcfg_pull_none_12ma>,
|
||||
<3 RK_PD5 3 &pcfg_pull_none_12ma>,
|
||||
<3 RK_PD0 3 &pcfg_pull_none_12ma>,
|
||||
<3 RK_PD1 3 &pcfg_pull_none_12ma>,
|
||||
<4 RK_PA0 3 &pcfg_pull_none>,
|
||||
<4 RK_PA5 3 &pcfg_pull_none>,
|
||||
<4 RK_PA6 3 &pcfg_pull_none>,
|
||||
<4 RK_PB1 3 &pcfg_pull_none_12ma>,
|
||||
<4 RK_PA4 3 &pcfg_pull_none_12ma>,
|
||||
<4 RK_PA1 3 &pcfg_pull_none>,
|
||||
<4 RK_PA3 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
rmii_pins: rmii-pins {
|
||||
rockchip,pins = <3 30 3 &pcfg_pull_none>,
|
||||
<3 31 3 &pcfg_pull_none>,
|
||||
<3 28 3 &pcfg_pull_none>,
|
||||
<3 29 3 &pcfg_pull_none>,
|
||||
<4 0 3 &pcfg_pull_none>,
|
||||
<4 5 3 &pcfg_pull_none>,
|
||||
<4 4 3 &pcfg_pull_none>,
|
||||
<4 1 3 &pcfg_pull_none>,
|
||||
<4 2 3 &pcfg_pull_none>,
|
||||
<4 3 3 &pcfg_pull_none>;
|
||||
rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
|
||||
<3 RK_PD7 3 &pcfg_pull_none>,
|
||||
<3 RK_PD4 3 &pcfg_pull_none>,
|
||||
<3 RK_PD5 3 &pcfg_pull_none>,
|
||||
<4 RK_PA0 3 &pcfg_pull_none>,
|
||||
<4 RK_PA5 3 &pcfg_pull_none>,
|
||||
<4 RK_PA4 3 &pcfg_pull_none>,
|
||||
<4 RK_PA1 3 &pcfg_pull_none>,
|
||||
<4 RK_PA2 3 &pcfg_pull_none>,
|
||||
<4 RK_PA3 3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
spdif {
|
||||
spdif_tx: spdif-tx {
|
||||
rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
/ {
|
||||
model = "Pine64 Pinebook Pro";
|
||||
compatible = "pine64,pinebook-pro", "rockchip,rk3399";
|
||||
chassis-type = "laptop";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdio0;
|
||||
|
|
@ -242,12 +243,12 @@
|
|||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
pwm-supply = <&vcc_sysin>;
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
|
|
@ -385,10 +386,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&cdn_dp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
|
@ -475,8 +472,6 @@
|
|||
vcc10-supply = <&vcc_sysin>;
|
||||
vcc11-supply = <&vcc_sysin>;
|
||||
vcc12-supply = <&vcc3v3_sys>;
|
||||
vcc13-supply = <&vcc_sysin>;
|
||||
vcc14-supply = <&vcc_sysin>;
|
||||
|
||||
regulators {
|
||||
/* rk3399 center logic supply */
|
||||
|
|
@ -711,7 +706,7 @@
|
|||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
data-role = "host";
|
||||
data-role = "dual";
|
||||
label = "USB-C";
|
||||
op-sink-microwatt = <1000000>;
|
||||
power-role = "dual";
|
||||
|
|
|
|||
|
|
@ -361,6 +361,16 @@ config ROCKCHIP_BOOT_MODE_REG
|
|||
The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
|
||||
according to the value from this register.
|
||||
|
||||
config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
|
||||
bool "Disable device boot on power plug-in"
|
||||
depends on PMIC_RK8XX
|
||||
default n
|
||||
---help---
|
||||
Say Y here to prevent the device from booting up because of a plug-in
|
||||
event. When set, the device will boot briefly to determine why it was
|
||||
powered on, and if it was determined because of a plug-in event
|
||||
instead of a button press event it will shut back off.
|
||||
|
||||
config ROCKCHIP_STIMER
|
||||
bool "Rockchip STIMER support"
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ int board_usb_init(int index, enum usb_init_type init)
|
|||
}
|
||||
otg_data.regs_otg = ofnode_get_addr(node);
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_RK3288
|
||||
#ifdef CONFIG_ROCKCHIP_USB2_PHY
|
||||
int ret;
|
||||
u32 phandle, offset;
|
||||
ofnode phy_node;
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@ def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, tee_file_name, dtbs_file
|
|||
num_segments = len(segments)
|
||||
|
||||
if tee_file_name:
|
||||
tee_segments = unpack_elf(tee_file_name)
|
||||
tee_segments = unpack_tee_file(tee_file_name)
|
||||
for index, entry, paddr, data in tee_segments:
|
||||
append_tee_node(fit_file, num_segments + index + 1, paddr, entry)
|
||||
num_segments = num_segments + len(tee_segments)
|
||||
|
|
@ -169,7 +169,7 @@ def generate_atf_binary(bl31_file_name):
|
|||
|
||||
def generate_tee_binary(tee_file_name):
|
||||
if tee_file_name:
|
||||
for index, entry, paddr, data in unpack_elf(tee_file_name):
|
||||
for index, entry, paddr, data in unpack_tee_file(tee_file_name):
|
||||
file_name = 'tee_0x%08x.bin' % paddr
|
||||
with open(file_name, "wb") as atf:
|
||||
atf.write(data)
|
||||
|
|
@ -194,6 +194,31 @@ def unpack_elf(filename):
|
|||
segments.append((index, e_entry, p_paddr, p_data))
|
||||
return segments
|
||||
|
||||
def unpack_tee_file(filename):
|
||||
if filename.endswith('.elf'):
|
||||
return unpack_elf(filename)
|
||||
with open(filename, 'rb') as file:
|
||||
bin = file.read()
|
||||
segments = []
|
||||
if bin[0:5] == b'OPTE\x01':
|
||||
# OP-TEE v1 format (tee.bin)
|
||||
init_sz, start_hi, start_lo, _, paged_sz = struct.unpack_from('<5I',
|
||||
bin,
|
||||
0x8)
|
||||
if paged_sz != 0:
|
||||
raise ValueError("OP-TEE paged mode not supported")
|
||||
e_entry = (start_hi << 32) + start_lo
|
||||
p_addr = e_entry
|
||||
p_data = bin[0x1c:]
|
||||
if len(p_data) != init_sz:
|
||||
raise ValueError("Invalid file '%s': size mismatch "
|
||||
"(expected %d, have %d)" % (filename, init_sz,
|
||||
len(p_data)))
|
||||
segments.append((0, e_entry, p_addr, p_data))
|
||||
else:
|
||||
raise ValueError("Unknown format for TEE file '%s'" % filename)
|
||||
return segments
|
||||
|
||||
def main():
|
||||
uboot_elf = "./u-boot"
|
||||
fit_its = sys.stdout
|
||||
|
|
@ -210,11 +235,13 @@ def main():
|
|||
logging.warning(' Please read Building section in doc/README.rockchip')
|
||||
|
||||
if "TEE" in os.environ:
|
||||
tee_elf = os.getenv("TEE")
|
||||
tee_file = os.getenv("TEE")
|
||||
elif os.path.isfile("./tee.bin"):
|
||||
tee_file = "./tee.bin"
|
||||
elif os.path.isfile("./tee.elf"):
|
||||
tee_elf = "./tee.elf"
|
||||
tee_file = "./tee.elf"
|
||||
else:
|
||||
tee_elf = ""
|
||||
tee_file = ""
|
||||
|
||||
opts, args = getopt.getopt(sys.argv[1:], "o:u:b:t:h")
|
||||
for opt, val in opts:
|
||||
|
|
@ -225,16 +252,16 @@ def main():
|
|||
elif opt == "-b":
|
||||
bl31_elf = val
|
||||
elif opt == "-t":
|
||||
tee_elf = val
|
||||
tee_file = val
|
||||
elif opt == "-h":
|
||||
print(__doc__)
|
||||
sys.exit(2)
|
||||
|
||||
dtbs = args
|
||||
|
||||
generate_atf_fit_dts(fit_its, bl31_elf, tee_elf, uboot_elf, dtbs)
|
||||
generate_atf_fit_dts(fit_its, bl31_elf, tee_file, uboot_elf, dtbs)
|
||||
generate_atf_binary(bl31_elf)
|
||||
generate_tee_binary(tee_elf)
|
||||
generate_tee_binary(tee_file)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ CONFIG_TPL_OF_CONTROL=y
|
|||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_TPL_OF_PLATDATA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_TPL_DM=y
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ CONFIG_CMD_CACHE=y
|
|||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_PARTITIONS is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
|
|||
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x8000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
|
||||
|
|
@ -22,7 +23,6 @@ CONFIG_MISC_INIT_R=y
|
|||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_TPL=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
|
|||
|
|
@ -42,6 +42,8 @@ CONFIG_AHCI_PCI=y
|
|||
CONFIG_SATA_SIL=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_MMC_DW=y
|
||||
|
|
|
|||
|
|
@ -6,10 +6,82 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dm/lists.h>
|
||||
#include <errno.h>
|
||||
#include <log.h>
|
||||
#include <power/rk8xx_pmic.h>
|
||||
#include <power/pmic.h>
|
||||
#include <sysreset.h>
|
||||
|
||||
static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type)
|
||||
{
|
||||
struct rk8xx_priv *priv = dev_get_priv(dev->parent);
|
||||
|
||||
if (type != SYSRESET_POWER_OFF)
|
||||
return -EPROTONOSUPPORT;
|
||||
|
||||
switch (priv->variant) {
|
||||
case RK805_ID:
|
||||
case RK808_ID:
|
||||
case RK816_ID:
|
||||
case RK818_ID:
|
||||
pmic_clrsetbits(dev->parent, REG_DEVCTRL, 0, BIT(0));
|
||||
break;
|
||||
case RK809_ID:
|
||||
case RK817_ID:
|
||||
pmic_clrsetbits(dev->parent, RK817_REG_SYS_CFG3, 0,
|
||||
BIT(0));
|
||||
break;
|
||||
default:
|
||||
printf("Unknown PMIC RK%x: Cannot shutdown\n",
|
||||
priv->variant);
|
||||
return -EPROTONOSUPPORT;
|
||||
};
|
||||
|
||||
return -EINPROGRESS;
|
||||
}
|
||||
|
||||
static struct sysreset_ops rk8xx_sysreset_ops = {
|
||||
.request = rk8xx_sysreset_request,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(rk8xx_sysreset) = {
|
||||
.name = "rk8xx_sysreset",
|
||||
.id = UCLASS_SYSRESET,
|
||||
.ops = &rk8xx_sysreset_ops,
|
||||
};
|
||||
|
||||
/* In the event of a plug-in and the appropriate option has been
|
||||
* selected, we simply shutdown instead of continue the normal boot
|
||||
* process. Please note the rk808 is not supported as it doesn't
|
||||
* have the appropriate register.
|
||||
*/
|
||||
void rk8xx_off_for_plugin(struct udevice *dev)
|
||||
{
|
||||
struct rk8xx_priv *priv = dev_get_priv(dev);
|
||||
|
||||
switch (priv->variant) {
|
||||
case RK805_ID:
|
||||
case RK816_ID:
|
||||
case RK818_ID:
|
||||
if (pmic_reg_read(dev, RK8XX_ON_SOURCE) & RK8XX_ON_PLUG_IN) {
|
||||
printf("Power Off due to plug-in event\n");
|
||||
pmic_clrsetbits(dev, REG_DEVCTRL, 0, BIT(0));
|
||||
}
|
||||
break;
|
||||
case RK809_ID:
|
||||
case RK817_ID:
|
||||
if (pmic_reg_read(dev, RK817_ON_SOURCE) & RK8XX_ON_PLUG_IN) {
|
||||
printf("Power Off due to plug-in event\n");
|
||||
pmic_clrsetbits(dev, RK817_REG_SYS_CFG3, 0,
|
||||
BIT(0));
|
||||
}
|
||||
break;
|
||||
default:
|
||||
printf("PMIC RK%x: Cannot read boot reason.\n",
|
||||
priv->variant);
|
||||
}
|
||||
}
|
||||
|
||||
static struct reg_data rk817_init_reg[] = {
|
||||
/* enable the under-voltage protection,
|
||||
|
|
@ -61,7 +133,7 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
|
|||
static int rk8xx_bind(struct udevice *dev)
|
||||
{
|
||||
ofnode regulators_node;
|
||||
int children;
|
||||
int children, ret;
|
||||
|
||||
regulators_node = dev_read_subnode(dev, "regulators");
|
||||
if (!ofnode_valid(regulators_node)) {
|
||||
|
|
@ -72,6 +144,14 @@ static int rk8xx_bind(struct udevice *dev)
|
|||
|
||||
debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
|
||||
|
||||
if (CONFIG_IS_ENABLED(SYSRESET)) {
|
||||
ret = device_bind_driver_to_node(dev, "rk8xx_sysreset",
|
||||
"rk8xx_sysreset",
|
||||
dev_ofnode(dev), NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
children = pmic_bind_children(dev, regulators_node, pmic_children_info);
|
||||
if (!children)
|
||||
debug("%s: %s - no child found\n", __func__, dev->name);
|
||||
|
|
@ -163,6 +243,8 @@ static int rk8xx_probe(struct udevice *dev)
|
|||
pmic_reg_read(dev, on_source),
|
||||
pmic_reg_read(dev, off_source));
|
||||
printf("\n");
|
||||
if (CONFIG_IS_ENABLED(ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
|
||||
rk8xx_off_for_plugin(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ config USB_GADGET_PRODUCT_NUM
|
|||
hex "Product ID of the USB device"
|
||||
default 0x1010 if ARCH_SUNXI
|
||||
default 0x310a if ROCKCHIP_RK3036
|
||||
default 0x300a if ROCKCHIP_RK3066
|
||||
default 0x310c if ROCKCHIP_RK3128
|
||||
default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288
|
||||
default 0x330a if ROCKCHIP_RK3328
|
||||
|
|
|
|||
|
|
@ -42,6 +42,12 @@ struct rockchip_usb2_phy_dt_id {
|
|||
const void *data;
|
||||
};
|
||||
|
||||
static const struct rockchip_usb2_phy_cfg rk3066a_pdata = {
|
||||
.port_reset = {0x00, 12, 12, 0, 1},
|
||||
.soft_con = {0x08, 2, 2, 0, 1},
|
||||
.suspend = {0x08, 8, 3, (0x01 << 3), (0x2A << 3)},
|
||||
};
|
||||
|
||||
static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
|
||||
.port_reset = {0x00, 12, 12, 0, 1},
|
||||
.soft_con = {0x08, 2, 2, 0, 1},
|
||||
|
|
@ -49,6 +55,8 @@ static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
|
|||
};
|
||||
|
||||
static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
|
||||
{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
|
||||
{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3288_pdata },
|
||||
{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
|
||||
{}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,9 +15,6 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
|
||||
#define CONFIG_SPL_STACK 0x10081fff
|
||||
|
||||
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
|
||||
#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x60000000
|
||||
#define SDRAM_BANK_SIZE (512UL << 20UL)
|
||||
#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
|
||||
|
|
|
|||
|
|
@ -16,8 +16,6 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
|
||||
|
||||
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
|
||||
#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
|
||||
#define CONFIG_IRAM_BASE 0x10080000
|
||||
|
||||
/* spl size 32kb sram - 2kb bootrom */
|
||||
|
|
|
|||
|
|
@ -16,8 +16,6 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR 0x61100000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x100000
|
||||
|
||||
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
|
||||
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
|
||||
#define CONFIG_IRAM_BASE 0x10080000
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x60000000
|
||||
|
|
|
|||
|
|
@ -214,6 +214,9 @@ enum {
|
|||
#define RK817_ON_SOURCE 0xf5
|
||||
#define RK817_OFF_SOURCE 0xf6
|
||||
|
||||
#define RK8XX_ON_PWRON BIT(7)
|
||||
#define RK8XX_ON_PLUG_IN BIT(6)
|
||||
|
||||
struct reg_data {
|
||||
u8 reg;
|
||||
u8 val;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue