As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the
common driver. Currently AR8031_driver didn't work for AR8033,
hence updated it to have it work on AR8031/AR8033.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
The fec_halt() never free'd both RX and TX DMA descriptors that
were allocated in fec_init(), nor did it free the RX buffers.
Rework the FEC driver so that these descriptors and buffers are
allocated only once in fec_probe().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced personality of T1040 with less cores(2 cores)
-T1022:Reduced personality of T1040 with 2 cores and without L2 switch
Update defines in arch/powerpc header files, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefiles]
Acked-by: York Sun <yorksun@freescale.com>
The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade. It is now
causing build issues. Instead of wasting time on things nobody is
interested in any more, we rather drop this board.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@grandegger.com>
cc: Tom Rini <trini@ti.com>
Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
board/compulab/cm_t35/Makefile
board/corscience/tricorder/Makefile
board/ppcag/bg0900/Makefile
drivers/bootcount/Makefile
include/configs/omap4_common.h
include/configs/pdnb3.h
Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:
board/compulab/common/Makefile
board/udoo/Makefile
include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.
include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.
Note: 'git show' will also list two files just because
they are new:
include/configs/am335x_igep0033.h
include/configs/omap3_igep00x0.h
On relatively slow boards (such as the MIPS Malta with an FPGA core
card) it can be extremely common for transmits to underflow - to the
point where it appears they simply do not work at all. Setting the
NOUFLO bit causes the ethernet controller to not begin transmission on
the wire until a transmit start point is reached. Setting that transmit
start point to the full packet will cause the controller to only
transmit the packet once it has buffered it entirely thus preventing any
transmit underflows from occuring and allowing the controller to
function on slower boards.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Ensure that the view of memory from the CPU & the ethernet controller is
coherent at the various points where they exchange data. This prevents
stale data from being transmitted or received, and prevents the driver
from getting stuck waiting for the ethernet controller to update
descriptors when in reality it has but the old values are being read
from cache.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fix up the code to match Documentation/CodingStyle. This is mostly
removing extraneous spaces.
No functional change is intended.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Netconsole loses the second character when used as input by
either setenv stdin nc or setenv stdin serial,nc if using CONSOLE_CONSOLE_MUX
Before a nc_send_packet() to echo the input, a check is done to see if
nc_ether is valid. If its not, it waits for an arp request and then sends
the packet (which contains the first character of line to be displayed as
output). As part of reaping the arp request, the second character is consumed.
We protect this by making the call to NetLoop(NETCONS) between
input_recursion.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Get DMA bus width from design config register
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This can be useful if one wants to disable an interface in u-boot
because u-boot should not manage it but then later reenable it for FDT
fixing or if the kernel uses this interface.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix conflict in fm_eth.h]
Acked-by: York Sun <yorksun@freescale.com>
T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.
T1040QDS board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch
- Four 1 Gbps Ethernet controllers
- SERDES Connections, 8 lanes supporting:
— PCI Express: supporting Gen 1 and Gen 2;
— SGMII
— QSGMII
— SATA 2.0
— Aurora debug with dedicated connectors
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 8-bit, async, up to 2GB.
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- GASIC: Simple (minimal) target within Qixis FPGA
- PromJET rapid memory download support
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- QIXIS System Logic FPGA
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- Video
- DIU supports video at up to 1280x1024x32bpp
- USB
- Supports two USB 2.0 ports with integrated PHYs
— Two type A ports with 5V@1.5A per port.
— Second port can be converted to OTG mini-AB
- SDHC
- SDHC port connects directly to an adapter card slot, featuring:
- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
— Supporting eMMC memory devices
- SPI
- On-board support of 3 different devices and sizes
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: York Sun <yorksun@freescale.com>
Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.
QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
1. Confirm whether QSGMII Riser Card is used.
2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.
However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
if phy_connect() did not find a phy, phydev is NULL and
following code in cpsw_phy_init() crashes. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Performing tftp transfers on mx28 results in random timeouts.
Hector Palacios and Robert Hodaszi analyzed the root cause being related to the
wrong alignment of the 'buff' buffer inside fec_recv().
Benoît Thébaudeau provided an excellent analysis of the alignment bug that is
present on older versions, such as GCC 4.5.4:
http://marc.info/?l=u-boot&m=137942904906131&w=2
Use ALLOC_CACHE_ALIGN_BUFFER() to avoid alignment issues from older GCC
versions.
Reported-by: Hector Palacios <hector.palacios@digi.com>
Tested-by: Oliver Metz <oliver@freetz.org>
Tested-by: Hector Palacios <hector.palacios@digi.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
Similarly as mx25 and mx53, mx6solo-lite needs to setup the MII gasket for RMII
mode.
Add support for mx6solo-lite.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The SPDX License List version 1.19 now contains an official entry for
the IBM-pibs license. However, instead of our suggestion "ibm-pibs",
the SPDX License List uses "IBM-pibs", with the following rationale:
"The reason being that all other SPDX License List short identifiers
tend towards using capital letters unless spelling a word. I'd prefer
to be consistent to this end".
Change the license IDs to use the official name.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix various misspellings of things like "environment", "kernel",
"default" and "volatile", and throw in a couple grammar fixes.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
fix the following building warning
---8>---
macb.c: In function 'macb_init':
macb.c:400:14: warning: 'phydev' may be used uninitialized in this function
macb.c:377:21: note: 'phydev' was declared here
---<8---
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Without this change, the following message is generated:
Warning: FEC using MAC address from net device
See doc/README.enetaddr for details.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN.
3. fix dtb for QSGMII interface.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
This commit adapts the files that were derived from PIBS (PowerPC
Initialization and Boot Software) codeto using SPDX License
Identifiers.
So far, SPDX has not assigned an official License ID for the PIBS
license yet, so this should be considered preliminary.
Note that the following files contained incorrect license information:
arch/powerpc/cpu/ppc4xx/4xx_uart.c
arch/powerpc/cpu/ppc4xx/start.S
arch/powerpc/include/asm/ppc440.h
These files included, in addition to the GPL-2.0 / ibm-pibs dual
license as inherited from PIBS, a GPL-2.0+ license header which was
obviously incorrect. This has been removed.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Conflicts:
Licenses/README
Acked-by: Stefan Roese <sr@denx.de>
1. Reformat tx/rx descriptor as an uniform struct.
2. Replace uint32_t[2] with uint64_t for descriptor control.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Joe Hershberger <joe.hershberger@gmail.com>
This patch adds support for Realtek PHY modules RTL8211DN and
RTL8211E (variants: RTL8211E-VB-CG, RTL8211E-VL-CG, RTL8211EG-VB-CG),
which can be found on Freescale's T1040RDB boards.
To make the driver more generic across 8211 family, a generic name 8211x
is added for macros and function names.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Use ARRAY_SIZE instead of having similar implementation in each drivers.
The NUMELEMS defined in drivers/net/npe/include/IxOsalTypes.h is not used
at all, so this patch removes it instead of converting it to use ARRAY_SIZE.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Fixup an easy conflict over adding the clk_get prototype and USB_OTG
defines for am33xx having moved.
Conflicts:
arch/arm/include/asm/arch-am33xx/hardware.h
Signed-off-by: Tom Rini <trini@ti.com>
FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even
remote. In case none of them is defined, set it to null.
Signed-off-by: York Sun <yorksun@freescale.com>
accessing a lan9303 switch with the cpsw driver results in wrong
speed detection, as the switch sets the BMSR_ERCAP in BMSR
register, and follow read of the MII_STAT1000 register fails, as
the switch does not support it. Current code did not check,
if a phy_read() fails ... fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
BD ram address may vary in various SOC, so removing the hardcoding and
passing the same information through platform data
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
There is no reason to wait for the entire frame to start DMA on receive,
so enable rx cut-thru for better performance.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The pcnet driver uses the pci_phys_to_mem function
to get the memory address of the DMA buffers. This
This assumes an 1:1 mapping between the PCI and
physical memory which is not true on all platforms.
On MIPS platform U-Boot is running within a mapped
memory region, and the pci_phys_to_mem macro can't
be used to obtain the memory address of the buffers.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Commit de1d786e (add support for Xilinx 1000BASE-X phy (GTX)) introduced the
checking for ESTATUS_1000_XHALF, but it incorrectly sets the
SUPPORTED_1000baseX_Full flag in this case.
Set the SUPPORTED_1000baseX_Half flag instead.
Acked-by: Charles Coldwell <coldwell@gmail.com>
Reviewed-By: Sascha Silbe <t-uboot@infra-silbe.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
de1d786 [add support for Xilinx 1000BASE-X phy (GTX)] introduced a
check for the extended status register in order to support
1Gbps-capable PHYs that don't have the 1000BASE-T registers. Since
Extended Status only indicates what the PHY (i.e. the local side) is
capable of, this broke communication with non-1Gbps peers.
Only check the extended status if the 1000BASE-T registers are
actually missing so we don't end up setting speed to 1Gbps even though
the previous test (for the combination of local and peer support for
1Gbps) already indicated we can't do 1Gbps with the current peer.
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.
Conflicts:
arch/arm/dts/exynos5250.dtsi
Signed-off-by: Tom Rini <trini@ti.com>
The MX28 multi-layer AHB bus can be too slow and trigger the
FEC DMA too early, before all the data hit the DRAM. This patch
ensures the data are written in the RAM before the DMA starts.
Please see the comment in the patch for full details.
This patch was produced with an amazing help from Albert Aribaud,
who pointed out it can possibly be such a bus synchronisation
issue.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Remove incorrectly called and duplicate flush_dcache_range() call
from fec_mxc driver. The call is not needed, since the caches are
already flushed in fec_tbd_init(), moreover the second argument should
be the ending address, not size.
Signed-off-by: Marek Vasut <marex@denx.de>
Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
add atheros ar803x phy, used on the upcoming siemens boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
add natsemi dp83630 phy, used on the upcoming siemens boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Using CONFIG_AT91FAMILY replace #ifdeferry for atmel SoC
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
The device interface is 16 bits wide.
All the available packets are read from the incoming fifo.
Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it>
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
[voice.shen@atmel.com: address comments from review results]
[voice.shen@atmel.com: clean up for submit]
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
commit 39695029bc15041c809df3db4ba19bd729c447fa
Author: Charles Coldwell <coldwell@ll.mit.edu>
Date: Tue Feb 19 08:27:33 2013 -0500
Changes to support the Xilinx 1000BASE-X phy (GTX/MGT)
Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>
Add support for Micrel PHY KSZ9031 in phylib,
including small rework for KSZ9021 to avoid
code duplication
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Joe Herschberger <joe.hershberger@gmail.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their
respective phys. Currently there is a fixed configuration in which only a
particular MAC can use the MDIO lines.
Call an arch specific function to take control of specific mdio lines at
runtime.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This patch adds support for the WEMAC, the ethernet controller included
in the Allwinner A10 SoC. It will get used in the upcoming A10 board
support.
From: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
This patch adds FEC support for Vybrid VF610 platform.
In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
and slot2
- Configure MDIO for 10Gig Mac
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
MAC node disabled incorrectly.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reported-by: John Traill <john.traill@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO
Do not enable emio for this standard board configuration for now.
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Pass the PHY address to the driver init to
allow parallel use of both interfaces
Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.
This patch solves the problem with repeatable tftp transfers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Removing this bit causes that frame is sent only once.
(With wrap big one packet has been sent several times
which dramatically decrease throughput)
TRM: (Table 16-3: Tx Buffer Descriptor Entry)
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
This phy is used on zedboard (xilinx zynq platform).
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.
Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: York Sun <yorksun@freescale.com>
- In arch/arm/cpu/armv7/omap-common/timer.c,
drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files
that the driver needs but had been relying on <config.h> to bring in.
- In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h>
- In am335x_evm.h and pcm051.h don't globally include
<asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h>
as that is the only include which defines things the config uses.
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these
conflicts manually and comment the #else/#endif lines for clarity.
Conflicts:
arch/arm/include/asm/arch-davinci/gpio.h
drivers/gpio/da8xx_gpio.c
Signed-off-by: Tom Rini <trini@ti.com>
Before submitting packets to cpdma, phy status is updated on every packet
which leads to delay in packet send intern reduces the Ethernet performance.
Checking mdio status for each packet will reduce timetaken to send a packet
and there by increasing the Ethernet performance. With this the performance
is increased from 208KiB/s to 375KiB/s on EVMsk
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
It is useful to be able to try a range of
possible phy addresses to connect.
Also, an ethernet device is not required
to use phy_find_by_mask leading to better
separation of mii vs ethernet, as suggested
by Andy Fleming.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Only the hardware ethernet registers are needed
for this function, so don't pass the more general
structure. I'm trying to separate MII and fec.
This also fixes MX28 fec_mii_setspeed use on secondary ethernet port
This was found by inspection of the code and should be
checked on real hardware.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
It is more logical to test for CONFIG_FEC_MXC_PHYADDR
to determine whether to define the function fecmxc_initialize.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
SH7752 has two fast ethernet controllers and two gigabit ethernet
controllers. It is similar to SH7757.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marvell 88E1118R has different uid then 88E1118.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Andy Fleming <afleming@freescale.com>
CC: Zang Roy-R61911 <tie-fei.zang@freescale.com>
CC: Kumar Gala <galak@kernel.crashing.org>
In e1000e driver, Rx descriptor queue is used such that hardware can add only
one descriptor at a time. So the WTHRESH granularity in RXDCTL should be set
to single descriptor. This would ensure that every time controller fills a Rx
descriptor, it is flushed to host memory. Earlier this granularity was in
cache line units i.e 2 descriptors. This leads to controller always waiting
for 2 descriptors before flushing them out. But since not more than one Rx BD
is actually available , the accumulation condition never gets hit.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static?
bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static?
bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static?
arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static?
arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static?
arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static?
atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static?
net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static?
net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static?
ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static?
ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static?
tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static?
tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static?
eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static?
Note: in the ping.c fix, commit a36b12f95a
"net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING
clause from when it was necessary to avoid warnings when it was embedded
in net.c.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives. Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h. They come with 'const' added for some swab functions, so
fix those up, too:
include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]
Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).
We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:
macb.c:54:0: warning: "barrier" redefined [enabled by default]
In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)). This fixes
arch/powerpc/lib/bootm.c:
bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token
powerpc sparse builds yield:
include/common.h:356:22: error: marked inline, but without a definition
the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'
also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]
and:
Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here
and:
In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>
TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.
struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The following warning was produced, fix it:
mcfmii.c: In function 'mcffec_miiphy_write':
mcfmii.c:318:8: warning: variable 'rdreg' set but not used [-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com>
Cc: Jason Jin <jason.jin@freescale.com>
As the board seems to be unmaintained for some time, lets remove
the support in mainline completely.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: James MacAulay <james.macaulay@amirix.com>
Acked-by: Marek Vasut <marex@denx.de>
The mechanism waiting for transmission to finish in fec_send() now
relies on the E-bit being cleared in the TX buffer descriptor. In
case of data cache being on, this means invalidation of data cache
above this TX buffer descriptor on each test for the E-bit being
cleared.
Apparently, there is another way to check if the transmission did
complete. This is by checking the TDAR bit in the X_DES_ACTIVE
register. Reading a register does not need any data cache invalidation,
which is beneficial.
Rework the sequence that wait for completion of the transmission so that
the TDAR bit is tested first and afterwards check the E-bit being clear.
This cuts down the number of cache invalidation calls to one.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
The FEC hardware sometimes errors out on data transfer and hangs in
the tightloop adjusted by this patch. So add timeout into the tightloop
to make such a hang recoverable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Align the address that's to be invalidated/flushed properly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Benoit Thebaudeau <benoit.thebaudeau@advans>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Do not pass unaligned RX buffer to the upper layers. The upper layer,
especially in the ARP case, recycles the buffer and passes it back into
the FEC, into it's TX path. With caches enabled, the FEC hangs on this
from time to time.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Benoit Thebaudeau <benoit.thebaudeau@advans>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
-VSC8662 is Dual Port 10/100/1000Base-T Phy,
100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy.
-Its register set and features are similar to
other Vitesse Phys
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This patch add support for the configuration of an external switch from
the 88E6xxx series from Marvell trough an MDIO link using indirect
adressing. This can be used if we do not want to use an EEPROM for the
configuration.
This driver is not generic and was not tested on other switches than the
88e6352. This is proposed as a first implementation that is somewhat
limited but works and that can be used as a basis for further
developments for this switch family.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
Device driver for Zynq Gem IP.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Check the incoming packets' source IP address... if ncip isn't set to a
broadcast address, only listen to the client at ncip.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Refresh the netconsole settings from the env before each packet instead
of only on netconsole init.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Previously u-boot would initialize the network interface for every
network operation and then shut it down again. This makes sense for
most operations where the network in not known to be needed soon after
the operation is complete. In the case of netconsole, it will use the
network for every interaction with the shell or every printf. This
means that the network is being reinitialized very often. On many
devices, this intialization is very slow.
This patch checks for consecutive netconsole actions and leaves the
ethernet hardware initialized between them. It will still behave the
same old way for all other network operations and any time another
network operation happens between netconsole operations.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Allow a board to configure a larger buffer for netconsole, but leave
the default.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
R8A7740 of rmobile has ethernet device, and this is same IP of
sh-ether. This support R8A7740 of rmobile.
Signed-off-by: Hideyuki Sano <hideyuki.sano.dn@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Apply the following questionable adjustment to silence GCC.
armada100_fec.c: In function ‘armdfec_send’:
armada100_fec.c:589:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Support new CONFIG_OF_CONTROL option where device
probing is done based on device tree description.
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: U-Boot DM <u-boot-dm@lists.denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
It is desirable to use different port numbers for sending and receiving
packets with netconsole in the case where you have more than one device
on the local subnet with netconsole enabled for broadcast. When they
use the same port for both, any output from one will look like input to
the other. This is typlically not desirable.
This patch allows the input and output ports to be specified separately
in the environment.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
greth.c: In function ‘greth_recv’:
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘unsigned int’ [-Wformat]
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘unsigned int’ [-Wformat]
greth.c:541:6: warning: pointer targets in assignment differ in signedness [-Wpointer-sign]
greth.c: In function ‘greth_initialize’:
greth.c:623:2: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:655:3: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:684:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: u-boot-dm@lists.denx.de
* 'master' of git://git.denx.de/u-boot-avr32:
net:macb: add line break
avr32:portmux: fix setup for macb1
avr32: Remove redundant LDSCRIPT definition
Signed-off-by: Wolfgang Denk <wd@denx.de>
Without this patch we see annoying output like this:
---8<---
U-Boot> dhcp
macb1: PHY not foundmacb0: PHY present at 1
macb0: Starting autonegotiation...
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
cc: Joe Hershberger <joe.hershberger@gmail.com>
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
CPSW is an on-chip ethernet switch that is found on various SoCs from Texas
Instruments. This patch adds a simple driver (based on the Linux driver) for
this hardware module.
This patch also adds support to clean and flush dcache during packet send
and receive.
Changes by Sandhya: Added support to clean and flush dcache during packet
send/receive and added timeouts.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
[Ilya: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
These are not supported as individual build targets, but instead
are supported by another target.
The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
* 'next' of git://git.denx.de/u-boot:
MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
doc: cleanup - move board READMEs into respective board directories
net: sh_eth: add support for SH7757's GETHER
net: sh_eth: modify the definitions of regsiter
net: sh_eth: add SH_ETH_TYPE_ condition
net: sh_eth: clean up for the SH7757's code
net: fec_mxc: Fix MDC for xMII
net: fec_mxc: Fix setting of RCR for xMII
net: nfs: make NFS_TIMEOUT configurable
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <wd@denx.de>
SH7757 has 2 ETHERs and 2 GETHERs. This patch supports the SH7757's
GETHER. If CONFIG_SH_ETHER_USE_GETHER is defined using SH7757,
the driver handles the GETHER.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The previous code had many similar definitions in each CPU.
This patch borrows from the sh_eth driver of Linux kernel.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
At the moment, the driver supports the following CPUs:
- GETHER (Gigabit Ethernet) : SH7763, SH7734
- ETHER (Fast Ethernet) : SH7724, SH7757
And the driver had the following "#if":
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
- Those are for GETHER
#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
- This is for ETHER
So, for clean up the code, this patch adds SH_ETH_TYPE_GETHER and
SH_ETH_TYPE_ETHER. And then, the patch modifies the above "#if".
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The SH7757's ETHER can work using the SH7724's setting. So, the patch
modifies it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so
mii_speed has to be set for all these interfaces, and not only for MII.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
At least on i.MX25, the RMII mode did not work, which is fixed by this patch.
The MII_MODE bit of the FEC RCR register means xMII, i.e. 'not 7-wire', so set
it accordingly.
According to the xMII and 7-wire (aka GPSI) standards, full duplex should be
available on xMII, but not on 7-wire, so set FCE accordingly. The FEC may
support full duplex for 7-wire too, but the reference manual does not say that,
so avoid an invalid assumption. Actually, the choice between half and full
duplex also depends on the endpoint/switch/repeater configuration, so a config
option could be added for that, but there has been no need for it so far.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Now that common code doesn't declare these as volatile, we don't need to
either anymore. This fixes the build warning:
bfin_mac.c: In function 'bfin_EMAC_recv':
bfin_mac.c:193:23: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 'next' of git://git.denx.de/u-boot-net:
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is an add-on to f6c4191f. There are a few registers where
consecutive writes to the same location should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers:
Registers 0-3 All bits
Registers 6-7 All bits
Register 10 All bits
Register 11 All bits except for 5-6.
Registers 16-47 All bits
Register 48 All bits except for 18-16, 14.
Register 448 Bit 4.
Register 459 Bits 0-3.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Matthew Gerlach <mgerlach@altera.com>
Acked-by: Amit Virdi <amit.virdi@st.com>
Micrel accidentally used the same part number
for the KS8721 and KSZ9021. So, both cannot be
in the same build of u-boot. Add a config option
to handle this.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Nobuhiro Iwamamatsu <nobuhiro.iwamatsu.yj@renesas.com> (sh_eth part)
Acked-by: Stephan Linz <linz@li-pro.net> (Xilinx part, xilinx_axi_emac and xilinx_ll_temac)
Reviewed-by: Marek Vasut <marex@denx.de> (FEC part)
phy_startup() calls the PHY driver's startup function, but it ignores the
return code from that function, and so it never returns any failures.
Signed-off-by: Timur Tabi <timur@freescale.com>
When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed.
Therefore SH7757 and SH7724 can not build. This revise this probelem.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
This patch adds the following changes to designware ethernet driver
found on the ST SPEAr SoC:
- Don't init MAC & PHY upon startup. This causes a delay, waiting for
the auto negotiation to complete. And we don't want this delay to
always happen. Especially not on platforms where ethernet is not
used at all (e.g. booting via flash).
Instead postpone the MAC / PHY configuration to the stage, where
ethernet is first used.
- Add possibility for board specific PHY init code. This is needed
for example on the X600 board, where the Vitesse PHY needs to be
configured for GMII mode.
This board specific PHY init is done via the function
designware_board_phy_init(). And this driver now adds a weak default
which can be overridden by board code.
- Use common functions miiphy_speed() & miiphy_duplex() to read
link status from PHY.
- Print status and progress of auto negotiation.
- Print link status (speed, dupex) upon first usage.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
Few Designware peripheral registers need to be modified based on the
ethernet interface selected by the board. This patch supports interface
information in ethernet driver
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
On DA850/OMAP-L138 it was observed that in RMII mode,
auto negotiation was not performed. This patch enables
auto negotiation in RMII mode. Without this patch, EMAC
initialization takes more time and sometimes tftp fails
in RMII mode.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
SH7734 support GMII. This add register infomation and the function
which enable GMII.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
SH7734 has one channel ethernet device.
This support 10/100/1000Base, and RMII/MII/GMII.
And this has the same structure as SH7763.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Add several levels of DEBUG prints so that you can limit the noise to
the severety of your problem.
DEBUG_LL_STATE = Link local state machine changes
DEBUG_DEV_PKT = Packets or info directed to the device
DEBUG_NET_PKT = Packets on info on the network at large
DEBUG_INT_STATE = Internal network state changes
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Call a built-in dummy if none is registered... don't require
protocols to register a handler (eliminating dummies)
NetConsole now uses the ARP handler when waiting on arp
(instead of needing a #define hack in arp.c)
Clear handlers at the end of net loop
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Rename IP header related things to IP_UDP. The existing definition
of IP_t includes UDP header, so name it to accurately describe the
structure.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
These are all the files which use the API incorrectly but did not get
built using MAKEALL -a powerpc|arm. I have no compiler for them, but
the remaining issues should be far less than without this patch.
Any outstanding issues are left to the maintainers of boards that use
these drivers.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
rtl8169.c: In function 'rtl8169_initialize':
rtl8169.c:907:13: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
pcnet.c: In function 'pcnet_initialize':
pcnet.c:224:13: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
xilinx_axi_emac.c: In function 'xilinx_axiemac_initialize':
xilinx_axi_emac.c:646: warning: assignment from incompatible pointer type
Signed-off-by: Stephan Linz <linz@li-pro.net>
Fix this:
xilinx_emaclite.c: In function 'xilinx_emaclite_initialize':
xilinx_emaclite.c:371: warning: assignment from incompatible pointer type
Signed-off-by: Stephan Linz <linz@li-pro.net>
Fix this:
xilinx_ll_temac.c: In function 'xilinx_ll_temac_initialize':
xilinx_ll_temac.c:332: warning: assignment from incompatible pointer type
xilinx_ll_temac.c:340: warning: assignment from incompatible pointer type
Signed-off-by: Stephan Linz <linz@li-pro.net>
Fix this:
uli526x.c: In function 'uli526x_initialize':
uli526x.c:243:13: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
tsi108_eth.c: In function 'tsi108_eth_initialize':
tsi108_eth.c:745:13: warning: assignment from incompatible pointer type
tsi108_eth.c: In function 'tsi108_eth_recv':
tsi108_eth.c:989:4: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
rtl8139.c: In function 'rtl8139_initialize':
rtl8139.c:234:13: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
ns8382x.c: In function 'ns8382x_initialize':
ns8382x.c:352:13: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
natsemi.c: In function 'natsemi_initialize':
natsemi.c:338:13: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
eth.c: In function 'fm_eth_initialize':
eth.c:651:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
e1000.c: In function 'e1000_initialize':
e1000.c:5264:13: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix this:
smc91111.c: In function 'smc91111_initialize':
smc91111.c:1363:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
macb.c: In function 'macb_eth_initialize':
macb.c:564:15: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
lan91c96.c: In function 'lan91c96_initialize':
lan91c96.c:811:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
ks8695eth.c: In function 'ks8695_eth_initialize':
ks8695eth.c:236:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
ftmac100.c: In function 'ftmac100_initialize':
ftmac100.c:266:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
fec_mxc.c: In function 'fec_probe':
fec_mxc.c:926:13: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
enc28j60.c: In function 'enc28j60_initialize':
enc28j60.c:967:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
eepro100.c: In function 'eepro100_initialize':
eepro100.c:464:13: warning: assignment from incompatible pointer type
eepro100.c: In function 'eepro100_recv':
eepro100.c:694:4: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type
include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile u8 *'
The use of a descriptor like this may mean DMA will update this at will
Beware this may be a source of trouble on some boards
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
dnet.c: In function 'dnet_eth_initialize':
dnet.c:380:15: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
dm9000x.c: In function 'dm9000_initialize':
dm9000x.c:636:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
dc2114x.c: In function 'dc21x4x_initialize':
dc2114x.c:305:15: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
cs8900.c: In function 'cs8900_initialize':
cs8900.c:326:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
calxedaxgmac.c: In function 'xgmac_rx':
calxedaxgmac.c:479:2: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type
include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile unsigned char *'
calxedaxgmac.c: In function 'calxedaxgmac_initialize':
calxedaxgmac.c:547:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
at91_emac.c: In function 'at91emac_register':
at91_emac.c:524:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix this:
armada100_fec.c: In function 'armada100_fec_register':
armada100_fec.c:723:12: warning: assignment from incompatible pointer type
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix:
4xx_enet.c: In function 'ppc_4xx_eth_initialize':
4xx_enet.c:2029: warning: assignment from incompatible pointer type
Tested on sequoia board.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Anatolij Gustschin <agust@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fixes:
davinci_emac.c: In function 'davinci_emac_initialize':
davinci_emac.c:796:12: warning: assignment from incompatible pointer type [enabled by default]
Tested on da850_am18xxevm
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fixes:
tsec.c: In function 'tsec_initialize':
tsec.c:638:12: warning: assignment from incompatible pointer type
Tested on MPC8313e-RDB
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Fix:
mpc512x_fec.c: In function 'mpc512x_fec_initialize':
mpc512x_fec.c:634: warning: assignment from incompatible pointer type
Tested on mpc5121ads board using tftp and nfs commands.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Fix:
mpc5xxx_fec.c: In function 'mpc5xxx_fec_initialize':
mpc5xxx_fec.c:920: warning: assignment from incompatible pointer type
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Anatolij Gustschin <agust@denx.de>
smc911x.c: In function 'smc911x_initialize':
smc911x.c:288:12: warning: assignment from incompatible pointer type
[enabled by default]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Abstract out common register setup. This also configured r_cntrl
to correct value at registration time.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
locally.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
... after commit "net/miiphy/serial: drop duplicate NAMESIZE
define" (sha1:f6add13) was applied. The building of the new
LL TEMAC network driver fails with error below:
xilinx_ll_temac.c: In function 'xilinx_ll_temac_initialize':
xilinx_ll_temac.c:301: error: 'NAMESIZE' undeclared (first use in this function)
xilinx_ll_temac.c:301: error: (Each undeclared identifier is reported only once
xilinx_ll_temac.c:301: error: for each function it appears in.)
Signed-off-by: Stephan Linz <linz@li-pro.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The new implementation changes the timeout loop implementation to avoid 1 ms
delay in each failing test. It also configures the delay to 10usec.
Signed-off-by: Amit Virdi <amit.virdi@st.com>
This patch forces the advertised capabilities during auto
negotiation to always be 10/100 Mbps and half/full as duplexing.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
If AN(auto-negotiation) is ON, speed bit of control register are not
applicable. Also phy registers were not getting programmed as per the
result of AN. This patch sets only AN bit & restart AN bit for AN ON
selection & programs PHY registers as per AN result.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Phy autonegotiation works only when the ethernet cable is plugged in.
Since the phy was configured only at the init time, a plugged in cable
was necessary to initialize the phy properly.
This patch keeps a flag to check if the phy initialization has
succeeded, and calls configure_phy routine at every init if this flag
reports otherwise.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
The code assumes the phy address to be > 0, which is not true, the phy address
can be in the range 0-31.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
The max frame length for normal descriptor can be 0x7FF i.e 2047. It was wrongly
specified as 2048. Currently, the max descriptor length is around 1500, so
redefining the mask to 1600
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
The network controller mac resets hardware address stored in MAC_HI and MAC_LO
registers if mac is resetted. So, hw mac address needs to be restored in case
mac is explicitly resetted from driver.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Xilinx LocalLink Tri-Mode Ether MAC driver can be
used by Xilinx Microblaze or Xilinx ppc405/440 in
SDMA and FIFO mode. DCR or XPS bus can be used.
The driver uses and requires MII and PHYLIB.
CP: 4 warnings: 'Use of volatile is usually wrong'
I won't fix this, because it depends on the network
driver subsystem.
Reported-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Stephan Linz <linz@li-pro.net>
Some baords may use the GBE interface but they have no
phy connected to the interface and a direct MAC/MAC interface.
For them we need to get rid of compiler warnings.
Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
flush_dcache is not declared in the common.h API,
flush_dcache_range however is
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
flush_dcache is not declared in the common.h API,
flush_dcache_range however is
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
* 'agust@denx.de' of git://git.denx.de/u-boot-staging:
lzma: fix printf warnings
Remove CONFIG_SYS_EXTBDINFO from snapper9260.h
cmd_pxe.c: fix strict-aliasing warnings
net: smc91111: use mdelay()
doc: Fix some typos in different files
disk/part.c: Fix device enumeration through API
mkenvimage: Really set the redundant byte when applicable
mkenvimage: Don't try to detect comments in the input file
mkenvimage: Use mmap() when reading from a regular file
mkenvimage: Read/Write from/to stdin/out by default or if the filename is "-"
mkenvimage: More error handling
mkenvimage: Correct an include and add a missing one
mkenvimage: correct and clarify comments and error messages
MAKEALL: display SPL size if present
ARMV7/Vexpress: add missing get_ticks() and get_tbclk()
mkenvimage: fix usage message
cmd_fat: add FAT write command
fs/fat/fat_write.c: Fix GCC 4.6 warnings
FAT write: Fix compile errors
Ensure that transmit and receive buffers are cache-line aligned.
Invalidate cache for each packet as received, update receive buffer
descriptors one cache line at a time, flush cache before transmitting.
Original patch by Marek:
http://lists.denx.de/pipermail/u-boot/2012-February/117695.html
Signed-off-by: Eric Nelson <eric.nelson at boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
A few subsystems are using the same define "NAMESIZE". This has been
working so far because they define it to the same number. However, I
want to change the size of eth_device's NAMESIZE, so rather than tweak
the define names, simply drop references to it. Almost no one does,
and the handful that do can easily be changed to a sizeof().
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
EDMR_INIT_CNT holds the check count of initialization.
Since there were more same values (1000), this collected as TIMEOUT_CNT.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Boards may have things they want done before or after normal phy config.
Letting the boards call drv->config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Add the gigabit phy KSZ9021.
Also, add function ksz9021_phy_extended_write
/_read for access to the phys extended registers.
The environment variable "disable_giga"
can be used to disable 1000baseTx.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Surround non PHYLIB routines miiphy_restart_aneg
and miiphy_wait_aneg with ifndef CONFIG_PHYLIB.
When later PHYLIB is required it is easy to delete
the non-PHYLIB code. This separation idea
came from Andy Fleming.
fec_miiphy_read, and fec_miiphy_write changed to
fec_phy_read, and fec_phy_write with argument changes.
Deprecated miiphy_register is no longer used. Both
old and new PHYLIB code now use mdio_register.
Cleanup some debug prints.
Inline function fec_miiphy_fec_to_eth is no longer necessary.
Moved to the single call location.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.
This feature is important on mx28 SoC for example that has two FEC ports.
Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This adds ethernet driver for Calxeda xgmac found on Highbank SOC.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Fix: WARNING: __aligned(size) is preferred over
__attribute__((aligned(size)))
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'next' of ../next:
mkenvimage: Add version info switch (-V)
mkenvimage: Fix getopt() error handling
mkenvimage: Fix some typos
phy: add Micrel KS8721BL phy definition
net: introduce per device index
mvgbe: remove setting of ethaddr within the driver
x86: Add support for specifying an initrd with the zboot command
x86: Refactor the zboot innards so they can be reused with a vboot image
x86: Add infrastructure to extract an e820 table from the coreboot tables
x86: Add support for booting Linux using the 32 bit boot protocol
x86: Clean up the x86 zimage code in preparation to extend it
x86: Import code from coreboot's libpayload to parse the coreboot table
x86: Initial commit for running as a coreboot payload
CHECKPATCH: ./board/esd/hh405/logo_320_240_8bpp.c
CHECKPATCH: ./board/esd/hh405/logo_1024_768_8bpp.c
CHECKPATCH: ./board/esd/hh405/logo_320_240_4bpp.c
CHECKPATCH: ./board/esd/hh405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/apc405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/voh405/logo_320_240_4bpp.c
CHECKPATCH: ./board/esd/voh405/logo_640_480_24bpp.c
CHECKPATCH: ./board/esd/hh405/fpgadata.c
CHECKPATCH: ./board/esd/pci405/fpgadata.c
CHECKPATCH: ./board/esd/tasreg/fpgadata.c
CHECKPATCH: ./board/esd/apc405/fpgadata.c
CHECKPATCH: ./board/esd/voh405/fpgadata.c
CHECKPATCH: ./board/esd/ash405/fpgadata.c
CHECKPATCH: ./board/esd/dasa_sim/fpgadata.c
CHECKPATCH: ./board/esd/ar405/fpgadata_xl30.c
CHECKPATCH: ./board/esd/ar405/fpgadata.c
CHECKPATCH: ./board/esd/plu405/fpgadata.c
CHECKPATCH: ./board/esd/wuh405/fpgadata.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci405.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci405ab.c
CHECKPATCH: ./board/esd/cpci405/fpgadata_cpci4052.c
CHECKPATCH: ./board/esd/canbt/fpgadata.c
CHECKPATCH: ./board/esd/du405/fpgadata.c
CHECKPATCH: ./board/esd/cpciiser4/fpgadata.c
CHECKPATCH: ./board/dave/PPChameleonEVB/fpgadata.c
avr32:mmu.c: fix printf() length modifier
fat.c: fix printf() length modifier
cmd_sf.c: fix printf() length modifier
Make printf and vprintf safe from buffer overruns
vsprintf: Move function documentation into header file
Add safe vsnprintf and snprintf library functions
Move vsprintf functions into their own header
Conflicts:
tools/mkenvimage.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
This adds support for the Micrel KS8721BL/SL PHY.
The definition is taken from the correspondent datasheet.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Fix:
e1000_spi.c: In function 'spi_free_slave':
e1000_spi.c:115: warning: unused variable 'hw'
e1000_spi.c: In function 'do_e1000_spi':
e1000_spi.c:472: warning: 'checksum' may be used uninitialized in this function
e1000_spi.c:472: note: 'checksum' was declared here
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
A network driver should not touch the environment at all. This patch fixes
this behaviour by removing the code for setting a default/randomized MAC
address.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Eric Cooper <ecc@cmu.edu>
Cc: Jason Cooper <u-boot@lakedaemon.net>
Cc: Siddarth Gore <gores@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Fix trailing white space, indentation by spaces instead of TABs,
excessive blank lines, trailing blank lines.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
at91_emac.c: In function 'at91emac_phy_init':
at91_emac.c:244:20: warning: variable 'duplex' set but not used
[-Wunused-but-set-variable]
at91_emac.c:244:13: warning: variable 'speed' set but not used
[-Wunused-but-set-variable]
Use new debug_cond() to fix these warnings. In the result, anumber of
inconsistent printf() formats are detected:
at91_emac.c: In function 'at91emac_read':
at91_emac.c:147:2: warning: format '%x' expects argument of type
'unsigned int', but argument 2 has type 'struct at91_emac_t *'
[-Wformat]
at91_emac.c: In function 'at91emac_write':
at91_emac.c:157:2: warning: format '%x' expects argument of type
'unsigned int', but argument 2 has type 'struct at91_emac_t *'
[-Wformat]
at91_emac.c:157:2: warning: format '%x' expects argument of type
'unsigned int', but argument 4 has type 'short unsigned int *'
[-Wformat]
at91_emac.c: In function 'at91emac_recv':
at91_emac.c:451:3: warning: format '%d' expects argument of type
'int', but argument 2 has type 'long unsigned int' [-Wformat]
at91_emac.c:451:3: warning: format '%x' expects argument of type
'unsigned int', but argument 4 has type 'long unsigned int' [-Wformat]
Fix these, too.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Jens Scharsig <js_at_ng@scharsoft.de>
Cc: Andreas Bießmann <andreas.devel@gmail.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
Fix:
ne2000_base.c: In function 'dp83902a_send':
ne2000_base.c:282:7: warning: variable 'tmp' set but not used
[-Wunused-but-set-variable]
ne2000_base.c: In function 'dp83902a_RxEvent':
ne2000_base.c:376:5: warning: variable 'rsr' set but not used
[-Wunused-but-set-variable]
ne2000_base.c: In function 'dp83902a_TxEvent':
ne2000_base.c:513:5: warning: variable 'tsr' set but not used
[-Wunused-but-set-variable]
ne2000_base.c: In function 'dp83902a_ClearCounters':
ne2000_base.c:550:17: warning: variable 'cnt3' set but not used
[-Wunused-but-set-variable]
ne2000_base.c:550:11: warning: variable 'cnt2' set but not used
[-Wunused-but-set-variable]
ne2000_base.c:550:5: warning: variable 'cnt1' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
This fixes the build of the two sh boards shmin and r7780mp and qemu-mips
which currently fail to build due to dropped pre-CONFIG_NET_MULTI code.
This v2 patch minimizes the number of lines in the diff for easy review
and to eliminate any possible accidential changes resulting from moving
lines of code in the file. This also makes the register function very easy.
Any cleanups and improvements are intentionally deferred to follow-up patches
to keep this patch as simple and as easy to review as possible.
A new driver register function, ne2k_register() calls the existing
one-time setup part of the old init function and calls eth_register().
Changes to shmin, r7780mp and qemu-mips:
- Call the new ne2k_register() from board_eth_init() of the boards.
- Tested using qemu-mips board,
- Tested the two renesas / sh boards r7780mp and shmin to compile again,
and should work.
checkpatch-clean when "--ignore VOLATILE" is added to .checkpatch.conf,
and no warnings introduced in none of the three boards using this driver.
Signed-off-by: Bernhard Kaindl <bernhard.kaindl@gmx.net>
Fix:
inca-ip_sw.c: In function 'inca_switch_init':
inca-ip_sw.c:210:6: warning: variable 'v' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix the condition for number of phys in
davinci_eth_phy_detect() function.
CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT indicates number of
phys. From this commit id dc02badab4
davinci emac initilazed one less than the number of phy count.
Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
For some reason code setting the speed based on the PHY feedback causes
troubles on AM3517 so hardcode 100Mbps for now.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache
enabled by default. So we have to take care and flush/invalidate the
cache before/after the DMA operations.
Please note that the receive buffer alignment to 32 byte boundary comes
from the old driver version I don't know if it is really needed or
alignment to cache line size is enough.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
On AM35xx CPPI RAM had different addresses when accessed from the CPU
and from the EMAC. We need to account this to deal with the buffer
descriptors correctly.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs
also. This patch moves common defines from arch-davinci/emac_defs.h to
drivers/net/davinci_emac.h
DaVinci specific PHY drivers hacked to include the new header. We might
want to switch to phylib in future.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
This adds support for the SMSC LAN87xx PHYs.
Following PHYs can be used by set CONFIG_PHY_SMSC to config.
- SMSC LAN8700
- SMSC LAN8710/LAN8720
- SMSC LAN8710/LAN8720
A setup of PHY was copied from linux kenrel.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Fixed white space errors; modified commit message a bit.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The original m88e1111s_config() does not do the SGMII mode
initialization and is buggy. Rewrite the function according to
3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
The sh_eth driver had an own mii functions. However the function
didn't support the gigabit PHY. The U-Boot has the general phy driver
and miiphybb driver, and they already support it.
So this patch removes the own functions and uses the phy driver.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman. Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both. A given SOC will only have
a QE or an Fman, so this is safe.
Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND. There's no way to know by looking at a variable how it's supposed
to be used.
In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
cs8900.c: In function 'get_reg_init_bus':
cs8900.c:69:14: warning: variable 'c' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Fix:
lan91c96.c: In function 'dump_memory_info':
lan91c96.c:157:7: warning: variable 'mem_info' set but not used
[-Wunused-but-set-variable]
lan91c96.c: In function 'smc_send_packet':
lan91c96.c:320:16: warning: variable 'ioaddr' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
device is already in *normal* (D0) mode => it doesn't need to be wake-up.
With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE
bits of PM_CTRL register is in sleep (D1/D2) mode.
Signed-off-by: Bertrand Cachet <bertrand.cachet@heig-vd.ch>
No one uses this driver, and it isn't converted to the NET_MULTI
framework (which we dropped recently), so drop this driver too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Fix the following build warning in drivers/net/e1000.c
e1000.c: In function 'e1000_reset_hw':
e1000.c:1373:11: warning: variable 'icr' set but not used [-Wunused-but-set-variable]
e1000.c: In function 'e1000_phy_init_script':
e1000.c:4395:11: warning: variable 'ret_val' set but not used [-Wunused-but-set-variable]
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Fix:
enc28j60.c: In function 'enc_receive':
enc28j60.c:435:5: warning: variable 'eir_reg' set but not used
[-Wunused-but-set-variable]
enc28j60.c: In function 'enc_poll':
enc28j60.c:503:5: warning: variable 'estat_reg' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Fix:
at91_emac.c: In function 'at91emac_write_hwaddr':
at91_emac.c:477:15: warning: variable 'dev' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Fix:
4xx_enet.c: In function 'ppc_4xx_eth_init':
4xx_enet.c:875:6: warning: variable 'ethgroup' set but not used [-Wunused-but-set-variable]
I used "__maybe_unused" here intentionally, since all other
alternatives to fix this compilation warning would result in more
ifdef's.
Signed-off-by: Stefan Roese <sr@denx.de>
* 'master' of git://git.denx.de/u-boot-arm:
arm, davinci: add DAVINCI_MMC_CLKID
arm, davinci_emac: fix driver bug if more then 3 PHYs are detected
arm, davinci: da850/dm365 lowlevel cleanup
omap5: Add omap5_evm board build support.
omap4/5: Add support for booting with CH.
omap5: emif: Add emif/ddr configurations required for omap5 evm
omap5: clocks: Add clocks support for omap5 platform.
omap5: Add minimal support for omap5430.
omap: Checkpatch fixes
omap4: make omap4 code common for future reuse
GCC4.6: Squash warnings in onenand_base.c
GCC4.6: Fix common/usb.c on xscale
OneNAND: Add simple OneNAND SPL
PXA: vpac270: Enable the new generic MMC driver
PXA: Cleanup serial_pxa
PXA: Drop csb226 and innokom boards (unmaintained)
m28evk: Fix comment about the number of RAM banks
mx31: Fix checkpatch warnings in generic.c
mx31: Use proper IO accessor for GPR register
mx31: Remove duplicate definition for GPR register
qong: Use generic function for configuring GPR register
M28EVK: Enable USB HOST support
iMX28: Add USB HOST driver
iMX28: Add USB and USB PHY register definitions
M28: Add memory detection into SPL
iMX28: Fix ARM vector handling
M28: Add doc/README.m28 documentation
M28: Add MMC SPL
iMX28: Add support for DENX M28EVK board
iMX28: Add u-boot.sb target to Makefile
iMX28: Add image header generator tool
iMX28: Add driver for internal RTC
iMX28: Add GPMI NAND driver
iMX28: Add APBH DMA driver
iMX28: Add SPI driver
iMX28: Add GPIO control
iMX28: Add I2C bus driver
iMX28: Add PINMUX control
FEC: Add support for iMX28 quirks
iMX28: Add SSP MMC driver
iMX28: Initial support for iMX28 CPU
MX25: zmx25: GCC4.6 fix build warnings
da850: add new config file for AM18xx
BeagleBoard: config: Switch to ttyO2
OMAP3: Change omap3_evm maintainer
devkit8000: Fix NAND SPL on boards with 256MB NAND
integrator: enable Vpp and disable flash protection
integrator: add system controller header
integrator: make flash writeable on boot
integrator: use io-accessors for board init
integrator: move text offset to config
integrator: pass configs for core modules
ARM: remove superfluous setting of arch_number in board specific code.
SPL: Allow ARM926EJS to avoid compiling in the CPU support code
integrator: do not test first part of the memory
arm: a320: fix broken timer
ARM: define CONFIG_MACH_TYPE for all ronetix boards
dm646x: pass board revision info to kernel
dm646x: add new configuration for dm6467T
arm, davinci: Fix setting of the SDRAM configuration register
arm, davinci: Remove the duplication of LPSC functions
arm, davinci: Rename AM1808 lowlevel functions to DA850
da8xxevm: fix build error
ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE
since commits:
davinci: emac: add support for more than 1 PHYs
062fe7d332
davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
fb1d6332b5
I get following warning on the enbw_cmc board:
Err: serial
Net: 5 ETH PHY detected
miiphy_register: non unique device name 'KSZ8873 @ 0x01'
DaVinci-EMAC
Hit any key to stop autoboot: 0
Also I see some debug printfs:
=> run load
+ emac_close
+ emac_ch_teardown
- emac_ch_teardown
+ emac_ch_teardown
- emac_ch_teardown
- emac_close
+ emac_open
- emac_open
Using DaVinci-EMAC device
reason is 062fe7d332 new define MAX_PHY.
This is set to 3! I get on this board 5 active phys, so
this leads in wrong memory writes ...
so I changed:
- define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT to set
the MAX_PHY value, add a description in README
for the new CONFIG_SYS option.
- print an error message if more then MAX_PHYs are
detected.
- fill the active_phy_addr array in a for loop with
0xff
- changed printf() in debug_emac()
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Tom Rini <tom.rini@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Fix:
fm.c: In function 'fm_init_common':
fm.c:398:6: warning: variable 'n' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early
verion silicons. This workaround detects if the eTSEC Rx logic is properly
initialized, and reinitialize the eTSEC Rx logic.
Signed-off-by: Gong Chen <g.chen@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 'master' of git://git.denx.de/u-boot-arm:
Arm: re-introduce the MACH_TYPE_XXXXXX for EB_CPUX9K2 board
arm: jadecpu: Readd MACH_TYPE_JADECPU
at91: defined mach-types for otc570 board in board config file
at91: defined mach-types for meesc board in board config file
mx31pdk: Enable D and I caches
ehci-mxc: remove incorrect comment
README: Fix supported i.MX SoC list for CONFIG_MXC_SPI
mx53: Turn off child clocks before reconfigure perclk_root
qong: enable support for compressed images
imx: imx31_phycore.h: fix checkpatch warnings
vision2: Remove unused get_board_rev function
mx53smd: Remove unused get_board_rev function
mx53ard: Remove unused get_board_rev function
mx53evk: Remove unused get_board_rev function
mx53evk: Add RTC support
mx53loco: Remove unused get_board_rev function
mx53evk: Remove unneeded '1' from mx53evk.h
OMAP3: mvblx: Initial support for mvBlueLYNX-X
ARM: dig297: Define MACH_TYPE_OMAP3_CPS and CONFIG_MACH_TYPE
omap3: mem: Move comments next to definitions
omap3: mem: Clean-up whitespaces
omap3: mem: Define and use common macros
Davinci: ea20: added PREBOOT to configuration
Davinci: ea20: added I2C support
Davinci: ea20: added video support
VIDEO: davinci: add framebuffer to da8xx
ARM: Davinci: added missing registers to hardware.h
Davinci: ea20: add gpios for LCD backlight control
Davinci: ea20: add gpio for keeping power on in board_late_init
Davinci: ea20: Add default U-Boot environment
Davinci: ea20: Add early init to get early output from console
Davinci: ea20: Add NAND support
Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
Davinci: ea20: set console on UART0
arm, davinci: add cam_enc_4xx support
arm926ejs, davinci: add missing spi defines for dm365
arm926ejs, davinci: add cpuinfo for dm365
arm, davinci: add lowlevel function for dm365 soc
arm, davinci: add header files for dm365
spl, nand: add 4bit HW ecc oob first nand_read_page function
arm, davinci: add support for new spl framework
spl: add option for adding post memory test to the SPL framework
net, davinci_emac: make clock divider in MDIO control register configurable
arm, usb, davinci: make USBPHY_CTL register configurable
usb, davinci: add enable_vbus() weak function
omap3evm: fix errors caused by multiple definitions
omap3evm: Add (quick) configuration for NAND only
omap3evm: Add (quick) configuration for MMC/SD only
omap3evm: move common config options to new file
omap3evm: Prepare to split configuration
omap3evm: Reorder related config options
omap/spl: actually enable the console
davinci_emac: compilation fix, phy is array now
omap3evm: Set environment variable 'ethaddr'
arm, arm926: fix missing symbols in NAND_SPL mode
arm, davinci: Add function lpsc_syncreset()
arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD
arm/km: portl2 environment address update to P1B
arm/km: adapt bootcounter evaluation
arm/km: enable jffs2 cmds
arm/km: trigger reconfiguration for the Xilinx FPGA
arm/km: add boardid and hwkey to kernel command line
ARM: Reintroduce MACH_TYPE_KM_KIRKWOOD for keymile ARM boards
netspace_v2: enable I2C EEPROM support
netspace_v2: fix SDRAM configuration
armada100: define CONFIG_SYS_CACHELINE_SIZE
pantheon: define CONFIG_SYS_CACHELINE_SIZE
kirkwood: define CONFIG_SYS_CACHELINE_SIZE
kirkwood: drop empty asm-offsets.s file
arm/km/mgcoge3un: enhance "waitforne" feature
arm/km: add variable waitforne to mgcoge3un
gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared
ARM: dreamplug: fix compilation
ARM: DockStar: fix compilation
ARM: netspace_v2: fix warnings
am335x: Drop board_sysinfo struct
am335x: Temporarily add MACH_TYPE define
misc:pmic:samsung Enable PMIC driver at C210 Universal target
dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p UNIVERSAL C210 target
dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p GONI target
smdkv310: use macro for mmc data read function address
smdkv310: use spl framework for mmc spl
SMDKV310: use get_ram_size() to validate dram size
SMDKV310: Initialize board id using CONFIG_MACH_TYPE
ORIGEN : use absolute paths and fix tool naming
ORIGEN : enable device tree support
MX25: tx25: Fix building due to missing MACH_TYPE
mx31: Add board support for HALE TT-01
mx31: add ESD control registers
mx31: define pins and init for UART2 and CSPI3
MX35: add support for flea3 board
MX51: vision2: add MACH_TYPE in config file
vision2: Remove unused header file
mx51evk: Remove unused get_board_rev function
mx51evk: Remove unneeded '1' from mx51evk.h
I2C: Fix mxc_i2c.c problem on imx31_phycore
mx35pdk: Add RTC support
mx51evk: Use GPIO API for configuring the IOMUX
mx51evk: Add RTC support
rtc: Make mc13783-rtc driver generic
qong: remove unneeded IOMUX settings
qong: Use mx31_set_gpr to setup USBH2 pins
mx31: Introduce mx31_set_gpr function
mx31pdk: Add MC13783 PMIC support
qong: remove unneeded "1" from qong.h
misc: pmic: fix regression in pmic_fsl.c (SPI)
mx5 configs: CONFIG_PRIME should really be CONFIG_ETHPRIME
MX35: Drop unnecessary prototypes from imx-regs.h
I2C: added I2C-2 and I2C-3 to MX35
MX35: factorize common assembly code
MX35: add reset cause as provided by other i.MX
MX35: add pins definition for UART3
MX35: added ESDC structure to imx-regs
Fix:
rtl8139.c: In function 'rtl8139_probe':
rtl8139.c:256:15: warning: variable 'fullduplex' set but not used
[-Wunused-but-set-variable]
rtl8139.c:256:6: warning: variable 'speed10' set but not used
[-Wunused-but-set-variable]
rtl8139.c: In function 'rtl_transmit':
rtl8139.c:419:16: warning: variable 'txstatus' set but not used
[-Wunused-but-set-variable]
Change code to use new debug macros; also fix the new errors and
warnigns popping up now, like "error: 'to' undeclared" and some
"warning: format '%X' expects argument of type 'unsigned int', but
argument X has type 'long unsigned int'"
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
rtl8169.c: In function 'rtl_init':
rtl8169.c:742:13: warning: variable 'printed_version' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
pcnet.c: In function 'pcnet_probe':
pcnet.c:247:8: warning: variable 'chipname' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@denx.de>
Define CONFIG_SYS_EMAC_TI_CLKDIV for setting the clkdiv value
in the MDIO control register.
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Sandeep Paulraj <s-paulraj@ti.com>
cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Fix build problem:
mvgbe.c: In function 'mvgbe_initialize':
mvgbe.c:735: warning: implicit declaration of function 'get_random_hex'
dockstar.c: In function 'board_early_init_f':
dockstar.c:43: warning: implicit declaration of function 'kw_config_gpio'
dockstar.c: In function 'board_init':
dockstar.c:113: warning: implicit declaration of function 'kw_sdram_bar'
dockstar.c: In function 'set_leds':
dockstar.c:161: warning: implicit declaration of function 'readl'
dockstar.c:161: error: dereferencing pointer to incomplete type
dockstar.c:162: warning: implicit declaration of function 'writel'
dockstar.c:162: error: dereferencing pointer to incomplete type
dockstar.c:163: error: dereferencing pointer to incomplete type
dockstar.c:164: error: dereferencing pointer to incomplete type
make[1]: *** [dockstar.o] Error 1
make: *** [board/Seagate/dockstar/libdockstar.o] Error 2
Reported-by: Roland Kletzing <devzero@web.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Fix:
4xx_enet.c: In function 'enet_rcv':
4xx_enet.c:1772:21: warning: variable 'ef_ptr' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Fix:
eepro100.c: In function 'read_hw_addr':
eepro100.c:926:6: warning: variable 'eeprom' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
ns8382x.c: In function 'ns8382x_check_duplex':
ns8382x.c:704:6: warning: variable 'hun' set but not used
[-Wunused-but-set-variable]
To fix this, we get rid of the NS8382X_DEBUG code and use standard
debug() instead.
This will now trigger a so far undetected warning:
ns8382x.c:780:2: warning: format '%X' expects argument of type
'unsigned int', but argument 2 has type 'long unsigned int' [-Wformat]
Fix that, too.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Commit 114d7fc0 "e1000: Rewrite EEPROM checksum error to give more
information" failed to initialize the checksum variable which should
result in random results. Fix that.
Commit 2326a94d caused a ton of "unused variable 'x'" warnings.
Fix these. While we are at it, remove some bogus parens.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
As a part of the manufacturing process for some of our custom hardware,
we are programming the EEPROMs attached to our Intel 82571EB controllers
from software using U-Boot and Linux.
This code provides several conditionally-compiled features to assist in
our manufacturing process:
CONFIG_CMD_E1000:
This is a basic "e1000" command which allows querying the controller
and (if other config options are set) performing EEPROM programming.
In particular, with CONFIG_E1000_SPI this allows you to display a
hex-dump of the EEPROM, copy to/from main memory, and verify/update
the software checksum.
CONFIG_E1000_SPI_GENERIC:
Build a generic SPI driver providing the standard U-Boot SPI driver
interface. This allows commands such as "sspi" to access the bus
attached to the E1000 controller. Additionally, some E1000 chipsets
can support user data in a reserved space in the E1000 EEPROM which
could be used for U-Boot environment storage.
CONFIG_E1000_SPI:
The core SPI access code used by the above interfaces.
For example, the following commands allow you to program the EEPROM from
a USB device (assumes CONFIG_E1000_SPI and CONFIG_CMD_E1000 are enabled):
usb start
fatload usb 0 $loadaddr 82571EB_No_Mgmt_Discrete-LOM.bin
e1000 0 spi program $loadaddr 0 1024
e1000 0 spi checksum update
Please keep in mind that the Intel-provided .eep files are organized as
16-bit words. When converting them to binary form for programming you
must byteswap each 16-bit word so that it is in little-endian form.
This means that when reading and writing words to the SPI EEPROM, the
bit ordering for each word looks like this on the wire:
Time >>>
------------------------------------------------------------------
... [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8], ...
------------------------------------------------------------------
(MSB is 15, LSB is 0).
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
A followup patch will be adding a configurable feature to enable
programming of E1000 EEPROMs from the command line or via the generic
U-Boot SPI interface.
In order for it to work it needs access to certain E1000-internal
functions, so export those in the e1000.h header file.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
As an aide to debugging, we should print out the expected value of the
EEPROM checksum in addition to just saying that it is wrong.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
By allocating the e1000 device structures much earlier, we can easily
generate better error messages and siginficantly clean things up.
The only user-visable change (aside from reworded error messages) is
that a detected e1000 device which fails to initialize due to software
or hardware error will still be allocated a device number.
As one example, consider a system with 2 e1000 PCI devices where the
first controller has a corrupted EEPROM. Using the old code the
second controller would be "e1000#0", while with this change it would be
"e1000#1".
This change should hopefully make such EEPROM errors much more
straightforward to handle correctly in boot scripts and the like.
It is also necessary for a followup patch which allows SPI programming
of an e1000 controller's EEPROM even if the checksum is invalid.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Consolidate the test for a dual-port NIC to one location for easy
modification, then fix support for the dual-port 82571.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
* 'master' of git://git.denx.de/u-boot-arm:
ARM: Add Calxeda Highbank platform
dkb: make mmc command as default enabled
Marvell: dkb: add mmc support
ARM: pantheon: add mmc definition
davinci: remove config.mk file from the sources
ARM:AM33XX: Add support for TI AM335X EVM
ARM:AM33XX: Added timer support
ARM:AM33XX: Add emif/ddr support
ARM:AM33XX: Add clock definitions
ARM:AM33XX: Added support for AM33xx
omap3/emif4: fix registers definition
davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
davinci: emac: add support for more than 1 PHYs
davinci: emac: add new features to autonegotiate for EMAC
da850evm: Move LPSC configuration to board_early_init_f()
omap4_panda: Build in cmd_gpio support on panda
omap: Don't use gpio_free to change direction to input
mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
OMAP3: overo : Add environment variable optargs to bootargs
OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
OMAP3: overo : Use ttyO2 instead of ttyS2.
da830: add support for NAND boot mode
dm36x: revert cache disable patch
dm644X: revert cache disable patch
devkit8000: Add malloc space
omap: spl: fix build break due to changes in FAT
OMAP3 SPL: Provide weak omap_rev_string
omap: beagle: Use ubifs instead of jffs2 for nand boot
omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
omap: overo: Configure mux for gpio10
SPL: Add DMA library
omap3: Add interface for omap3 DMA
omap3: Add DMA register accessors
omap3: Add Base register for DMA
arm, davinci: add missing LSPC define for MMC/SD1
U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
DaVinci: correct MDSTAT.STATE mask
omap4: splitting padconfs into common, 4430 and 4460
omap4: adding revision detection for 4460 ES1.1
omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
gplug: fixed build error as a result of code cleanup patch
kirkwood_spi: add dummy spi_init()
gpio: mvmfp: reduce include platform file
ARM: orion5x: reduce dependence of including platform file
serial: reduce include platform file for marvell chip
ARM: kirkwood: reduce dependence of including platform file
ARM: armada100: reduce dependence of including platform file
ARM: pantheon: reduce dependence of including platform file
Armada100: Add env storage support for Marvell gplugD
Armada100: Add SPI flash support for Marvell gplugD
Armada100: Add SPI support for Marvell gplugD
SPI: Add SPI driver support for Marvell Armada100
dreamplug: initial board support.
imx: fix coding style
misc: pmic: drop old Freescale's pmic driver
MX31: mx31pdk: use new pmic driver
MX31: mx31ads: use new pmic driver
MX31: mx31_litekit: use new pmic driver
MX5: mx53evk: use new pmic driver
MX5: mx51evk: use new pmic driver
MX35: mx35pdk: use new pmic driver
misc: pmic: addI2C support to pmic_fsl driver
misc: pmic: use I2C_SET_BUS in pmic I2C
MX5: efikamx/efikasb: use new pmic driver
MX3: qong: use new pmic driver
RTC: Switch mc13783 to generic pmic code
MX5: vision2: use new pmic driver
misc: pmic: Freescale PMIC switches to generic PMIC driver
misc:pmic:samsung Enable PMIC driver at GONI target
misc:pmic:max8998 MAX8998 support at a new PMIC driver.
misc:pmic:core New generic PMIC driver
mx31pdk: Remove unneeded config
mx31: provide readable WEIM CS accessor
MX51: vision2: Set global macros
I2C: Add i2c_get/set_speed() to mxc_i2c.c
ARM: Update mach-types
devkit8000: Add config to enable SPL MMC boot
devkit8000: protect board_mmc_init
arm, post: add missing post_time_ms for arm
cosmetic, post: Codingstyle cleanup
arm, logbuffer: make it compileclean
tegra2: Enable MMC for Seaboard
tegra2: Add more pinmux functions
tegra2: Rename PIN_ to PINGRP_
tegra2: Add more clock functions
tegra2: Clean up board code a little
tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
fec_mxc.c: In function 'fec_mii_setspeed':
fec_mxc.c:112:2: warning: format '%#lx' expects type 'long unsigned int', but
argument 2 has type 'u32'
fec_mxc.c: In function 'fec_recv':
fec_mxc.c:632:2: warning: format '%x' expects type 'unsigned int', but argument
2 has type 'long unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
ks8695eth.c:199:2: warning: format '%x' expects type 'unsigned int', but
argument 4 has type 'volatile void *'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
4xx_enet.c: In function 'ppc_4xx_eth_init':
4xx_enet.c:1352: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'volatile struct mal_desc_t *'
4xx_enet.c:1352: warning: format '%08x' expects type 'unsigned int', but
argument 3 has type 'volatile struct mal_desc_t *'
4xx_enet.c:1365: warning: format '%08lx' expects type 'long unsigned int', but
argument 3 has type 'unsigned int'
4xx_enet.c:1376: warning: format '%08lx' expects type 'long unsigned int', but
argument 3 has type 'unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
remove macro CONFIG_EMAC_MDIO_PHY_NUM and depending macro EMAC_MDIO_PHY_NUM
as they are no longer needed with the support for more than 1 PHYs in davinci
emac driver.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
add support for more than 1 PHYs. Many of the davinci platforms have more
than 1 PHYs on thier board. This patch extends support in davinci emac
driver for upto 3 PHYs.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
add more features like DUPLEX, 100MB link speed etc to auto negotiate
in EMAC driver. EMAC controller autonegotiates for these features with
PHYs which are on the board.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
For files like the drivers/serial/serial.c, it must include the
platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the
definition in the platform definition files.
Include the platform definition file in the config file, so that it
would decouple the dependence for the driver files.
Signed-off-by: Lei Wen <leiwen@marvell.com>
It seems to be good practice to return the number of received bytes in the
eth_device's recv() callback, here: tse_eth_rx().
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Note: This is kind of guess work. The current code is preserved for
all RGMII related modes. It is different for flags=0 (GMII) and flags=5
(SGMII). The last case, SGMII, is successfully tested on
Altera's Terasic DE4.
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Only one board uses this driver (ns9750dev), but the board doesn't seem
to have an entry to actually build it in the Makefile/boards.cfg, so just
delete net support from its board config.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Everyone seems to have converted to the new enc28j60 driver, so drop
this older one which isn't used and doesn't support NET_MULTI.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
There are several mdelay() definitions in the driver and
board code. Remove them all and provide a common mdelay()
in lib/time.c.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The code had two paths depending on whether the card was to be
accessed from plain memory or the IO region. However the error
path checks whether IO region was obtained - twice. Fix up the
error path according to the probable intention.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch move the reset function from initialization to
driver register procedure.
Some embedded system supports wake on lan nowadays. On this kind of system,
the ftgmac100 will be still supplied power after the system has been
shut-down by Linux. Hence the register used by linux won't be clear
when the system has been powered-off.
The origin ftgmac100 driver in u-boot will only register
driver and functions to network stack and won't reset the ftgmac100
hardware if the network won't be used during boot-up.
This will lead ftgmac100 continue receiving packets and then might corrupt
linux kernel when booting up.
So we reorder the hardware reset function earlier to force the hardware
to be reset whether it will be used or not.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MDIO controller to talk to external PHYs is on FM1-DTSEC1 so don't
allow disabling. If we disable it we end up powering the block down in
the SoC and thus can't communicate to any external PHYs.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
FM1-DTSEC1's MAC was being marked as disabled if the port was not
configured based on the SoC configuration. However we utilize the MAC
interface for MDIO and thus should NOT mark it disabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit a45dde2293 changed the dm9000
direct register access to standard IO. This should work
on the ColdFire platform as there are corresponding macros for
the LE devices. But the hardware settings on some ColdFire boards had
swapped the byte order which make the original macros such as out_le16
cannot work. To avoid changing the common io access code on ColdFire
platform, the DM9000_BYTE_SWAPPED define was added to make the dm9000 use
__raw* IO access on some ColdFire boards.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Add axi_ethernet driver for little-endian Microblaze.
RX/TX BDs and rxframe buffer are shared among all axi_ethernet MACs.
Only one MAC can work in one time.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Setup RX/TX ping-pong buffer for every emaclite IP separately.
The next patch move initialization directly to board code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.
Note that this process can take up to three seconds.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the
P3060 and should always be set to zero.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Function dtsec_configure_serdes() needs to know where the TBI PHY registers
are in order to configure SGMII for proper SerDes operation.
During SGMII initialzation, fm_eth_init_mac() passing NULL for 'phyregs'
when it called init_dtsec(), because it was believed that phyregs was not
used. In fact, it is used by dtsec_configure_serdes() to configure the TBI
PHY registers.
We also need to define the PHY registers in struct fm_mdio.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Teranetics PHY does not properly report the link state
for fiber connections. The new PHY code actually checked the link,
and so the FM driver would refuse to talk over a linkless PHY.
But the link may actually be up, so now we always report it as up
for fiber connections on the tn2020.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Fix:
smc91111.c: In function 'smc_phy_configure':
smc91111.c:1194:6: warning: variable 'failed' set but not used [-Wunused-but-set-variable]
smc91111.c:1190:7: warning: variable 'phyaddr' set but not used [-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Esp. while printing the environment the output is usually longer than 512
bytes. Instead of cutting the message, send multiple 512 bytes packets.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Mike Frysinger <vapier@gentoo.org>
