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Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2013-09-04 11:50:25 +02:00
commit 4eef93da26
19 changed files with 486 additions and 196 deletions
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24
arch/arm/cpu/armv7/at91/sama5d3_devices.c
View file

@ -144,6 +144,30 @@ void at91_macb_hw_init(void)
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_EMAC);
}
void at91_gmac_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_GMAC);
}
#endif
#ifdef CONFIG_LCD

1
arch/arm/include/asm/arch-at91/at91_common.h
View file

@ -10,6 +10,7 @@
#define AT91_COMMON_H
void at91_can_hw_init(void);
void at91_gmac_hw_init(void);
void at91_macb_hw_init(void);
void at91_mci_hw_init(void);
void at91_serial0_hw_init(void);

6
arch/arm/include/asm/arch-at91/at91sam9x5.h
View file

@ -161,6 +161,12 @@
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
#define ATMEL_ID_UHP ATMEL_ID_UHPHS
/*
* PMECC table in ROM
*/
#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
/*
* at91sam9x5 specific prototypes
*/

2
arch/arm/include/asm/arch-at91/sama5d3.h
View file

@ -191,8 +191,6 @@
*/
#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
#define ATMEL_PMECC_ALPHA_OFFSET_512 0x10000
#define ATMEL_PMECC_ALPHA_OFFSET_1024 0x18000
/*
* SAMA5D3 specific prototypes

2
arch/arm/include/asm/arch-at91/sama5d3_smc.h
View file

@ -17,7 +17,6 @@
#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x60C)
#else
struct at91_cs {
u32 reserved[96];
u32 setup; /* 0x600 SMC Setup Register */
u32 pulse; /* 0x604 SMC Pulse Register */
u32 cycle; /* 0x608 SMC Cycle Register */
@ -26,6 +25,7 @@ struct at91_cs {
};
struct at91_smc {
u32 reserved[384];
struct at91_cs cs[4];
};
#endif /* __ASSEMBLY__ */

1
board/atmel/at91sam9m10g45ek/config.mk
View file

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x73f00000

1
board/atmel/at91sam9x5ek/config.mk
View file

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x26f00000

20
board/atmel/sama5d3xek/sama5d3xek.c
View file

@ -17,6 +17,7 @@
#include <lcd.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#include <micrel.h>
#include <net.h>
#include <netdev.h>
@ -178,6 +179,8 @@ int board_init(void)
#ifdef CONFIG_MACB
if (has_emac())
at91_macb_hw_init();
if (has_gmac())
at91_gmac_hw_init();
#endif
#ifdef CONFIG_LCD
if (has_lcdc())
@ -193,6 +196,21 @@ int dram_init(void)
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/* rx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
/* tx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
/* rx/tx clock delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
@ -200,6 +218,8 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_MACB
if (has_emac())
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
if (has_gmac())
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
#endif
return rc;

14
doc/README.atmel_pmecc
View file

@ -19,17 +19,6 @@ To use PMECC in this driver, the user needs to set:
It can be 2, 4, 8, 12 or 24.
2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE.
It only can be 512 or 1024.
3. The PMECC index lookup table's offsets in ROM code: CONFIG_PMECC_INDEX_TABLE_OFFSET.
In the chip datasheet section "Boot Stragegies", you can find
two Galois Field Table in the ROM code. One table is for 512-bytes
sector. Another is for 1024-byte sector. Each Galois Field includes
two sub-table: indext table & alpha table.
In the beginning of each Galois Field Table is the index table,
Alpha table is in the following.
So the index table's offset is same as the Galois Field Table.
Please set CONFIG_PMECC_INDEX_TABLE_OFFSET correctly according the
Galois Field Table's offset base on the sector size you used.
Take AT91SAM9X5EK as an example, the board definition file likes:
@ -38,7 +27,4 @@ Take AT91SAM9X5EK as an example, the board definition file likes:
#define CONFIG_ATMEL_NAND_HW_PMECC 1
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
NOTE: If you use 1024 as the sector size, then need set 0x10000 as the
CONFIG_PMECC_INDEX_TABLE_OFFSET

295
drivers/gpio/at91_gpio.c
View file

@ -1,5 +1,5 @@
/*
* Memory Setup stuff - taken from blob memsetup.S
* Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
*
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
*
@ -8,16 +8,6 @@
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* WARNING:
*
* As the code is right now, it expects all PIO ports A,B,C,...
* to be evenly spaced in the memory map:
* ATMEL_BASE_PIOA + port * sizeof at91pio_t
* This might not necessaryly be true in future Atmel SoCs.
* This code should be fixed to use a pointer array to the ports.
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
@ -25,19 +15,42 @@
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
static struct at91_port *at91_pio_get_port(unsigned port)
{
switch (port) {
case AT91_PIO_PORTA:
return (struct at91_port *)ATMEL_BASE_PIOA;
case AT91_PIO_PORTB:
return (struct at91_port *)ATMEL_BASE_PIOB;
case AT91_PIO_PORTC:
return (struct at91_port *)ATMEL_BASE_PIOC;
#if (ATMEL_PIO_PORTS > 3)
case AT91_PIO_PORTD:
return (struct at91_port *)ATMEL_BASE_PIOD;
#if (ATMEL_PIO_PORTS > 4)
case AT91_PIO_PORTE:
return (struct at91_port *)ATMEL_BASE_PIOE;
#endif
#endif
default:
return NULL;
}
}
int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (use_pullup)
writel(1 << pin, &pio->port[port].puer);
writel(1 << pin, &at91_port->puer);
else
writel(1 << pin, &pio->port[port].pudr);
writel(mask, &pio->port[port].per);
writel(1 << pin, &at91_port->pudr);
writel(mask, &at91_port->per);
}
return 0;
}
@ -46,15 +59,16 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
*/
int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(mask, &pio->port[port].per);
writel(mask, &at91_port->per);
}
return 0;
}
@ -63,23 +77,24 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
*/
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
writel(readl(&pio->port[port].abcdsr1) & ~mask,
&pio->port[port].abcdsr1);
writel(readl(&pio->port[port].abcdsr2) & ~mask,
&pio->port[port].abcdsr2);
writel(readl(&at91_port->abcdsr1) & ~mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) & ~mask,
&at91_port->abcdsr2);
#else
writel(mask, &pio->port[port].asr);
writel(mask, &at91_port->asr);
#endif
writel(mask, &pio->port[port].pdr);
writel(mask, &at91_port->pdr);
}
return 0;
}
@ -88,23 +103,24 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
*/
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
writel(readl(&pio->port[port].abcdsr1) | mask,
&pio->port[port].abcdsr1);
writel(readl(&pio->port[port].abcdsr2) & ~mask,
&pio->port[port].abcdsr2);
writel(readl(&at91_port->abcdsr1) | mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) & ~mask,
&at91_port->abcdsr2);
#else
writel(mask, &pio->port[port].bsr);
writel(mask, &at91_port->bsr);
#endif
writel(mask, &pio->port[port].pdr);
writel(mask, &at91_port->pdr);
}
return 0;
}
@ -114,19 +130,20 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
*/
int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(readl(&pio->port[port].abcdsr1) & ~mask,
&pio->port[port].abcdsr1);
writel(readl(&pio->port[port].abcdsr2) | mask,
&pio->port[port].abcdsr2);
writel(mask, &pio->port[port].pdr);
writel(readl(&at91_port->abcdsr1) & ~mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) | mask,
&at91_port->abcdsr2);
writel(mask, &at91_port->pdr);
}
return 0;
}
@ -135,19 +152,20 @@ int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
*/
int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(readl(&pio->port[port].abcdsr1) | mask,
&pio->port[port].abcdsr1);
writel(readl(&pio->port[port].abcdsr2) | mask,
&pio->port[port].abcdsr2);
writel(mask, &pio->port[port].pdr);
writel(readl(&at91_port->abcdsr1) | mask,
&at91_port->abcdsr1);
writel(readl(&at91_port->abcdsr2) | mask,
&at91_port->abcdsr2);
writel(mask, &at91_port->pdr);
}
return 0;
}
#endif
@ -158,16 +176,17 @@ int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
*/
int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
writel(mask, &pio->port[port].odr);
writel(mask, &pio->port[port].per);
writel(mask, &at91_port->odr);
writel(mask, &at91_port->per);
}
return 0;
}
@ -177,20 +196,21 @@ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
*/
int at91_set_pio_output(unsigned port, u32 pin, int value)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
writel(mask, &pio->port[port].pudr);
writel(mask, &at91_port->idr);
writel(mask, &at91_port->pudr);
if (value)
writel(mask, &pio->port[port].sodr);
writel(mask, &at91_port->sodr);
else
writel(mask, &pio->port[port].codr);
writel(mask, &pio->port[port].oer);
writel(mask, &pio->port[port].per);
writel(mask, &at91_port->codr);
writel(mask, &at91_port->oer);
writel(mask, &at91_port->per);
}
return 0;
}
@ -199,20 +219,21 @@ int at91_set_pio_output(unsigned port, u32 pin, int value)
*/
int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (is_on) {
#if defined(CPU_HAS_PIO3)
writel(mask, &pio->port[port].ifscdr);
writel(mask, &at91_port->ifscdr);
#endif
writel(mask, &pio->port[port].ifer);
writel(mask, &at91_port->ifer);
} else {
writel(mask, &pio->port[port].ifdr);
writel(mask, &at91_port->ifdr);
}
}
return 0;
}
@ -222,19 +243,20 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
*/
int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (is_on) {
writel(mask, &pio->port[port].ifscer);
writel(div & PIO_SCDR_DIV, &pio->port[port].scdr);
writel(mask, &pio->port[port].ifer);
writel(mask, &at91_port->ifscer);
writel(div & PIO_SCDR_DIV, &at91_port->scdr);
writel(mask, &at91_port->ifer);
} else {
writel(mask, &pio->port[port].ifdr);
writel(mask, &at91_port->ifdr);
}
}
return 0;
}
@ -244,17 +266,18 @@ int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
*/
int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(mask, &pio->port[port].pudr);
writel(mask, &at91_port->pudr);
if (is_on)
writel(mask, &pio->port[port].ppder);
writel(mask, &at91_port->ppder);
else
writel(mask, &pio->port[port].ppddr);
writel(mask, &at91_port->ppddr);
}
return 0;
}
@ -263,14 +286,15 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
*/
int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
writel(readl(&pio->port[port].schmitt) | mask,
&pio->port[port].schmitt);
writel(readl(&at91_port->schmitt) | mask,
&at91_port->schmitt);
}
return 0;
}
#endif
@ -281,16 +305,17 @@ int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
*/
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (is_on)
writel(mask, &pio->port[port].mder);
writel(mask, &at91_port->mder);
else
writel(mask, &pio->port[port].mddr);
writel(mask, &at91_port->mddr);
}
return 0;
}
@ -299,16 +324,17 @@ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
*/
int at91_set_pio_value(unsigned port, unsigned pin, int value)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (value)
writel(mask, &pio->port[port].sodr);
writel(mask, &at91_port->sodr);
else
writel(mask, &pio->port[port].codr);
writel(mask, &at91_port->codr);
}
return 0;
}
@ -317,13 +343,56 @@ int at91_set_pio_value(unsigned port, unsigned pin, int value)
*/
int at91_get_pio_value(unsigned port, unsigned pin)
{
u32 pdsr = 0;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
u32 mask;
struct at91_port *at91_port = at91_pio_get_port(port);
u32 pdsr = 0, mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
if (at91_port && (pin < 32)) {
mask = 1 << pin;
pdsr = readl(&pio->port[port].pdsr) & mask;
pdsr = readl(&at91_port->pdsr) & mask;
}
return pdsr != 0;
}
/* Common GPIO API */
#define at91_gpio_to_port(gpio) (gpio / 32)
#define at91_gpio_to_pin(gpio) (gpio % 32)
int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
int gpio_free(unsigned gpio)
{
return 0;
}
int gpio_direction_input(unsigned gpio)
{
at91_set_pio_input(at91_gpio_to_port(gpio),
at91_gpio_to_pin(gpio), 0);
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
{
at91_set_pio_output(at91_gpio_to_port(gpio),
at91_gpio_to_pin(gpio), value);
return 0;
}
int gpio_get_value(unsigned gpio)
{
return at91_get_pio_value(at91_gpio_to_port(gpio),
at91_gpio_to_pin(gpio));
}
int gpio_set_value(unsigned gpio, int value)
{
at91_set_pio_value(at91_gpio_to_port(gpio),
at91_gpio_to_pin(gpio), value);
return 0;
}

198
drivers/mtd/nand/atmel_nand.c
View file

@ -16,6 +16,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <malloc.h>
#include <nand.h>
#include <watchdog.h>
@ -50,13 +51,13 @@ struct atmel_nand_host {
void __iomem *pmecc_index_of;
/* data for pmecc computation */
int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)];
int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1];
int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1];
int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */
int pmecc_mu[CONFIG_PMECC_CAP + 1];
int pmecc_dmu[CONFIG_PMECC_CAP + 1];
int pmecc_delta[CONFIG_PMECC_CAP + 1];
int16_t *pmecc_smu;
int16_t *pmecc_partial_syn;
int16_t *pmecc_si;
int16_t *pmecc_lmu; /* polynomal order */
int *pmecc_mu;
int *pmecc_dmu;
int *pmecc_delta;
};
static struct atmel_nand_host pmecc_host;
@ -109,6 +110,48 @@ static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
table_size * sizeof(int16_t);
}
static void pmecc_data_free(struct atmel_nand_host *host)
{
free(host->pmecc_partial_syn);
free(host->pmecc_si);
free(host->pmecc_lmu);
free(host->pmecc_smu);
free(host->pmecc_mu);
free(host->pmecc_dmu);
free(host->pmecc_delta);
}
static int pmecc_data_alloc(struct atmel_nand_host *host)
{
const int cap = host->pmecc_corr_cap;
int size;
size = (2 * cap + 1) * sizeof(int16_t);
host->pmecc_partial_syn = malloc(size);
host->pmecc_si = malloc(size);
host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
host->pmecc_smu = malloc((cap + 2) * size);
size = (cap + 1) * sizeof(int);
host->pmecc_mu = malloc(size);
host->pmecc_dmu = malloc(size);
host->pmecc_delta = malloc(size);
if (host->pmecc_partial_syn &&
host->pmecc_si &&
host->pmecc_lmu &&
host->pmecc_smu &&
host->pmecc_mu &&
host->pmecc_dmu &&
host->pmecc_delta)
return 0;
/* error happened */
pmecc_data_free(host);
return -ENOMEM;
}
static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
{
struct nand_chip *nand_chip = mtd->priv;
@ -622,6 +665,99 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd)
pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
}
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
/*
* get_onfi_ecc_param - Get ECC requirement from ONFI parameters
* @ecc_bits: store the ONFI ECC correct bits capbility
* @sector_size: in how many bytes that ONFI require to correct @ecc_bits
*
* Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
* @sector_size are initialize to 0.
* Return 0 if success to get the ECC requirement.
*/
static int get_onfi_ecc_param(struct nand_chip *chip,
int *ecc_bits, int *sector_size)
{
*ecc_bits = *sector_size = 0;
if (chip->onfi_params.ecc_bits == 0xff)
/* TODO: the sector_size and ecc_bits need to be find in
* extended ecc parameter, currently we don't support it.
*/
return -1;
*ecc_bits = chip->onfi_params.ecc_bits;
/* The default sector size (ecc codeword size) is 512 */
*sector_size = 512;
return 0;
}
/*
* pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
* pmecc_corr_cap or pmecc_sector_size is 0, then set it as
* ONFI ECC parameters.
* @host: point to an atmel_nand_host structure.
* if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
* if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
* @chip: point to an nand_chip structure.
* @cap: store the ONFI ECC correct bits capbility
* @sector_size: in how many bytes that ONFI require to correct @ecc_bits
*
* Return 0 if success. otherwise return the error code.
*/
static int pmecc_choose_ecc(struct atmel_nand_host *host,
struct nand_chip *chip,
int *cap, int *sector_size)
{
/* Get ECC requirement from ONFI parameters */
*cap = *sector_size = 0;
if (chip->onfi_version) {
if (!get_onfi_ecc_param(chip, cap, sector_size)) {
MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
*cap, *sector_size);
} else {
dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
}
} else {
dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
}
if (*cap == 0 && *sector_size == 0) {
/* Non-ONFI compliant or use extended ONFI parameters */
*cap = 2;
*sector_size = 512;
}
/* If head file doesn't specify then use the one in ONFI parameters */
if (host->pmecc_corr_cap == 0) {
/* use the most fitable ecc bits (the near bigger one ) */
if (*cap <= 2)
host->pmecc_corr_cap = 2;
else if (*cap <= 4)
host->pmecc_corr_cap = 4;
else if (*cap <= 8)
host->pmecc_corr_cap = 8;
else if (*cap <= 12)
host->pmecc_corr_cap = 12;
else if (*cap <= 24)
host->pmecc_corr_cap = 24;
else
return -EINVAL;
}
if (host->pmecc_sector_size == 0) {
/* use the most fitable sector size (the near smaller one ) */
if (*sector_size >= 1024)
host->pmecc_sector_size = 1024;
else if (*sector_size >= 512)
host->pmecc_sector_size = 512;
else
return -EINVAL;
}
return 0;
}
#endif
static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
struct mtd_info *mtd)
{
@ -635,9 +771,45 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
nand->ecc.correct = NULL;
nand->ecc.hwctl = NULL;
cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP;
sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
host->pmecc_corr_cap = host->pmecc_sector_size = 0;
#ifdef CONFIG_PMECC_CAP
host->pmecc_corr_cap = CONFIG_PMECC_CAP;
#endif
#ifdef CONFIG_PMECC_SECTOR_SIZE
host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
#endif
/* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
* CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
* from ONFI.
*/
if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
cap, sector_size);
return -EINVAL;
}
if (cap > host->pmecc_corr_cap)
dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
host->pmecc_corr_cap, cap);
if (sector_size < host->pmecc_sector_size)
dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
host->pmecc_sector_size, sector_size);
#else /* CONFIG_SYS_NAND_ONFI_DETECTION */
host->pmecc_corr_cap = CONFIG_PMECC_CAP;
host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
#endif
cap = host->pmecc_corr_cap;
sector_size = host->pmecc_sector_size;
/* TODO: need check whether cap & sector_size is validate */
if (host->pmecc_sector_size == 512)
host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
else
host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
MTDDEBUG(MTD_DEBUG_LEVEL1,
"Initialize PMECC params, cap: %d, sector: %d\n",
@ -691,6 +863,12 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
return 0;
}
/* Allocate data for PMECC computation */
if (pmecc_data_alloc(host)) {
dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
return -ENOMEM;
}
nand->ecc.read_page = atmel_nand_pmecc_read_page;
nand->ecc.write_page = atmel_nand_pmecc_write_page;
nand->ecc.strength = cap;

12
drivers/net/macb.c
View file

@ -36,6 +36,7 @@
#include <asm/io.h>
#include <asm/dma-mapping.h>
#include <asm/arch/clk.h>
#include <asm-generic/errno.h>
#include "macb.h"
@ -397,9 +398,14 @@ static int macb_phy_init(struct macb_device *macb)
}
#ifdef CONFIG_PHYLIB
phydev->bus = macb->bus;
phydev->dev = netdev;
phydev->addr = macb->phy_addr;
/* need to consider other phy interface mode */
phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
printf("phy_connect failed\n");
return -ENODEV;
}
phy_config(phydev);
#endif

16
drivers/usb/musb-new/linux-compat.h
View file

@ -39,15 +39,6 @@ typedef unsigned long dmaaddr_t;
#define cpu_relax() do {} while (0)
#define pr_debug(fmt, args...) debug(fmt, ##args)
#define dev_dbg(dev, fmt, args...) \
debug(fmt, ##args)
#define dev_vdbg(dev, fmt, args...) \
debug(fmt, ##args)
#define dev_info(dev, fmt, args...) \
printf(fmt, ##args)
#define dev_err(dev, fmt, args...) \
printf(fmt, ##args)
#define printk printf
#define WARN(condition, fmt, args...) ({ \
int ret_warn = !!condition; \
@ -55,13 +46,6 @@ typedef unsigned long dmaaddr_t;
printf(fmt, ##args); \
ret_warn; })
#define KERN_DEBUG
#define KERN_NOTICE
#define KERN_WARNING
#define KERN_ERR
#define kfree(ptr) free(ptr)
#define pm_runtime_get_sync(dev) do {} while (0)
#define pm_runtime_put(dev) do {} while (0)
#define pm_runtime_put_sync(dev) do {} while (0)

2
include/configs/at91sam9m10g45ek.h
View file

@ -13,6 +13,8 @@
#include <asm/hardware.h>
#define CONFIG_SYS_TEXT_BASE 0x73f00000
#define CONFIG_AT91_LEGACY
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */

3
include/configs/at91sam9n12ek.h
View file

@ -122,6 +122,9 @@
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
#define CONFIG_CMD_NAND_TRIMFFS
#endif
#define CONFIG_MTD_PARTITIONS

5
include/configs/at91sam9x5ek.h
View file

@ -11,6 +11,8 @@
#include <asm/hardware.h>
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
@ -121,7 +123,8 @@
#define CONFIG_ATMEL_NAND_HW_PMECC 1
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS

62
include/configs/eb_cpux9k2.h
View file

@ -39,6 +39,7 @@
#define CONFIG_SYS_TEXT_BASE 0x21f00000
#endif
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000
#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
@ -123,41 +124,40 @@
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_I2C_CMD_NO_FLAT
#define CONFIG_I2C_CMD_TREE
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_CMD_UBI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_UBIFS
#define CONFIG_SYS_LONGHELP
/*
* Filesystems
* MTD defines
*/
#define CONFIG_JFFS2_NAND 1
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO
#ifndef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_JFFS2_PART_OFFSET 0
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#else
#define MTDIDS_DEFAULT "nor0=0,nand0=1"
#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
#define MTDPARTS_DEFAULT "mtdparts=" \
"0:" \
"384k(U-Boot)," \
"128k(Env)," \
"128k(Splash)," \
"4M(Kernel)," \
"-(FS)" \
"physmap-flash.0:" \
"512k(U-Boot)," \
"128k(Env)," \
"128k(Splash)," \
"4M(Kernel)," \
"384k(MiniFS)," \
"-(FS)" \
";" \
"1:" \
"-(jffs2)"
#endif /* CONFIG_JFFS2_CMDLINE */
"atmel_nand:" \
"1M(emergency)," \
"-(data)"
/*
* Hardware drivers
*/
@ -328,7 +328,7 @@
#define CONFIG_BOOTDELAY 5
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000)
#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
#define CONFIG_BAUDRATE 115200
@ -347,12 +347,14 @@
"displayheight=512\0" \
"displaybsteps=1023\0" \
"ubootaddr=10000000\0" \
"splashimage=10080000\0" \
"kerneladdr=100A0000\0" \
"splashimage=100A0000\0" \
"kerneladdr=100C0000\0" \
"kernelsize=00400000\0" \
"rootfsaddr=104A0000\0" \
"rootfsaddr=10520000\0" \
"copy_addr=21200000\0" \
"rootfssize=00B60000\0" \
"rootfssize=00AE0000\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"bootargsdefaults=set bootargs " \
"console=ttyS0,115200 " \
"video=vcxk_fb:xres:${displaywidth}," \
@ -373,15 +375,15 @@
"erase $(rootfsaddr) +$(rootfssize);" \
"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
"\0" \
"update_uboot=protect off 10000000 1005FFFF;" \
"update_uboot=protect off 10000000 1007FFFF;" \
"dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
"erase 10000000 1005FFFF;" \
"erase 10000000 1007FFFF;" \
"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
"protect on 10000000 1005FFFF;reset\0" \
"protect on 10000000 1007FFFF;reset\0" \
"update_splash=protect off $(splashimage) +20000;" \
"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
"erase $(splashimage) +20000;" \
"cp.b $(fileaddr) 10080000 $(filesize);" \
"cp.b $(fileaddr) $(splashimage) $(filesize);" \
"protect on $(splashimage) +20000;reset\0" \
"emergency=run bootargsdefaults;" \
"set bootargs $(bootargs) root=initramfs boot=emergency " \

10
include/configs/sama5d3xek.h
View file

@ -56,7 +56,6 @@
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 24
#define CONFIG_LCD_LOGO
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_SYS_WHITE_ON_BLACK
@ -112,7 +111,6 @@
#define CONFIG_CMD_NAND
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MAX_CHIPS 1
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
@ -126,7 +124,6 @@
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_PMECC_INDEX_TABLE_OFFSET ATMEL_PMECC_INDEX_OFFSET_512
#define CONFIG_CMD_NAND_TRIMFFS
#endif
@ -136,6 +133,11 @@
#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
#define CONFIG_RGMII
#define CONFIG_CMD_MII
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
/* MMC */
#define CONFIG_CMD_MMC
@ -195,7 +197,7 @@
"bootm 0x22000000 - 0x21000000"
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#define CONIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_NOWHERE
#endif
#ifdef CONFIG_SYS_USE_MMC

8
include/linux/compat.h
View file

@ -3,6 +3,14 @@
#define ndelay(x) udelay(1)
#define dev_dbg(dev, fmt, args...) \
debug(fmt, ##args)
#define dev_vdbg(dev, fmt, args...) \
debug(fmt, ##args)
#define dev_info(dev, fmt, args...) \
printf(fmt, ##args)
#define dev_err(dev, fmt, args...) \
printf(fmt, ##args)
#define printk printf
#define KERN_EMERG