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net: sh_eth: use miiphybb instead of own mii functions
The sh_eth driver had an own mii functions. However the function didn't support the gigabit PHY. The U-Boot has the general phy driver and miiphybb driver, and they already support it. So this patch removes the own functions and uses the phy driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Yoshihiro Shimoda
Nobuhiro Iwamatsu
parent
7708d8b352
commit
bd1024b052
2 changed files with 104 additions and 248 deletions
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@ -25,6 +25,7 @@
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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@ -45,144 +46,6 @@
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#define SH_ETH_PHY_DELAY 50000
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/*
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* Bits are written to the PHY serially using the
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* PIR register, just like a bit banger.
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*/
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static void sh_eth_mii_write_phy_bits(int port, u32 val, int len)
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{
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int i;
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u32 pir;
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/* Bit positions is 1 less than the number of bits */
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for (i = len - 1; i >= 0; i--) {
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/* Write direction, bit to write, clock is low */
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pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
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outl(pir, PIR(port));
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udelay(1);
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/* Write direction, bit to write, clock is high */
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pir = 3 | ((val & 1 << i) ? 1 << 2 : 0);
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outl(pir, PIR(port));
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udelay(1);
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/* Write direction, bit to write, clock is low */
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pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
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outl(pir, PIR(port));
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udelay(1);
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}
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}
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static void sh_eth_mii_bus_release(int port)
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{
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/* Read direction, clock is low */
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outl(0, PIR(port));
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udelay(1);
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/* Read direction, clock is high */
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outl(1, PIR(port));
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udelay(1);
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/* Read direction, clock is low */
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outl(0, PIR(port));
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udelay(1);
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}
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static void sh_eth_mii_ind_bus_release(int port)
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{
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/* Read direction, clock is low */
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outl(0, PIR(port));
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udelay(1);
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}
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static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len)
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{
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int i;
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u32 pir;
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*val = 0;
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for (i = len - 1; i >= 0; i--) {
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/* Read direction, clock is high */
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outl(1, PIR(port));
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udelay(1);
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/* Read bit */
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pir = inl(PIR(port));
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*val |= (pir & 8) ? 1 << i : 0;
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/* Read direction, clock is low */
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outl(0, PIR(port));
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udelay(1);
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}
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}
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#define PHY_INIT 0xFFFFFFFF
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#define PHY_READ 0x02
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#define PHY_WRITE 0x01
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/*
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* To read a phy register, mii managements frames are sent to the phy.
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* The frames look like this:
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* pre (32 bits): 0xffff ffff
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* st (2 bits): 01
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* op (2bits): 10: read 01: write
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* phyad (5 bits): xxxxx
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* regad (5 bits): xxxxx
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* ta (Bus release):
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* data (16 bits): read data
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*/
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static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
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{
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u32 val;
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/* Sent mii management frame */
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/* pre */
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sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
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/* st (start of frame) */
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sh_eth_mii_write_phy_bits(port, 0x1, 2);
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/* op (code) */
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sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
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/* phy address */
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sh_eth_mii_write_phy_bits(port, phy_addr, 5);
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/* Register to read */
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sh_eth_mii_write_phy_bits(port, reg, 5);
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/* Bus release */
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sh_eth_mii_bus_release(port);
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/* Read register */
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sh_eth_mii_read_phy_bits(port, &val, 16);
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return val;
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}
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/*
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* To write a phy register, mii managements frames are sent to the phy.
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* The frames look like this:
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* pre (32 bits): 0xffff ffff
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* st (2 bits): 01
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* op (2bits): 10: read 01: write
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* phyad (5 bits): xxxxx
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* regad (5 bits): xxxxx
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* ta (2 bits): 10
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* data (16 bits): write data
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* idle (Independent bus release)
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*/
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static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val)
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{
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/* Sent mii management frame */
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/* pre */
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sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
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/* st (start of frame) */
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sh_eth_mii_write_phy_bits(port, 0x1, 2);
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/* op (code) */
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sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2);
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/* phy address */
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sh_eth_mii_write_phy_bits(port, phy_addr, 5);
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/* Register to read */
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sh_eth_mii_write_phy_bits(port, reg, 5);
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/* ta */
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sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
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/* Write register data */
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sh_eth_mii_write_phy_bits(port, val, 16);
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/* Independent bus release */
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sh_eth_mii_ind_bus_release(port);
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}
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int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
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{
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struct sh_eth_dev *eth = dev->priv;
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@ -480,62 +343,26 @@ err_tx_init:
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static int sh_eth_phy_config(struct sh_eth_dev *eth)
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{
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int port = eth->port, timeout, ret = 0;
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int port = eth->port, ret = 0;
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struct sh_eth_info *port_info = ð->port_info[port];
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u32 val;
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struct eth_device *dev = port_info->dev;
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struct phy_device *phydev;
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/* Reset phy */
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sh_eth_mii_write_phy_reg
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(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET);
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timeout = 10;
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while (timeout--) {
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val = sh_eth_mii_read_phy_reg(port,
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port_info->phy_addr, PHY_CTRL);
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if (!(val & PHY_C_RESET))
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break;
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udelay(SH_ETH_PHY_DELAY);
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}
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phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
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port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
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port_info->phydev = phydev;
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phy_config(phydev);
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if (timeout < 0) {
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printf(SHETHER_NAME ": phy reset timeout\n");
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ret = -EIO;
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goto err_tout;
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}
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/* Advertise 100/10 baseT full/half duplex */
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sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA,
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(PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT));
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/* Autonegotiation, normal operation, full duplex, enable tx */
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sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL,
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(PHY_C_ANEGEN|PHY_C_RANEG));
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/* Wait for autonegotiation to complete */
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timeout = 100;
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while (timeout--) {
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val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
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if (val & PHY_S_ANEGC)
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break;
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udelay(SH_ETH_PHY_DELAY);
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}
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if (timeout < 0) {
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printf(SHETHER_NAME ": phy auto-negotiation failed\n");
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ret = -ETIMEDOUT;
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goto err_tout;
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}
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return ret;
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err_tout:
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return ret;
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}
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static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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{
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int port = eth->port, ret = 0;
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u32 val, phy_status;
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u32 val;
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struct sh_eth_info *port_info = ð->port_info[port];
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struct eth_device *dev = port_info->dev;
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struct phy_device *phy;
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/* Configure e-dmac registers */
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outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
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@ -582,31 +409,31 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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printf(SHETHER_NAME ": phy config timeout\n");
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goto err_phy_cfg;
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}
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/* Read phy status to finish configuring the e-mac */
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phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
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phy = port_info->phydev;
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phy_startup(phy);
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/* Set the transfer speed */
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#ifdef CONFIG_CPU_SH7763
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if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
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if (phy->speed == 100) {
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printf(SHETHER_NAME ": 100Base/");
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outl(GECMR_100B, GECMR(port));
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} else {
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} else if (phy->speed == 10) {
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printf(SHETHER_NAME ": 10Base/");
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outl(GECMR_10B, GECMR(port));
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}
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#endif
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#if defined(CONFIG_CPU_SH7757)
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if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
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if (phy->speed == 100) {
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printf("100Base/");
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outl(1, RTRATE(port));
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} else {
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} else if (phy->speed == 10) {
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printf("10Base/");
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outl(0, RTRATE(port));
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}
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#endif
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/* Check if full duplex mode is supported by the phy */
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if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {
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if (phy->duplex) {
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printf("Full\n");
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outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
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} else {
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@ -707,6 +534,9 @@ int sh_eth_initialize(bd_t *bd)
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/* Register Device to EtherNet subsystem */
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eth_register(dev);
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bb_miiphy_buses[0].priv = eth;
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miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
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if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
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puts("Please set MAC address\n");
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@ -722,3 +552,86 @@ err:
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printf(SHETHER_NAME ": Failed\n");
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return ret;
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}
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/******* for bb_miiphy *******/
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static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
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{
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return 0;
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}
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static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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outl(inl(PIR(port)) | PIR_MMD, PIR(port));
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return 0;
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}
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static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
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return 0;
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}
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static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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if (v)
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outl(inl(PIR(port)) | PIR_MDO, PIR(port));
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else
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outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
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return 0;
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}
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static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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*v = (inl(PIR(port)) & PIR_MDI) >> 3;
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return 0;
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}
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static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
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{
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struct sh_eth_dev *eth = bus->priv;
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int port = eth->port;
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if (v)
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outl(inl(PIR(port)) | PIR_MDC, PIR(port));
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else
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outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
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return 0;
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}
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static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
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{
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udelay(10);
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return 0;
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}
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struct bb_miiphy_bus bb_miiphy_buses[] = {
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{
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.name = "sh_eth",
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.init = sh_eth_bb_init,
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.mdio_active = sh_eth_bb_mdio_active,
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.mdio_tristate = sh_eth_bb_mdio_tristate,
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.set_mdio = sh_eth_bb_set_mdio,
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.get_mdio = sh_eth_bb_get_mdio,
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.set_mdc = sh_eth_bb_set_mdc,
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.delay = sh_eth_bb_delay,
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}
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};
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int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
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@ -89,6 +89,7 @@ struct sh_eth_info {
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u8 mac_addr[6];
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u8 phy_addr;
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struct eth_device *dev;
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struct phy_device *phydev;
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};
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struct sh_eth_dev {
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@ -435,61 +436,3 @@ enum FIFO_SIZE_BIT {
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FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
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};
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enum PHY_OFFSETS {
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PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
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PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
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PHY_16 = 16,
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};
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/* PHY_CTRL */
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enum PHY_CTRL_BIT {
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PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
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PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
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PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
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};
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#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
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/* PHY_STAT */
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enum PHY_STAT_BIT {
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PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
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PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
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PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
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PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
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};
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/* PHY_ANA */
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enum PHY_ANA_BIT {
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PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
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PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
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PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
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PHY_A_SEL = 0x001e,
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PHY_A_EXT = 0x0001,
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};
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/* PHY_ANL */
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enum PHY_ANL_BIT {
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PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
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PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
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PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
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PHY_L_SEL = 0x001f,
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};
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/* PHY_ANE */
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enum PHY_ANE_BIT {
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PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
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PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
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};
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/* DM9161 */
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enum PHY_16_BIT {
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PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
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PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
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PHY_16_TXselect = 0x0400,
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PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
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PHY_16_Force100LNK = 0x0080,
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PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
|
||||
PHY_16_RPDCTR_EN = 0x0010,
|
||||
PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
|
||||
PHY_16_Sleepmode = 0x0002,
|
||||
PHY_16_RemoteLoopOut = 0x0001,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue