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net/designware: Consecutive writes to the same register to be avoided

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This commit is an add-on to f6c4191f. There are a few registers where
consecutive writes to the same location should be avoided or have a delay.

According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:

DMA Registers:
Register 0        Bit 7
Register 6        All bits except for 24, 16-13, 2-1.

GMAC Registers:
Registers 0-3     All bits
Registers 6-7     All bits
Register 10       All bits
Register 11       All bits except for 5-6.
Registers 16-47   All bits
Register 48       All bits except for 18-16, 14.
Register 448      Bit 4.
Register 459      Bits 0-3.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Matthew Gerlach <mgerlach@altera.com>
Acked-by: Amit Virdi <amit.virdi@st.com>
This commit is contained in:
Dinh Nguyen 2012-06-08 05:26:52 +00:00 committed by Joe Hershberger
parent c59ab0921f
commit 66f119e50c
1 changed files with 2 additions and 2 deletions
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4
drivers/net/designware.c
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@ -171,8 +171,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
&dma_p->busmode);
writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
TXSECONDFRAME, &dma_p->opmode);
conf = FRAMEBURSTENABLE | DISABLERXOWN;