Configure the phy regulator if defined by the "phy-supply" DT phandle.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The DT binding says:
- phy-reset-duration : Reset duration in milliseconds. Should present
only if property "phy-reset-gpios" is available. Missing the property
will have the duration be 1 millisecond. Numbers greater than 1000 are
invalid and 1 millisecond will be used instead.
However the current code:
- clamps values greater than 1000ms to 1000ms rather than 1.
- does not initialize the delay if the property does not exist
(else clause mismatch)
- returns an error if phy-reset-gpios is not defined
Fix all this and simplify by using dev_read_u32_default()
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The DT binding says that phy-reset-duration is in ms, but the driver
currently uses udelay().
Switch to mdelay() to fix this.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If the phy reports a valid firmware version and doesn't indicate
a fault, skip loading the firmware. This allows the same image
to be used on boards that have firmware storage and those that do not.
Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia phys have firmware that can be loaded automatically
from storage directly attached to the phy or via MDIO commands.
Add support for loading firmware from either a file or a
raw location on an MMC device.
Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The aquantia driver requires both CONFIG_PHY_GIGE and CONFIG_PHYLIB_10G.
Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
sunxi_rgb2yuv_coef is readonly and never modified.
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Choose best prescaler to improve PWM resolution. Without this change
driver chooses first prescaler that gives us period value within
range, but it could be not the best one.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Looks like old prescaler was used when configuring PWM, fix it.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Fix off-by-one that prevented PWM driver to use prescaler bypass.
Without this change prescaler is always enabled.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
This is required for the current Linux kernel to reboot. It should also
probably be fixed in Linux.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently in pmecc_get_sigma(), the code tries to clear the memory
pointed by smu with wrong size 'sizeof(int16_t) * ARRAY_SIZE(smu)'.
Since smu is actually a pointer, not an array, so ARRAY_SIZE(smu)
does not generate correct size to be cleared.
In fact, GCC 8.1.0 reports a warning against it:
error: division 'sizeof (int16_t * {aka short int *}) / sizeof (int16_t
{aka short int})' does not compute the number of array elements
[-Werror=sizeof-pointer-div]
Fix it by using the correct size.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
When CONIFG_CLK is enabled, use uclass clk api to handle
the clock.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Add CONFIG_ARCH_IMX8 to use the 64bits support in usdhc driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Modify most APIs to use udevice as the first parameter, then
it will be easy to get the clk reference by using udevice pointer.
Use uclass api to get lpuart clk when CONFIG_CLK is enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Enable the RX and TX FIFO in LPUART driver to avoid the input lost
during U-Boot boot up.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add i.MX8 compatible string and cpu type support to lpuart driver,
to use little endian 32 bits configurations.
Also, according to RM, the Receive FIFO Enable (RXFE) field in LPUART
FIFO register is bit 3, so this definition should change to 0x08
(not 0x40) for i.MX8, otherwise the Receive FIFO is not disabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add the power domain DM driver for i.MX8, that it depends on the DTB
power domain trees to generate the power domain provider devices. Users
need to add power domain trees with property "compatible = "nxp,imx8-pd";"
When power on a PD device, the driver will power on its ancestor PD
devices in power domain tree.
When power off a PD device, the driver will check its child PD devices
first. Only if all child PD devices are off, then power off the current PD
device. Then the driver checks sibling PD devices. If sibling PD devices
are off, then it will power off parent PD device.
There is no counter maintained in this driver, but a state to hold current
on/off state. So the request and free functions are empty.
The power domain implementation in i.MX8 DTB set the "#power-domain-cells"
to 0, so there is no ID binding with each PD device. We don't use "id"
variable in struct power_domain. At the same time, we have to set of_xlate
to empty to bypass standard of_xlate in uclass driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add pinctrl driver for i.MX8. The pads configuration is controlled
by SCU, so need to ask SCU to configure pads through scfw API.
Add pinctrl-scu to invoke sc_pad_set to configure pads.
Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms
which could directly configure pads from Acore side.
Add CONFIG_PINCTRL_IMX8 as the built gate.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add clk/misc/pad/pm/rm scfw api implementaion for different
drivers to invoke. The low level code is using misc_call
to invoke imx8_scu driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add i.MX8 MISC driver to handle the communication between
A35 Core and SCU.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
So far the TSC timer driver supports trying hardware calibration first
and using device tree as last resort for its running frequency as the
normal timer.
However when it is used as the early timer, it only supports hardware
calibration and if it fails, the driver just panics. This introduces
a new config option to specify the early timer frequency in MHz and
it should be equal to the value described in the device tree.
Without this patch, the travis-ci testing on QEMU x86_64 target fails
each time after it finishes the 'bootefi selftest' as the test.py see
an error was emitted on the console like this:
TSC frequency is ZERO
resetting ...
### ERROR ### Please RESET the board ###
It's strange that this error is consistently seen on the travis-ci
machine, but only occasionally seen on my local machine (maybe 1 out
of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses
early timer, with this fix it should work without any failure.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In initr_bootstage() we call bootstage_mark_name() which ends up calling
timer_get_us(). This call happens before initr_dm(), which inits driver
model.
On x86 we set gd->timer to NULL in the transition from board_init_f()
to board_init_r(). See board_init_f_r() for this assignment. So U-Boot
knows there is no timer available in the period immediately after
relocation.
On x86 the timer_get_us() call is implemented as calls to get_ticks() and
get_tbclk(). Both of these call dm_timer_init() to set up the timer, if
gd->timer is NULL and the early timer is not available.
However dm_timer_init() cannot succeed before initr_dm() is called.
So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable
CONFIG_TIMER_EARLY. Update the Kconfig to handle this.
Note: On most architectures we can rely on the pre-relocation memory still
being available, so that gd->timer pointers to a valid timer device and
everything works correctly. Admittedly this is not strictly correct since
the timer device is set up by pre-relocation U-Boot, but normally this is
fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot
disappears in board_init_f_r() and any attempt to access it will hang.
This is the reason why we must mark the timer as invalid when we get to
board_init_f_r().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The PCI controller can have DT subnodes describing extra properties
of particular PCI devices, ie. a PHY attached to an EHCI controller
on a PCI bus. This patch parses those DT subnodes and assigns a node
to the PCI device instance, so that the driver can extract details
from that node and ie. configure the PHY using the PHY subsystem.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This converts the following to Kconfig:
CONFIG_FLASH_CFI_DRIVER
CONFIG_SYS_FLASH_USE_BUFFER_WRITE
CONFIG_FLASH_CFI_MTD
CONFIG_SYS_FLASH_PROTECTION
CONFIG_SYS_FLASH_CFI
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Re-migrate]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add new Kconfig option, SYS_BOOTCOUNT_MAGIC, to select the boot
counter magic word. This can be useful ie. in case the entire
boot counter register is not usable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.
The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We need to #ifdef some variables to avoid warning about them being
unused.
Fixes: 1a048cd656 ("driver: net: fsl-mc: Add support of multiple phys for dpmac")
Signed-off-by: Tom Rini <trini@konsulko.com>
NOR flash name MT35X_QLKA and MT25Q_** used on NXP board has
manufacturer id as 0x2C, which are rather for newer flashes
after the split of Micron from ST.
So macro for this micron manufacturer id.
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
[jagan: updated commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
accidentially while fixing merge errors for patch:
https://lists.denx.de/pipermail/u-boot/2018-September/342278.html
missed to add files:
MAINTAINERS
drivers/i2c/Kconfig
drivers/i2c/Makefile
add them with this patch.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Till now we have had cases where we had one phy device per dpmac.
Now, with the upcoming products (LX2160AQDS), we have cases, where there
are sometimes two phy devices for one dpmac. One phy for TX lanes and
one phy for RX lanes. to handle such cases, add the support for multiple
phys in ethernet driver. The ethernet link is up if all the phy devices
connected to one dpmac report link up. also the link capabilities are
limited by the weakest phy device.
i.e. say if there are two phys for one dpmac. one operates at 10G without
autoneg and other operate at 1G with autoneg. Then the ethernet interface
will operate at 1G without autoneg.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The dpmac initalization should not depend on phy.
As the phy is not necessary to be present for dpmac to function.
Therefore, remove dpmac initialization dependency from phy.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
when there is no phy present for a dpmac, a dummy phy device is created.
when we move to multiple phy method, we need to create as many dummy phy
devices.
Change this method so that we don't need to create dummy phy devices.
We always report linkup if no phy is present.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
if an error occurs during init_phy, we should free the phydev structure
which has been allocated by phy_connect.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The phydev structure is present in both ldpaa_eth_priv and
wriop_dpmac_info. the phydev in wriop_dpmac_info is not being used
As the phydev is created based on phy_addr and bus members of
wriop_dpmac_info, it is appropriate to keep phydev in wriop_dpmac_info.
Also phy_regs is not being used, therefore remove it
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Sandbox SPL/TPL support
Various dm-related improvements
-----BEGIN PGP SIGNATURE-----
iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlu9RL4RHHNqZ0BjaHJv
bWl1bS5vcmcACgkQfxc6PpAIreYd8gf+NYAGhpiEZZ5vc3DB4Xdn2okgakbbg0QQ
/b0Lr9xQsKgZthK0rvPlH2dXxf+ViAm1iHTy8KBCFi0SHNder48Zui9uTrX0NRq8
pLZGyJPXPYbiyc4pQTEJpTth4iShcphRVio0no4sLpNQqO4aQrialSLa9fnwd9Ra
1l9mF91aaYw6cG+/ejg3UR1LfsDdQ5bjubt0Fw0wGX9UvQOAz5gz5+a17wrz6+Gx
L0gzvyfbuLUhbWB36DXikrL14DAFys2uV9aHJ5zEd53l+F7ZHWsupCO0OtN66cV7
KpPKoYG7vhLqBXKpyrW20T+BPeSyDKmDQE6wbpECmEDOvKzvW67O/w==
=Bfjm
-----END PGP SIGNATURE-----
Merge tag 'dm-9oct18' of git://git.denx.de/u-boot-dm
Test improvements to tidy up output and drop duplicate tests
Sandbox SPL/TPL support
Various dm-related improvements
Push generic defines of gpio.h out of mach-davinci to drivers/gpio
now that non-davinci architectures are beginning to use this IP.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Fix calimain build]
Signed-off-by: Tom Rini <trini@konsulko.com>
The goto label name is misspelled it should be DPMAC not DPAMC
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The target will respond to pings while doing other network handling.
Make sure that the response happens and is correct.
This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This tests that ARP requests made to this target's IP address are
responded-to by the target when it is doing other networking operations.
This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tests need to be able to pass their "unit test state" to the handlers
where asserts are evaluated. Add a function that allows the tests to set
this private data on the sandbox eth device.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use up to the max allocated receive buffers so as to be able to test
more complex situations.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If tests want to implement tx handlers, they will likely need access to
the details in the priv structure.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Make the send handler registerable so tests can check for different
things.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Store the per-device data with the device.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.
To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).
To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.
Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"
https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
Based on commit ac6e058b75be ("net: phy: dp83867: Recover from "port mirroring"
N/A MODE4") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
This patch adds support for enabling or disabling the lane swapping
(called "port mirroring" in PHY's CFG4 register) feature of the DP83867
TI's PHY device.
One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).
Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping
support in the DP83867 TI's PHY driver") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There are plenty of existing drivers that have macros like ETH_ALEN
defined in their own source files. Now that we imported the kernel's
if_ether.h to U-Boot we can reduce some duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Davanci spi driver has DM support already, this patch
add support for platdata so-that SPL can use it for
low foot-print.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Adam Ford <aford173@gmail.com>
Some boards (like omap3_logic) hang when trying to access
address 0. This happens when executing the new 'mtd list' command.
This patch enhances the checks for conditions that would
preclude mtd_probe_devices() from operating.
Fixes: 5db66b3aee ("cmd: mtd: add 'mtd' command")
Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Currently there are two ethernet drivers (mvneta.c and mvpp2.c) that
has netdev_### (eg: netdev_dbg) log macros defined in its own driver
file. This adds these log macros in a common place linux/compat.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The internal DMAC on Gen3 is 32bit only, limit the DMA address
range to 32bit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Pass the entire source data pointer to tmio_sd_addr_is_dmaable()
so we don't have to apply casts throughout the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
At present this function uses pixels but it seems more useful for it to
position in terms of characters on the screen. This also matches the
comment to the function. Update this.
Unfortunately there is one user of this function (at91). Have a crack at
fixing this, since I cannot test it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
We have a method to return the last reset as a string for humans, but not
a method that allows it to be used programmatically. Add a new method that
returns the last reset as an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present ctags emits lines with unmatched quotes which means that the
output file is invalid. This is with exuberant-ctags version 5.9~svn201103
but I also see it with plain ctags. I am not sure that it is a bug though.
Make a few minor changes in the source code to fix this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the panel can be turned on but not off, and the brightness
cannot be controlled at run-time. Add a new API function to both the panel
and backlight uclasses to handle this. Enhance the PWM backlight driver
to deal with custom levels properly and allow the backlight to be turned
on and off.
Update the test to cover thes new features.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this uclass has no tests. Add a simple one which checks the PWM
configuration, regulator and GPIO.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present version 3 messages are only supported on SPI. Add support for
using LPC as well, as used on samus.
Signed-off-by: Simon Glass <sjg@chromium.org>
This file has changed quite a bit in the last 5 years as the capabilities
of the ECs have grown. Sync it up with the copy in coreboot commit
b9141f2215.
The only change is the addition of EC_VBNV_BLOCK_SIZE_V2. This is needed
because U-Boot uses the new v2 vboot API and this is not currently fully
supported by Chromium OS firmware.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust the TPM drivers to use livetree (only one does not). Also,
sometimes TPMs can have child devices if they provide a service to the
system (such as storing secure data), so permit that.
Signed-off-by: Simon Glass <sjg@chromium.org>
All driver-model operation should return an error code. Adjust this
function to do so also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
When SPI flash operations fail it is helpful to be able to see the error
codes and where they are generated. Add logging to capture this
information for read operations.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we pass around a private pointer to specify the cros_ec device.
With driver model it makes more sense to pass the device. Update the code
to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this option applies to SPL, but it should be available in TPL
also, and separately. Change to using CONFIG_IS_ENABLED(), add a new
Kconfig option and fix up hang().
Signed-off-by: Simon Glass <sjg@chromium.org>
At present it is not possible to specify that a node should be used before
relocation (in U-Boot proper) without it also ending up in SPL and TPL
device trees. Add a new "u-boot,dm-pre-proper" boolean property for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add Kconfig options so that the RTC can be used in SPL and TPL. This is
helpful for accessing the contents of CMOS RAM, for example.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present it is not possible to enable/disable block drivers in TPL. This
is needed to provide sandbox support. Add a Kconfig option and adjust the
Makefile.
Signed-off-by: Simon Glass <sjg@chromium.org>
In some cases it is necessary to read the keyboard in early phases of
U-Boot. Update the config to allow this.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present spi_flash_cmd_read_ops() allocates and frees a few bytes of
memory every time it is called. It is faster to use the stack for this
and this is now supported by the minimum GCC version required by U-Boot.
Remove the allocation and use a variable-sized array instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present ofnode_read_fmap_entry() reads a flash map entry in a format
which is not supported by binman. To allow use to use binman-format
descriptions, update this function.
Also add a simple test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some devices have children and want to press an existing inactive child
into service when needed. Add a function to help with this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Quite a few functions do not actually modify the device that is passed in.
Update the function signatures to reflect that.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no reason why this feature should not be supported for uclass-
private data. Update the code accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present sandbox sets non-blocking I/O as soon as any input is read
from the terminal. However it does not restore the previous state on
exit. Fix this and drop the old os_read_no_block() function.
This means that we always enable blocking I/O in sandbox (if input is a
terminal) whereas previously it would only happen on the first call to
tstc() or getc(). However, the difference is likely not important.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that we don't have to deal with the command-line flag we can simplify
the code for detecting the emulator. Remove the lookup based on the SPI
specification, relying just on the device tree to locate the emulator.
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver was originally written against Chromium OS circa 2012. A few
new features have been added. Enhance the TPM driver to match. This mostly
includes a few new messages and properly modelling whether a particular
'space' is present or not.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use an enum for command values instead of open-coding them. This removes
the need for comments. Also make sure the driver returns proper error
numbers instead of -1.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present sandbox assumes that device-tree control is active, but this
may not be the case in SPL or TPL. Add some conditions to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present there are many situations where sandbox syncs the display to
the SDL frame buffer. This is a very expensive operation but is only
needed every now and then. Update video_sync() so that we can specify
whether this operation is really needed.
At present this flag is not used on other architectures. It could also
be used for reducing writeback-cache flushes but the benefit of that would
need to be investigated.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Add logging to aid debugging features in these drivers. Also drop some
code in sandbox_spi_xfer() which is not used.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we support specifying SPI flash devices to use in the device
tree and on the command line. Drop the second option, since it is a pain
to support nicely with driver model, and unnecessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
This can be used for device register access from board code.
This allows access to capabilities in the RTC chip not abstracted in
U-Boot's RTC class. E.g., device NVRAM or a tamper detection circuit.
Cc: Klaus Goger <klaus.goger@theobroma-systems.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Of CONFIG_OF_TRANSLATE is enabled, this function still returns
untranslated bogus results. Add the missing translation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The size should be decoded using of_n_size_cells(), make it so.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enables cmd_avb and its dependencies need to run the AVB tests.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
[trini: Disable for sandbox_noblk]
Signed-off-by: Tom Rini <trini@konsulko.com>
Adds a sandbox tee driver which emulates a generic TEE with the OP-TEE
AVB TA.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Fix printf warnings in ta_avb_invoke_func, slots is uint]
Signed-off-by: Tom Rini <trini@konsulko.com>
Adds configuration option OPTEE_TA_AVB and a header file describing the
interface to the Android Verified Boot 2.0 (AVB) trusted application
provided by OP-TEE.
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adds support in optee supplicant to route signed (MACed) RPMB frames
from OP-TEE Secure OS to MMC and vice versa to manipulate the RPMB
partition.
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adds a OP-TEE driver.
* Targets ARM and ARM64
* Supports using any U-Boot memory as shared memory
* Probes OP-TEE version using SMCs
* Uses OPTEE message protocol version 2 to communicate with secure world
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Adds a uclass to interface with a TEE (Trusted Execution Environment).
A TEE driver is a driver that interfaces with a trusted OS running in
some secure environment, for example, TrustZone on ARM cpus, or a
separate secure co-processor etc.
The TEE subsystem can serve a TEE driver for a Global Platform compliant
TEE, but it's not limited to only Global Platform TEEs.
The over all design is based on the TEE subsystem in the Linux kernel,
tailored for U-Boot.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Adds mmc_rpmb_route_frames() to route RPMB data frames from/to an
external entity.
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Just as /chosen may contain devices /firmware may contain devices, scan
for devices under /firmware too.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Add support for the Arm Versatile Express config bus that is
being used for exposing various subsystems via a generic
configuration bus. This driver adds support for generating
transactions on this configuration bus and can be used by
other drivers to abstract the communication with the actual
function providers.
Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
- fixes to rkimage for SPL boot via USB
- fixes to make_fit_atf.py, incl. entry-point calculation and python3
compatibility
- OP-TEE support for ARMv7-based SoCs
- fixes to RGMII/GMII selection on the RK3328
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJbt0FOAAoJECaAFcEOcohNZmcH/A1mKO0/R4tHCqFP2j0I+OuP
PClkA1HUZuD5phvPMaxdHQBwsq7sAa8AljK1oPCNkslP7mFxToUUBx7xc0vB89P/
D+XsI4uce89hIyTULR2FdhR22MOk41zaLVeNicpQ1keCNbzCwsHsHTA+B4XN/xNe
tdPpu6wN2D+g88DAv+/ebVYgjmxRvFD4qpL9bbZpOqqA8XCcD31ukCR2E4fsESgn
mzwKaKcX6SeYgTVCT8Q15SLTNI1WRUY1Y1laj1WKl4abY+HsTt4Whm9imM2l3K5W
ODj6vnFlwEC9rgdxmtXGcmBfwtyXubSfuZDrMGFAiOlyIUgpPXWZI7i8LYQbZ7s=
=NdBl
-----END PGP SIGNATURE-----
Merge tag 'rockchip-for-v2018.11-rc2' of git://git.denx.de/u-boot-rockchip
Rockchip-focused changes for v2018.11-rc2:
- fixes to rkimage for SPL boot via USB
- fixes to make_fit_atf.py, incl. entry-point calculation and python3
compatibility
- OP-TEE support for ARMv7-based SoCs
- fixes to RGMII/GMII selection on the RK3328
Signed-off-by: Tom Rini <trini@konsulko.com>
Using PHY internal delays in combination with the phy-mode
rgmii-id/rxid/txid was not possible. Only rgmii was supported.
Now we can disable rockchip's gmac delay lines and also use
rgmii-id/rxid/txid.
Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add
handling for RGMII_ID/RXID/TXID") for mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of
RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii()
to enable the RX delay.
The MASK was used in a wrong way.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Reviewed-by: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds the SPI driver for the MediaTek MT7688 SoC (and
derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
Gateway additionally with an SPI NAND on CS1.
Note that the SPI controller only supports a max transfer size of 32
bytes. This driver implementes a workaround to enable bigger xfer
sizes to speed up the transfer especially for the SPI NAND support.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Piotr Dymacz <pepe2k@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
device is supported.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Jagan Teki <jagan@openedev.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
This patch adds support for 2 new XMC (Wuhan Xinxin Semiconductor
Manufacturing Corp) SPI NOR chips.
This support can be enabled by selecting the SPI_FLASH_XMC Kconfig
option.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change to use managed resource function devm_kcalloc(),
so it will auto free memory when driver is removed.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add a PHY driver for the R-Car Gen3 which allows configuring
USB OTG PHY on Gen3 into host mode and toggles VBUS in case a
dedicated regulator is present.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The Arm Versatile Express I2C controller is a simple register-based
controller that uses a register to control the state of the SCL and
SDA lines. Add support for it.
Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This is the PR for SPI-NAND changes along with few spi changes.
[trini: Re-sync changes for ls1012afrwy_qspi*_defconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add DM support to the SH QSPI driver while retaining non-DM support.
The later is required as this driver is used in SPL which has a size
limitation of 16 kiB.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
[jagan: use proper commit head]
Reviewed-by: Jagan Teki <jagan@openedev.com>
Convert fsl_qspi.c to complete DM mode.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Tested-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Tested-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add code to reset all reset signals as in SPI DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Release reset when _remove().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
There should not be a 'nand' command, a 'sf' command and certainly not
a new 'spi-nand' command. Write a 'mtd' command instead to manage all
MTD devices/partitions at once. This should be the preferred way to
access any MTD device.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Instead of collecting partitions in a flat list, create a hierarchy
within the mtd_info structure: use a partitions list to keep track of
the partitions of an MTD device (which might be itself a partition of
another MTD device), a pointer to the parent device (NULL when the MTD
device is the root one, not a partition).
By also saving directly in mtd_info the offset of the partition, we
can get rid of the mtd_part structure.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Using an MTD device (resp. partition) name in mtdparts is simple and
straightforward. However, for a long time already, another name was
given in mtdparts to indicate a device (resp. partition) so the
"mtdids" environment variable was created to do the match.
Let's create a function that, from an MTD device (resp. partition)
name, search for the equivalent name in the "mtdparts" environment
variable thanks to the "mtdids" string.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
The current parser is very specific to U-Boot mtdparts implementation.
It does not use MTD structures like mtd_info and mtd_partition. Copy
and adapt the current parser in drivers/mtd/mtd-uclass.c (to not break
the current use of mtdparts.c itself) and write some kind of a wrapper
around the current implementation to allow other commands to benefit
from this parsing in a user-friendly way.
This new function will allocate an mtd_partition array for each
successful call. This array must be freed after use by the caller.
The given 'mtdparts' buffer pointer will be moved forward to the next
MTD device (if any, it will point towards a '\0' character otherwise).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
The user might want to trigger the probe of any MTD device, export these
functions so they can be called from a command source file.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
The rk3188 works nicely with the rockchip mmc driver, so we just need
to add the different compatible for it - as used in the Linux kernel.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
While trying to enable the dw_mmc on rk3188 I managed to confuse
and hang the dw_mmc controller into not delivering further data.
The fifo state never became ready and the driver was iterating in
the while loop reading 0-byte packets forever.
So inspired by how other implementations handle this, check the fifo-
state beforhand and add a timeout to catch any glaring fifo issues
without hanging uboot altogether.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
MSM uses the chipidea controller IP, however it requires
to reinit the phy after controller reset. in EHCI mode there's a
dedicated callback for it.
In device mode however there's no such callback.
Add implementaion of ci_init_after_reset() to implement the above
requirement in case CI_UDC driver is used.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
MSM variant of Chipidea must reinitalize the phy
after controller reset.
Introduce ci_init_after_reset() weak function that
can be used to achieve the above init.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Add a PHY driver for the Qualcomm dragonboard 410c which
allows switching on/off and resetting the phy connected
to the EHCI controllers and USBHS controller.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
platdata_auto_alloc_size was not initialized in structure.
Caused null pointer dereference when configuring device as
gadget.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Since commit 7b3b74d321 ("serial: serial_stm32: Enable overrun")
on STM32F7xx based boards, the first lines of serial output are
missing during boot (we no more see the U-Boot release version,
board model and DRAM size).
By enabling the uart FIFO on STM32F7, the complete U-boot log
can be sent correctly.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The Arm Versatile Express and Juno development boards contain an
OSC clock generator that can be accessed through the Versatile
Express config bus. The generators are quite often being controlled
by some MCU and the config bus offers a uniform way of exposing them.
Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add a test which verifies that all subnodes under "/firmware"
nodes are scanned.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added 'imply FIRMWARE' to sandbox Kconfig to fix test failures, fixed
ordering of lines in arch/sandbox/dts/test.dts and test/dm/Makefile,
updated #if condition in drivers/firmware/firmware-uclass.c:
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no prompt string for FIRMWARE config. Without this,
FIRMWARE config cannot be enabled through menuconfing or
config file. Fix this by adding prompt summary.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since there is no canonical "board device" that can be used in board
files, it is difficult to use DM function for board initialization in
these cases.
Hence, add a uclass that implements a simple "board device", which can
hold devices not suitable anywhere else in the device tree, and is also
able to read encoded information, e.g. hard-wired GPIOs on a GPIO
expander, read-only memory ICs, etc. that carry information about the
hardware.
The devices of this uclass expose methods to read generic data types
(integers, strings, booleans) to encode the information provided by the
hardware.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
We cannot use device structures to disable devices, since getting
them with the API functions would bind and activate the device, which
would fail if the underlying device does not exist.
Reviewed-by: Simon Glass <sjg@chromium.org>
Implement a set of functions to manipulate properties in a live device
tree:
* ofnode_write_prop() to set generic properties of a node
* ofnode_write_string() to set string properties of a node
* ofnode_set_enabled() to either enable or disable a node
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbrkHRAAoJEO1FWZTaC520r3UQAIBntTglI1QK7YizVxZ1x9DL
42oSEIwkuN0wbndR7Jzx4EPPFJ8yX4v3stoxC3qS5DQ9kHMzuqRQcIDYbcn5Qy7Z
vd0mBUmpkRjr988pSaSHVQ8kPasncb545fCUumrXrCmhuG5Ea2Itw1zLdsTf7X5n
39KxFUOAR63BDCT0ZlR4VyMo01GxxHWCzRQH/rOWVzOcJsWF7R52hWIBBzVDxKPv
HF9SYaAB0PTFgSjJx5wYQ4xPdHVUp+svtYSJE8JYzEr/BvOVtL2iEi4t2rk19CrX
IaVMFydlv2iDgWdoSZFCCN/6lGDWSv1LWPDglWhLQhOYvrJOjZfgzzeAGU7wqoz4
JVjSLf6dHeOma55dbP/epDmyDFqWIfNOQ3uP4RM57xJ0PXQuT7ACVJctr6kHVTGL
1ZZxPdKSSf9lvtzoogPTTYRD5Ry7ud3sYZ0v3OHN1sbVcaHaVoHPeXeSz1sLg3Q+
zhUo1lXx4FcTz9R1fafdcqqAk/YGMZ7sBE+uYJPgExnApxrZID9IiOdGIBxo8jiK
ozLmaCIDqRyu/qhQW9WMri1tvYdKwq/739gBvvcIcrLR5RzfNUdwWjhtBokPQQnS
WZNqd3/0N8ZFGz7V0GOxCDnAo4nwQeZVFGMtTpoCtjPvr6DWBHsEUlQHTT3dQKz/
TXygMYUYGA+/vux0Dt4I
=XRFI
-----END PGP SIGNATURE-----
Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq
Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.
With DM_GPIO and DM_MMC translating GPIO_ACTIVE_LOW, any boards
using the 'cd-invert' option will no longer need to do this. This
patch removes the support for 'invert' from the MMC driver.
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Fix warning over when !DM_GPIO]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add a driver that supports Maxim 1 wire EEPROMs families
DS24B33 and DS2431.
Can be extended for other families as well.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
[eugen.hristev@microchip.com: reworked driver]
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
When a new device is discovered, this may be a w1 eeprom device.
Attempt to find the proper node and driver from the w1-eeprom subsystem.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
We might want to access data stored onto one wire EEPROMs.
Create a framework to provide a consistent API.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
[eugen.hristev@microchip.com: reworked patch]
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add a bus driver for bitbanging a 1-Wire bus over a GPIO.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
[eugen.hristev@microchip.com: fixed some issues]
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
We might want to use 1-Wire devices connected on boards such as EEPROMs in
U-Boot.
Provide a framework to be able to do that.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
[eugen.hristev@microchip.com: reworked]
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Add a function to find the block device descriptor of the parent
device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
[trini: Move function declaration to avoid warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for Arm Mali Display Processors DP500, DP550 and DP650.
Only one layer is being used to display the console or boot logo,
even if more layers are supported in the hardware.
Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Some devices offer a text-based OSD (on-screen display) that can be
programmatically controlled (i.e. text displayed on).
Add a uclass to support such devices.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The EFI subsystems needs to know the size of the terminal. If the
environment variable
stdout = serial,vidconsole
this size cannot be read from the video console. So the EFI subsystem
sends escape sequences to read the size. With this patch we get support
for the following escape sequences:
ESC "7" Save cursor position
ESC "8" Restore cursor position
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Recently the FMan Port and MAC compatibles were changed. This patch
aligns the FMan Port and MAC compatibles to the new FMan device tree
binding document. The FMan device tree binding document can be found
in the Linux kernel version 3.18.0, commit
297d35fd2a7d3fbd4e5c0f0c1c18213117ba11ba
./Documentation/devicetree/bindings/powerpc/fsl/fman.txt
This patch doesn't affect legacy compatibles support.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Enable support for ICID setup of qman portals and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Memory reserved for Management Complex needs to be cleaned before any
usage.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[York S: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The iommu-map property in the fsl-mc node is updated by
valid stream-ids by u-boot. This patch is to fixup this
property for LS208x and LS1088.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add ahci compatible support for ls1021a soc.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: York Sun <york.sun@nxp.com>
At present the MMC subsystem maintains its own list of MMC devices.
This cannot work with driver model when CONFIG_BLK is enabled, use
blk_dread to replace previous mmc read interface, use
mmc_get_blk_desc to get the mmc device property.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Based on dt-specs fixed-link doesn't require phy-handle to be used.
Fix driver to only read phy related setting when phy-handle is found.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
A lot of goodness in this release. We're *very* close to running the
UEFI Shell and SCT natively. The only missing piece are HII protocols.
- FAT write support (needed for SCT)
- improved FAT directory support (needed for SCT)
- RTC support with QEMU -M virt
- Sandbox support (run UEFI binaries in Linux - yay)
- Proper UTF-16 support
- EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell)
- EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell)
- Fix window size determination
- Fix Tegra by explicitly unmapping RAM
- Clean up handle entanglement
- Lots of generic code cleanup
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJbq6+cAAoJECszeR4D/txgV1cP+wZPVsY/kRDwCZ8PODOIyLW/
YWWX0CHOUNIXcvWyrQQVflRKE7IbsoPNU+PxOze/toBZvNGZofCqd/P0sT0kk8UU
/aQ55+Hn8/N4etysKxhk2uszBuEXZsOdprNV3H7tO9vKsMHpImAdLvIyviYK0eCF
WnNsmDVFv/W4M5IWDJrS7KqwTuLPYE5Xli9BW/O2qi8NOvpfyb4EEqdL7OHyHAxe
8zpzyaRXJkPcgPkJ6z3WZ+BmAuXSl5DsLWqfsnZJQzkXatRhT8PneRk787e+xK3A
OEFarj5t/94T1KivxquM9iYi0NzwGWrrCfRzbQh5klV4Z/bRYHbGQ92j6iZyfnpj
0zvWrJCalDaUz310BKZDyzKYQnoDj5/iYaMJHtaG6zmkXCzM41kniGKxuy/3IpTB
ozeFtH2AOwlAFZRIzQiazkyU0bizis2Y/K4xzOQczvVajdLW0DsLXL/hyqaFaGO2
3oVK350FXMHKa1UhpsG05aoQvyYq8N4YVEfOSdBKah8qhhMG8zZ2IaX5oheZJjr4
yPV8iaSj8trX3mI9clsnX9YT7qJdcS188JYSii+8SVpVH4VpgwvUSHfDqznn7JNz
COue6rFo9sg55Le9OsoxUgaQ5GO4oz+5iGmfyBmOtQ3n83JxmP4CJK84Ykw2i9fi
sxJR6aNtktsLhfYhlDO/
=ZuJG
-----END PGP SIGNATURE-----
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-09-26
A lot of goodness in this release. We're *very* close to running the
UEFI Shell and SCT natively. The only missing piece are HII protocols.
- FAT write support (needed for SCT)
- improved FAT directory support (needed for SCT)
- RTC support with QEMU -M virt
- Sandbox support (run UEFI binaries in Linux - yay)
- Proper UTF-16 support
- EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell)
- EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell)
- Fix window size determination
- Fix Tegra by explicitly unmapping RAM
- Clean up handle entanglement
- Lots of generic code cleanup
[trini: Fixup merge conflict in include/configs/qemu-arm.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
max-speed property is part of phynode and it has to be
read using ofnode_read_u32_default(). This fixes the issue
of incorrect max-speed read from DT.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch modifies PL bitstream loading sequence as per
latest Xilfpga which supports all variants of bitstream images
generated from vivado and from bootgen. With this new change in
Xilfpga, uboot doesn't need to validate and swap bitstream as it will
be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting
PMUFW version before skipping the validation and swap sequence as there
can be old PMUFW which doesn't supports this feature. In this case, driver
uses old way of PL bitstream loading sequence.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
AM654 uses a UART controller that is compatible (partially) with
existing OMAP UART, Introduce a compatible for adding support
for this controller.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When using device model this sort of hardcoded limits aren't used or
necessary.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
The loop in ahci_start_ports() is looping over the maximum number of
SCSI devices in the system, which can be larger than the amount of ports
a particular AHCI controller has. The extra looping isn't directly
harmful because the link_port_map bitmap won't have the bit set for a
nonexistent port, but it is wasteful. Replace the loop limit with the
port count of the AHCI controller instead.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
The MMC card detect pin is connected to gpio127 on omap3_logic.
When setting up the pbias register for MMC, let's also enable
gpio_127 for the card detect. As part of the package deal,
gpio_126 and gpio_129 are also enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
This adds support for the ARM PL022 SPI controller for the standard
variant (0x00041022) which has a 16bit wide and 8 locations deep TX/RX
FIFO.
A few parts were borrowed from the Linux kernel driver.
Cc: Armando Visconti <armando.visconti@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
On some boards using TI CPSW, it may be possible that
PHY address was not latched correctly, and the actual
address that the phy responds on is different from that
set in device-tree. For example, see this problem report
on beaglebone black:
https://groups.google.com/d/msg/beagleboard/9mctrG26Mc8/1FuI_i5KW10J
Add support to check for this condition and use the
detected phy address when its safe to do so.
Also, add a public API that exposes the phy address of
a given slave. This can be used to update device-tree that
is passed to Linux kernel.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
With this patch, PL031 driver is converted to driver-model-compliant
driver. In addition, CONFIG_SYS_RTC_PL031_BASE is no longer valid.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
CSI H can be used to position the cursor. The calling application may
specify a location that is beyond the limits of the screen. This may
lead to an illegal memory access.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
%s/efi_simple_input_interface/efi_simple_text_input_protocol/
We should be consistent in the naming of the EFI protocol interface
structures. The protocol is called EFI_SIMPLE_TEXT_INPUT_PROTOCOL.
%s/ExtendedVerification/extended_verification/
Use consistent naming of function parameters. Do not use CamelCase.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Balance debug message in the partition allocation/removal process in
order to keep track of them more easily.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
UBI selects MTD_PARTITIONS which is the symbol to compile
drivers/mtd/mtdpart.c. Unfortunately, the symbol was not defined in
Kconfig and this worked only with board files defining it. Fix this by
adding a boolean in Kconfig so boards defined by defconfig files only
will work as expected.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Add support for the MX35LF2GE4AB chip, which is similar to its cousin
MX35LF1GE4AB, with two planes instead of one.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Add minimal support for the MX35LF1GE4AB SPI NAND chip.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Add support for the W25M02GV chip.
Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more devices
afterwards.
Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.
In its current state, this framework supports the following features:
- single/dual/quad IO modes
- on-die ECC
Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Some controllers are exposing high-level interfaces to access various
kind of SPI memories. Unfortunately they do not fit in the current
spi_controller model and usually have drivers placed in
drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI
memories in general.
This is an attempt at defining a SPI memory interface which works for
all kinds of SPI memories (NORs, NANDs, SRAMs).
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Add an intermediate layer to abstract NAND device interface so that
some logic can be shared between SPI NANDs, parallel/raw NANDs,
OneNANDs, ...
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in a
raw/ subdirectory, to ease the addition of a core file in nand/ and the
introduction of a spi/ subdirectory specific to SPI NANDs.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
There is no reason to have NAND, SPI flashes and UBI sections outside of
the MTD submenu in Kconfig.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Some MTD sublayers/drivers are implementing ->_read/write() and
not ->_read/write_oob().
While for NAND devices both are usually valid, for NOR devices, using
the _oob variant has no real meaning. But, as the MTD layer is supposed
to hide as much as possible the flash complexity to the user, there is
no reason to error out while it is just a matter of rewritting things
internally.
Add a fallback on mtd->_read() (resp. mtd->_write()) when the user calls
mtd_read_oob() (resp. mtd_write_oob()) while mtd->_read_oob() (resp.
mtd->_write_oob) is not implemented. There is already a fallback on the
_oob variant if the former is used.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Unlike what's done in mtd_read/write(), there are no checks to make sure
the parameters passed to mtd_read/write_oob() are consistent, which
forces implementers of ->_read/write_oob() to do it, which in turn leads
to code duplication and possibly errors in the logic.
Do general sanity checks, like ops fields consistency and range checking.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Peter Pan <peterpandong@micron.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
[Miquel: squashed the fix about the chip's size check]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
There's no reason for having mtd_write_oob inlined in mtd.h header.
Move it to mtdcore.c where it belongs.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Some MTD sublayers/drivers are implementing ->_read/write_oob() and
provide dummy wrappers for their ->_read/write() implementations.
Let the core handle this case instead of duplicating the logic.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
- Multiples updates to the turris boards / platform
- Changes / enhancements to the Marvell PHY drivers, mainly
to support the turris platform
- Many fixes and enhancements to the pxa3xx NAND driver
- Fixes for the UART boot mode in kwboot
- Misc minor changes to other 32bit and 64bit boards
This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The
'phy-invert' DT property defines the inverted signals.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
add delay before processing the status flags in pxa3xx_nand_irq().
Signed-off-by: David Sniatkiwicz <davidsn@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
c: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI).
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Add comments with timing parameter names and some details about
nand layout fileds.
Remove unneeded definition.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Replace the hardcoded value of page chink with value that
depends on flash page size and ECC strength.
This fixes nand access errors for 2K page flashes with 8-bit ECC.
Move the initial flash commannd function assignment past the ECC
structures initialization for eliminating usage of hardcoded page
chunk size value.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for 2KB page 8-bit ECC strength flash layout
Signed-off-by: Victor Axelrod <victora@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
In the current driver, OOB bytes are accessed in raw mode, and when a
page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the
driver must read the whole spare area (64 bytes in case of a 2k page,
16 bytes for a 512 page). The driver was only reading the free OOB
bytes, which was leaving some unread data in the FIFO and was somehow
leading to a timeout.
We could patch the driver to read ->spare_size + ->ecc_size instead of
just ->spare_size when READOOB is requested, but we'd better make
in-band and OOB accesses consistent.
Since the driver is always accessing in-band data in non-raw mode (with
the ECC engine enabled), we should also access OOB data in this mode.
That's particularly useful when using the BCH engine because in this
mode the free OOB bytes are also ECC protected.
Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support")
Cc: stable@vger.kernel.org
Reported-by: Sean Nyekjær <sean.nyekjaer@prevas.dk>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.
When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.
When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:
| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |
So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.
When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:
| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC |
So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.
Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.
To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.
In order to implement reading of the last chunk, this commit:
- Adds a number of new fields to the pxa3xx_nand_info to describe how
many full chunks and how many chunks we have, the size of full
chunks and partial chunks, both in terms of data area and spare
area.
- Fills in the step_chunk_size and step_spare_size variables to
describe how much data and spare should be read/written for the
current read/program step.
- Reworks the state machine to accommodate doing the additional read
or program step when a last partial chunk is used.
This commit is taken from Linux:
'commit c2cdace755b'
("mtd: nand: pxa3xx_nand: add support for partial chunks")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.
This commit is taken from Linux:
'commit 154f50fbde53'
("mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.
Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ident()
and the second group later.
Let's split pxa3xx_nand_config in two halves, and set the
parameters that depend on the device geometry once this is known.
This commit is taken from Linux:
'commit 66e8e47eae65'
("mtd: pxa3xx_nand: Fix initial controller configuration")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transferred data.
However, the initial chunk size is used in a non-split way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).
Thus, the initial chunk size should be 2048 as well.
On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:
[..]
pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device
pxa3xx-nand f10d0000.nand: Wait time out!!!
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
nand: Micron MT29F8G08ABABAWP
nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224
This commit is taken from Linux:
'commit c7f00c29aa8'
("mtd: pxa3xx_nand: Increase the initial chunk size")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.
This commit is taken from Linux:
'commit b226eca2088'
("nand: pxa3xx: Increase READ_ID buffer and make the size static")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase
This patch is taken from Linux:
'commit 21fc0ef9652f'
("mtd: nand: pxa3xx-nand: fix random command timeouts")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
When the nand is first probe, and upon the first command start, the
status bits should be cleared before the interrupts are unmasked.
This commit is taken from Linux:
'commit 0b14392db2e'
("mtd: nand: pxa3xx_nand: fix early spurious interrupt")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Since the pxa3xx_nand driver was added there has been a discrepancy in
pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min.
This brings us into line with the current Linux code.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The initial buffer is used for the initial commands used to detect
a flash device (STATUS, READID and PARAM).
ONFI param page is 256 bytes, and there are three redundant copies
to be read. JEDEC param page is 512 bytes, and there are also three
redundant copies to be read. Hence this buffer should be at least
512 x 3. This commits rounds the buffer size to 2048.
This commit is taken from Linux:
'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for changing clock rate and parent clock for Armada 37xx
peripheral clocks.
Only clocks which can be disabled (.can_gate is true) can have parent
or rate changed.
This is needed so that Turris Mox can change SPI clock in device tree.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
This adds a weak definition of comphy_update_map to comphy_core,
which does nothing. If this function is defined elsewhere, for example
in board file, the board file can change some parameters of SERDES
configuration.
This is needed on Turris Mox, where the SERDES speed on lane 1 has to
be set differently when SFP module is connected and when Topaz Switch
module is connected.
This is a temporary solution. When the comphy driver for armada-3720
will be added to the kernel, the comphy driver in u-boot shall also be
updated and this should be done differently then.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Adds ofnode_by_prop_value() to search for nodes with a given property
and value, an ofnode version of fdt_node_offset_by_prop_value().
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
commit 30a90f56c3 ("dm: core: add functions to get memory-mapped I/O
addresses") introduced a devfdt_remap_addr_index() routine but it does
not make use of the index parameter.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
All Linux firmware drivers are put under "/firmware" node
and it has support to populate "/firmware" node by default.
u-boot and Linux can share same DTB. In this case, driver
probe for devices under "/firmware" will not be invoked
as "/firmware" does not have its own "compatible" property.
This patch scans "/firmware" node by default like "/clocks".
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Create separate function for scanning node by path and
move "/clock" node scan code into that function.
This will be usable if scanning of more node is required.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a driver to configure the SerDes (Serializer/Deserializer) lanes on
the MPC83xx architecture.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
It's useful to have the reset status of the SoC printed out during reset
(e.g. to learn whether the reset was caused by software or a watchdog).
As a first step to implement this, add a get_status method to the
sysreset class, which enables the caller to get printable information
about the reset status (akin to get_desc in the CPU uclass).
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Add vbus-supply regulator support.
On some board vbus is not controlled by the phy but by
an external regulator.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Incorrect type of size variable results in 0 being
returned for sdram sizes greater than or equal to
4GB.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Add code to reset all reset signals as in gpio DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Enabled get_function support for dwapb where the function will
return the state of GPIO port.
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Last user of this driver went away in May 2017, in
commit eb5ba3aefd ("i2c: Drop use of CONFIG_I2C_HARD")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
When used with a device tree, this will extract the card detect
and write protect pins from the device tree and configure them
accordingly. This assumes the GPIO_ACTIVE_LOW/HIGH is supported
by da8xx_gpio.
Signed-off-by: Adam Ford <aford173@gmail.com>
With CONFIG_BLK becoming a requirement, the Davinci MMC driver
needs to be updated with DM_MMC support. Since SPL is tiny and
many boards do not support DM in SPL, this retains the backwards
compatibility for those boards who need to initialize MMC manually
in SPL.
Signed-off-by: Peter Howard <phoward@gme.net.au>
Signed-off-by: Adam Ford <aford173@gmail.com>
The getcd and getwp functions when DM_MMC is enabled are
assumming the DM_GPIO is enabled. In cases (like SPL) where
DM_GPIO may not be enabled, wrap these calls in an #ifdef
Signed-off-by: Adam Ford <aford173@gmail.com>
Platforms with limited resources in SPL may enable OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree. This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Platforms with limited resources in SPL may enably OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree. This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.
Signed-off-by: Adam Ford <aford173@gmail.com>
Platforms with limited resources in SPL may enably OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree. This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.
Signed-off-by: Adam Ford <aford173@gmail.com>
The driver was developed with references for more than just
dra7, but never included. At least for omap3, this appears
to be functional.
Signed-off-by: Adam Ford <aford173@gmail.com>
The GPIO bank numbers do not appear in the device tree, so this
patch makes the gpio name based on the address
(ie gpio@49054000_31 vs gpio4_31)
adam
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
With DM and device tree support, let's use the GPIO_ACTIVE_HIGH
and GPIO_ACTIVE_LOW from the device tree as they are intended.
Signed-off-by: Adam Ford <aford173@gmail.com>
The GPIO banks are broken up into two 16-bit registers for each
bank set. Unfortunately, the math that determines how to shift
blindly shifted by the number of the gpio. This worked for gpio
numbers under 32, but higher gpio's are broken. This fixes the
gpio index, so the bank is passed and the shift amount within
the register is passed now instead of the gpio number.
Fixes: 8e51c0f25406("dm: gpio: Add DM compatibility to
GPIO driver for Davinci")
Signed-off-by: Adam Ford <aford173@gmail.com>
AM654 has an arasan sdhci controller and a mmc phy attached to it.
Add basic support for K3 specific arasan sdhci controller.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add support for K3 based remoteproc driver that
communicates with TISCI to start start a remote processor.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
K3 specific SoCs have a dedicated microcontroller for doing
resource management. Any HLOS/firmware on compute clusters should
load a firmware to this microcontroller before accessing any resource.
Adding support for loading this firmware.
After the K3 system controller got loaded with firmware and started
up it sends out a boot notification message through the secure proxy
facility using the TI SCI protocol. Intercept and receive this message
through the rproc start operation which will need to get invoked
explicitly after the firmware got loaded.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Existing rproc_init() api tries to initialize all available
remoteproc devices. This will fail when there is dependency
among available remoteprocs. So introduce a separate api
that allows to initialize remoteprocs individually based
on id.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Secure Proxy module manages hardware threads that are meant
for communication between the processor entities. Adding
support for this driver.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Devices from the TI K3 family of SoCs like the AM654x contain a Device
Management and Security Controller (SYSFW) that manages the low-level
device control (like clocks, resets etc) for the various hardware
modules present on the SoC. These device control operations are provided
to the host processor OS through a communication protocol called the TI
System Control Interface (TI SCI) protocol.
This patch adds a system reset driver that communicates to the system
controller over the TI SCI protocol for allowing to perform a system-
wide SoC reset.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.
This patch adds a power domain driver that communicates to the system
controller over the TI SCI protocol for performing power management of
various devices present on the SoC. Various power domain functionalities
are achieved by the means of different TI SCI device operations provided
by the TI SCI framework.
This code is loosely based on the drivers/soc/ti/ti_sci_pm_domains.c
driver of the Linux kernel.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
There are cases where there are more than one power domain
attached to the device inorder to get the device functional.
So add support for enabling power domain based on the index.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.
This patch adds a clock driver that communicates to the system
controller over the TI SCI protocol for performing clock management of
various devices present on the SoC. Various clock functionality is
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.
This code is loosely based on the drivers/clk/keystone/sci-clk.c driver
of the Linux kernel.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.
This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management of
various devices present on the SoC. Various reset functionalities are
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.
This code is loosely based on the drivers/reset/reset-ti-sci.c driver of
the Linux kernel.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add a reset operations function pointer to support querying the current
status of a reset control.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
To support scenarios where a firmware device node has subnodes that
have their own drivers automatically scan the DT and bind those when
the firmware device gets bound.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
TI-SCI message protocol provides support for controlling of various
physical cores available in SoC. In order to control which host is
capable of controlling a physical processor core, there is a processor
access control list that needs to be populated as part of the board
configuration data.
Introduce support for the set of TI-SCI message protocol apis that
provide us with this capability of controlling physical cores.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Since system controller now has control over SoC power management, it
needs to be explicitly requested to reboot the SoC. Add support for
it.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
In general, we expect to function at a device level of abstraction,
however, for proper operation of hardware blocks, many clocks directly
supplying the hardware block needs to be queried or configured.
Introduce support for the set of SCI message protocol support that
provide us with this capability.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
TI-SCI message protocol provides support for management of various
hardware entitites within the SoC. Introduce the fundamental
device management capability support to the driver protocol
as part of this change.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
TI-SCI message protocol provides support for board configuration
to assign resources and other board related operations.
Introduce the board configuration capability support to the driver protocol
as part of this change.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Texas Instrument's System Control Interface (TI SCI) message protocol is
used in Texas Instrument's System on Chip (SoC) such as those in the K3
family AM654 SoC to communicate between various compute processors with
a central system controller entity.
The TI SCI message protocol provides support for management of various
hardware entities within the SoC. Add support driver to allow
communication with system controller entity within the SoC using the
mailbox client.
This is mostly derived from the TI SCI driver in Linux located at
drivers/firmware/ti_sci.c.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Add driver model support for OMAP_SERIAL while reusing
the functions in ns16550.c
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
Following build warning appears when pinctrl-single is built for ARM64:
In file included from drivers/pinctrl/pinctrl-single.c:10:0:
drivers/pinctrl/pinctrl-single.c: In function ‘single_configure_pins’:
./arch/arm/include/asm/io.h:43:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define __arch_getw(a) (*(volatile unsigned short *)(a))
Fix this by using phys_addr_t for variable reg instead of u32
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
timer_pre_probe() tries to populate the clock rate from DT. omap
timer driver tries to overwrite this value irrespective of the value
populated fro DT. So update this value only when DT doesn't populate
the clock rate.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In order to handle counter overflows use 64 bit values for counter.
Also load the initial value during probe.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The strobe dll code is ported from Linux Kernel:
drivers/mmc/host/sdhci-esdhc-imx.c
The comments are from the above file,
"For HS400 eMMC, there is a data_strobe line. This signal is generated
by the device and used for data output and CRC status response output
in HS400 mode. The frequency of this signal follows the frequency of
CLK generated by host. The host receives the data which is aligned to the
edge of data_strobe line. Due to the time delay between CLK line and
data_strobe line, if the delay time is larger than one clock cycle,
then CLK and data_strobe line will be misaligned, read error shows up.
So when the CLK is higher than 100MHz, each clock cycle is short enough,
host should configure the delay target. "
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Add HS400 support.
Selecting HS400 needs first select HS200 according to spec, so use
a dedicated function for HS400.
Add HS400 related macros.
Remove the restriction of only using the low 6 bits of
EXT_CSD_CARD_TYPE, using all the 8 bits.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Replace clrsetbits on ODR register (2 operations: one read + one write)
by writing on the correct bit (SET or RESET) of the BSRR register
(only 1 write operation).
Moreover this register if safe for simultaneous access by 2 master on
the bus.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This patch adds support for :
- Rate calculation through muxes and generic dividers
- Basic gate setting propagation
- Reparenting for muxes
- Clock rate setting through generic dividers without reparenting
Support is only added to the Composite VPU and VAPB clocks in order
to support the Video Processing Unit Power Domain clock setup.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Amlogic Meson SoCs embeds a specific Power Domain dedicated to the
Video Processing Unit.
This patch implements support for this power domain in preparation of the
future support for the Video display support in U-Boot.
This driver will depend on changes in the clock driver to handle the setup
of the VPU and VAPB clocks configured from DT using assigned-clocks entries.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In int-ll64.h, we always use the following typedefs:
typedef unsigned int u32;
typedef unsigned long uintptr_t;
typedef unsigned long long u64;
This does not need to match to the compiler's <inttypes.h>.
Do not include it.
The use of PRI* makes the code super-ugly. You can simply use
"l" for printing uintptr_t, "ll" for u64, and no modifier for u32.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Replace stm32_serial_setparity by stm32_serial_setconfig
which allows to set serial bits number, parity and stop
bits number.
Only parity setting is implemented.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Replace setparity by more generic setconfig ops
to allow uart parity, bits word length and stop bits
number change.
Adds SERIAL_GET_PARITY/BITS/STOP macros.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add test to avoid access to rx buffer when this buffer is empty.
In this case directly call getc() function to avoid issue when tstc()
is not called.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If the OOB size is not multiple of the cache line size, the ARMv7
cache operation still prints "Misaligned operation at range".
=> nand info
Device 0: nand0, sector size 256 KiB
Page size 4096 b
OOB size 224 b
Erase size 262144 b
subpagesize 4096 b
options 0x00104200
bbt options 0x00060000
=> nand dump 0
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
...
The cache flushing operations won't happen in this case to cover all of
the range to fix this by making sure we have things aligned.
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Reword the commit message to be clear this is a direct problem
rather than just a warning]
The existing imx_watchdog driver is compatible with mx25 chipsets.
Add a WDOG1_BASE_ADDR define for the base address and enable the driver
in watchdog's Makefile.
To use the driver, a board must define CONFIG_IMX_WATCHDOG and
CONFIG_HW_WATCHDOG.
This fixes an issue when booting an mx25 chip via usb/serial. In this
case, the boot rom will always enable the watchdog. If u-boot is running
in interactive mode and the watchdog is not serviced, the system is
rebooted when the watchdog expires.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
The dev_get_priv(dev) is used twice in the probe function.
Replace the second invocation with priv variable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add code to reset all reset signals as in usb DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Only PCI device 1 and 2 is populated on the R-Car Gen2 internal
PCIe controller. Ignore all other devices. This fix prevents a
duplication of OHCI controller response on slot 0 and 1.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Add support for operating a PHY attached to ehci-pci. There are
systems where the EHCI controller is internally wired to a PCI
bus and has a PHY connected to it as well, ie. the R-Car Gen2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Add timer driver for the Designware APB Timer IP. This is present
for example on the Altera SoCFPGA chips.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
musb stop is musb core call during unregister or shutting down
gadget or host musb. For graceful exit add musb_platform_exit
on musb_stop so-that it can exit the musb platform driver as well.
Tested-by: Chen-Yu Tsai <wens@csie.org> # A33-OlinuXino
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
musb have platform ops to do proper graceful exit,
so add the exit call and move musb platform exit code
instead of keeping it in driver remove.
This make proper shutdown of musb where .remove will
call disable, exit serially via musb_stop.
Tested-by: Chen-Yu Tsai <wens@csie.org> # A33-OlinuXino
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
reset0 is not available for sun4i, 5i and 7i so access
the reset0 offset from ccm via driver data for relevant
Allwinner SoC. this will eventually drop the existing
ifdef for SUN6I.
Tested-by: Chen-Yu Tsai <wens@csie.org> # A33-OlinuXino
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Allocate struct phy in private structure instead of allocating
locally and assign it to a pointer. This eventually fix miss
alignment phy which is used in another functions.
Tested-by: Chen-Yu Tsai <wens@csie.org> # A33-OlinuXino
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
When MUSB is operating in peripheral mode, probe registering
musb core using musb_register which intern return int value
for validation. so there is no scope to preserve struct musb
pointer but the same can be used in .remove musb_stop.
So fix this by return musb_register with struct musb pointer.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Purna Chandra Mandal <purna.mandal@microchip.com>
Tested-by: Chen-Yu Tsai <wens@csie.org> # A33-OlinuXino
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Also add a 'drv' parameter to filter the children to remove/unbind.
Exporting those functions is a preparatory work for the addition of the
bind/unbind commands.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Also add device_find_global_by_ofnode() that also find a device based on
the OF node, but doesn't probe the device.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Command "dm tree" dumps the devices with class, driver, name information.
Add the index of the device in the class too, because the information is
useful for the bind/unbind commands.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This function is the reciprocal of uclass_find_device().
It will be used to print the index information in dm tree dump.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add an entry in usb_gadget_controller_number() for the DWC3 gadget
controller. Without it, it is not possible to bind the USB Ethernet driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
With upcoming changes that require CONFIG_BLK, this broke
USB Mass Storage on the OMAP3 boards because if CONFIG_BLK is
enabled, it assumes that DM_USB is enabled, but it wasn't yet
available on omap3 and omap4 boards.
This patch converts the OMAP2430 MUSB glue to support DM_USB and
extracts the necessary information based on the device tree.
It's based on the ti-musb driver, but there are enough significant
differences in both the architecture and device tree entires between
am33xx and OMAP3/OMAP4, that I think it makes sense to continue to
keep the separate.
Per doc/driver-model/usb-info.txt, the USB gadget stuff hasn't
migrated to DM_USB yet, so this only supports USB Host for now.
Users wanting USB Gadgets will need to disable DM_USB and leave
it the old way for now.
Signed-off-by: Adam Ford <aford173@gmail.com>
A bunch of code was encapsulated in #ifdef's whether or not
it is building or for U-Boot. Since this code is always building
for U-Boot, this patch removes the dead code.
Signed-off-by: Adam Ford <aford173@gmail.com>
At present if TSC frequency is provided in the device tree, it takes
precedence over hardware calibration result. This swaps the order to
try hardware calibration first and uses device tree as last resort.
This can be helpful when a generic dts (eg: coreboot/efi payload) is
supposed to work on as many hardware as possible, including emulators
like QEMU where TSC hardware calibration sometimes fails.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Add u-boot,off-on-delay-us for fixed regulator.
Depends on board design, the gpio regulator sometimes
connects with a big capacitance. When need to off, then
on the regulator, if there is no enough delay,
the voltage does not drop to 0, so introduce this
property to handle such case.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This converts the following to Kconfig:
CONFIG_TWL4030_LED
CONFIG_TWL4030_INPUT
This also removes dead references to:
CONFIG_TWL4030_KEYPAD
Signed-off-by: Adam Ford <aford173@gmail.com>
This converts the following to Kconfig:
CONFIG_MII
CONFIG_DRIVER_TI_EMAC
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Replaced misspelled words "parition"/"paritioning" (missing 't') in two
Kconfig files by correct words "partition"/"partitioning"
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add a PHY driver for the R-Car Gen2 which allows configuring the mux
connected to the EHCI controllers and USBHS controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The code fails to copy the last PHY phandle argument, so it is
missing from the adjusted phandle args and the consumer cannot
use it to determine what the PHY should do.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Add support for fetching the clock frequency both using the legacy
method in case clock framework is disabled as well as via the clock
framework if it is enabled. This allows for migration to the clock
framework on platforms which supports it while not breaking legacy
platforms. That said, the legacy method must be removed eventually.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.
Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Add wrapper around the designware MAC driver to handle the SoCFPGA
specific configuration bits. On Arria10, this is configuration of
syscon phy_intf.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The recv variable in sandbox_tpm2_fill_buf() is a pointer on a pointer
of a char array. It means accessing *recv is the char array pointer
itself while **recv is the first character of that array. There is no
need for such indirection here, so simplify the code.
Simplifying things will make the last assignment right: "*recv = NULL"
is now correct. The issue has been found by the following Coverity
Scan report:
CID 183371: Incorrect expression (UNUSED_VALUE)
Assigning value "4UL" to "*recv" here, but that stored value is overwritten before it can be used.
232 *recv += sizeof(rc);
233
234 /* Add trailing \0 */
235 *recv = NULL;
While at simplifying things, use '\0' instead of NULL when adding an
empty char at the end of the buffer.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The second check on pcr_map in sandbox_tpm2_xfer() is wrong. It should
check for pcr_map not being empty. Instead, it is a pure copy/paste of
the first check which is redundant.
This has been found thanks to a Coverity Scan report:
CID 183370: Memory - illegal accesses (UNINIT)
Using uninitialized value "pcr_index".
put_unaligned_be32(tpm->pcr_extensions[pcr_index], recv);
This is because pcr_index is initialized only if the user input is
correct, ie. at least one valid bit is set in pcr_map.
Fix the second check and also initialize pcr_index to 0 (which is
harmless in case of error) to make Coverity Scan happy.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In case the slow clock is not properly configured, the UTMI clock
cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles".
In this case U-boot will loop indefinitely.
Added a timeout in this case, to start U-boot even if UTMI clock is
not enabled, so the user can use different media if needed, or investigate.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add a driver for the Xilinx LogiCORE DisplayPort IP core, which is a
pure DP transmitter core for Xiling FPGA (no display capabilities).
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The entries of Makefiles should be sorted, which is not the case in the
video driver Makefile.
Sort the entries alphabetically as far as this makes sense.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Add a uclass for AXI (Advanced eXtensible Interface) busses, and a
driver for the gdsys IHS AXI bus on IHS FPGAs.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is a fix made for the fsl_ifc_nand driver on linux kernel by
Pavel Machek and is applied to uboot. It is currently on applied on
linux-mtd.
https://patchwork.kernel.org/patch/9758117/
IFC always raises ECC errors on erased pages. It is only ignored when
the buffer is checked for all 0xFF by is_blank(). The problem is a
single bitflip will cause is_blank() and then mtd_read to fail. The fix
makes use of nand_check_erased_ecc_chunk() to check for empty pages
instead of is_blank(). This also makes sure that reads are made at ECC
page size granularity to get a proper bitflip count. If the number of
bitflips does not exceed the ECC strength, the page is considered empty
and the bitflips will be corrected when data is sent to the higher
layers (e.g. ubi).
Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz>
Cc: Pavel Machek <pavel@denx.de>
Cc: Scott Wood <oss@buserror.net>
Acked-by: Pavel Machek <pavel@denx.de>
[Kurt: Replaced dev_err by printf due to compiler warnings]
Tested-by: Kurt Kanzenbach <kurt@linutronix.de>
Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch save common LED property "default-state" value
in post bind of LED uclass.
The configuration for this default state is only performed when
led_default_state() is called;
It can be called in your board_init()
or it could added in init_sequence_r[] in future.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This reverts commit bc882f5d5c.
because this patch adds the probe of LED driver during the
binding phasis. It is not allowed in driver model because
the drivers (clock, pincontrol) needed by the LED driver can
be also probed before the binding of all the device and
it is a source of problems.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
sourcing of sub directiory kconfig files are not in
proper order, so keep them in ascending order.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
It might be useful for user to see some human-readable root cause
message in addition to "configuration failed" message, so that the issue
can be fixed quickly.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
In case of error in dfu_init_env_entities(), env_bkp will leak. Fix it
by providing single return path.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Commit 5d8fae7916 ("dfu: avoid memory leak") brings a regression which
described below. This patch is effectively reverting that commit, adding
corresponding comment to avoid such regressions in future.
In case of error in dfu_config_entities(), it frees "dfu" array, which
leads to "data abort" in dfu_free_entities(), which tries to free the
same array (and even tries to access it from linked list first). The
issue occurs e.g. when partition table on device does not match
$dfu_alt_info layout:
=> dfu 0 mmc 1
Couldn't find part #2 on mmc device #1
DFU entities configuration failed!
data abort
To fix this issue, do not free "dfu" array in dfu_config_entities(). It
will be freed later in dfu_free_entities().
Tested on BeagleBone Black (where this regression was originally found).
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
As well as in K_FW_LBA_READ_10 and K_FW_LBA_ERASE_10 take device's
block size from f_rkusb->desc->blksz instead of the fixed 512 bytes.
Keep original behaviour of retry probing assigned block device on
every host request to manage late SDCard plugs.
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
While downloading or uploading megabytes of data we had thousands of
printf in console like:
transfer 0x10000 bytes done
OR
Uploading 0x1000 bytes
This because transfers are chunked and there is no way on target
side to know the overall transfer size (to print one string per
overall transfer).
All these prints on serial console do slow down significantly the
transfer and does not offer a significant information to the
developer: rkdeveloptool and Rockchip original tool do use small
chunks read/writes on big transfers. This allows on workstation
to print percentage of transfer complete and as well offers to
developer the information about: transfer is running OK.
On error, either the percentage will stop or an error will be shown
on workstation console.
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
This command is part of the write partition sequence performed by
rkdeveloptool: one partition is first completely erased and
than wrote.
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch implement reading blocks form selected device with
LBA addressing.
Corresponding command on workstation is:
rkdeveloptool rl <start_blk> <blk_cnt> <file>
While we support reading more than one blocks per K_FW_LBA_READ_10
request, rkdeveloptool and original rockchip tool do perform
chunk reads limiting the maximum size per chunk far lower
than max int values.
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Chip Version is a string saved in BOOTROM address space Little Endian.
Ex for rk3288: 0x33323041 0x32303134 0x30383133 0x56323030
which brings: 320A20140813V200
Note that memory version do invert MSB/LSB so printing the char
buffer would show: A02341023180002V
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Two consecutive rockusb_tx_write without waiting for request complete
do results in transfer reset of first request and thus no or incomplete
data transfer. This because rockusb_tx_write do use just one USB request
to keep serialization.
So calls like:
rockusb_tx_write_str(emmc_id);
rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD);
was succeeding only when DEBUG was defined because the time spent
printing debug info was enough for transfer to complete.
This patch fixes the issue adding a simple request complete handler
called rockusb_tx_write_csw to be set as complete handler of in_req
when sending back simple payload + CSW replies to commands.
This new handler will always send CSW_GOOD replies because in case
of error the command callback itself must send back an error CSW as
unique reply to command.
This patch fixes execution of:
$ rkdeveloptool rfi
when DEBUG is not defined.
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
After the commit 6aae84769a ("gadget: f_thor: Fix memory leaks of
usb request and its buffer"), there is hang-up with ctrl-c in some
udc. It is because req of out_ep is freed before out_ep is disabled.
Fix hang-up with ctrl-c by disabling ep before free req of the ep.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
The ethernet name should be within the ETH_NAME_LEN, as this
is the buffer space allocated to ethernet name.
Otherwise, this causes buffer overflow.
Reported-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Most FSL PCIe controllers expects 333 MHz PCI reference clock.
This clock is derived from the CCB but in many cases the ref.
clock is not 333 MHz and a divisor needs to be configured.
This adds PEX_CCB_DIV #define which can be defined for each
type of CPU/platform.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add several PCI capability and extended capability ID registers
in the swap_case driver, so that we can add test case for
dm_pci_find_capability() and dm_pci_find_ext_capability().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This introduces two new APIs dm_pci_find_capability() and
dm_pci_find_ext_capability() to get PCI capability address and
PCI express extended capability address for a given PCI device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We have "struct sandbox_pci_priv" in pci_sandbox driver. To avoid
confusion, rename the emul's priv to "struct sandbox_pci_emul_priv".
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a U_BOOT_PCI_DEVICE() declaration to the swap_case driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present all emulated sandbox pci devices must be present in the
device tree in order to be used. The real world pci uclass driver
supports pci device driver matching, and we should add such support
on sandbox too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The correct driver data comes from the matching 'id' instead of
'find_id' in pci_find_and_bind_driver().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the newly added test cases for PCI configuration access, we get:
=> ut dm pci_busdev
Test: dm_test_pci_busdev: pci.c
test/dm/pci.c:49, dm_test_pci_busdev(): SANDBOX_PCI_VENDOR_ID == vendor:
Expected 4660, got 65535
Test: dm_test_pci_busdev: pci.c (flat tree)
test/dm/pci.c:49, dm_test_pci_busdev(): SANDBOX_PCI_VENDOR_ID == vendor:
Expected 4660, got 65535
Failures: 2
The bug only shows up when bus number is not equal to zero. This is
caused by the plain find_devfn parameter is passed to function call
pci_bus_find_devfn(), inside which find_devfn is compared to devfn
in the device's pplat structure. However pplat->devfn does not carry
the bus number. Fix this by passing find_devfn with bus number masked.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the newly added testing of more than one device, we get:
=> ut dm pci_swapcase
Test: dm_test_pci_swapcase: pci.c
test/dm/pci.c:88, dm_test_pci_swapcase(): "tHIS IS A tESt" = ptr:
Expected "tHIS IS A tESt", got "this is a test"
Test: dm_test_pci_swapcase: pci.c (flat tree)
test/dm/pci.c:88, dm_test_pci_swapcase(): "tHIS IS A tESt" = ptr:
Expected "tHIS IS A tESt", got "this is a test"
Failures: 2
The failure only happens on the 2nd swap_case device on the PCI bus.
The case passes on the 1st device.
It turns out the swap_case driver does not emulate bit#0 in BAR
registers as a read-only bit. This corrects the implementation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The flag to control whether to scan multi-function device during
enumeration should be cleared at the beginning of each iteration
if the device's function number equals to zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently only devfn is extracted in child_post_bind(). Now that
we have the live-tree version API to look up PCI vendor and device
id from the compatible string, let's extract and save them too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We don't have the live-tree version of fdtdec_get_pci_vendev().
This adds the API.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds the initial support of the Broadcom BCM6838 SoC familly,
only cpu, dram, uart and leds are supported.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This adds an option to force the size of the ram, and
avoid the detection of ram size.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The only platform left for the AU1x00 SoCs was the pb1x00 platform, an
apparent clone of the dbau1x00 platform. As pb1x00 had no listed
maintainer I am assuming that it is also orphaned. Remove this platform
and then remove the unused SoC support.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add support for reading label property from DT and set up bank name
based on that. If label property is not present full device node name is
used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
.set_value functions have no specified return value and gpio_uclass is
not working with it too. But this patch is returning 0 to be in sync
with others DM gpio drivers.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Reading registers for finding out output value is not working because
input value is read instead in case of tristate.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
There is no reason to do read/write for if/else separately.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Set a value before changing gpio direction. This will ensure that the
old value is not propagated when direction has changed but new value is
not written yet.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Call xilinx_gpio_get_bank_pin() before use.
Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Add the PCA9646 support, which is 2-wire bus switch and buffered 4-channel.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Add CONFIG_SPL_POWER_DOMAIN config entry.
Build drivers/power/domain if this config is selected.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch used platdata structure instead of priv for storing static
information read from DT.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit enables support for Exynos Designware MMC driver based on DM.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
By convention for DM_MMC the host->priv is used to store struct udevice
*dev pointer.
Unfortunately, the legacy Exynos DW MMC code uses this field to
store pointer to dwmci_exynos_priv_data struct
Hence, we do need to get data in other way - namely by using container_of
when host pointer is present.
In this way the sdr_timing data is properly accessed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit prevents memory leak when this function is used with DM_MMC
as the struct dwmci_exynos_priv_data is already allocated by DM.
It is necessary for NON DM aware devices to allocate this struct first.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The Assigned Clock parents and rates misses the fact that a "0" entry can
be passed to skip setting a parent or rate of an assigned clock as
described in the Linux clock bindings at [1].
This patch simply skips the clock reparenting if the DT parsing returns
-ENOENT and the clock rate setting if "0" is passed as clock rate.
[1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/clock/clock-bindings.txt#L135
Fixes: f4fcba5c5b "clk: implement clk_set_defaults()"
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As platform uses GPIOs for card detection, it's
simpler and more readable to use GPIO_ACTIVE_(LOW|HIGH)
in the gpio flags instead of using the cd-inverted
property.
Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add missing clk_free() call in case of failure
when enabling the clock.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Config flag CONFIG_BLK becomes mandatory, update arm_pl180_mmci
to support this config.
This driver is used by STM32Fx and by Vexpress platforms.
Only STM32Fx are DM ready. No DM code is isolated and will be
removed easily when wexpress will be converted to DM.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
1947c2d2a0 introduces cache line flushes for the bootcounter, but if
the start address is not aligned then the flush causes warnings of
the form:
CACHE: Misaligned operation at range [4030b7fc, 4030b83c]
Align both the start and end of the buffer (possibly crossing multiple
lines).
Fixes: 1947c2d2a0 ("bootcount: flush after storing the bootcounter")
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch adds support for STMicroelectronics STM32 ADC (analog to
digital converter). It's originally based on Linux kernel v4.18-rcs
drivers/iio/adc/stm32-adc*. It's composed of:
- core driver (UCLASS_SIMPLE_BUS) manages common resources (clk, regu).
- child drivers (UCLASS_ADC) declare each ADC, channels and handle
conversions.
This driver currently supports STM32H7 and STM32MP1 ADC.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
device_get_supply_regulator() only needs to be called once.
But each time there's call to adc_vxx_value() for instance, it calls
adc_vxx_platdata_update() -> device_get_supply_regulator().
So, move device_get_supply_regulator() to pre_probe() routine.
This also allows vdd_supply/vss_supply to be provided directly from
uc_pdata, e.g dt-binding variant like stm32-adc provide its own
'vref-supply'.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add clk_valid() to check for optional clocks are valid.
Call clk_valid() in test/dm/clk.c and add relevant test routine to
sandbox clk tests.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This matches the compatible string used by the Linux kernel. This will
allow u-boot to use the same device tree files.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: use armada instead of orion on .data]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Get the is_errata_50mhz_ac in .ofdata_to_platdata, and
reuse it in .set_mode this can eventually initialized
dt code at once and adding room to add platdata.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for SPANSION s25fl128l
Signed-off-by: Clément Laigle <c.laigle@catie.fr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: fixed , at the end of } ]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Drop the DM_I2C dependency, as the library only implements
the parsing of EDID data and doesn't depend on any driver
One user of this library, the i2c command, implements
support for legacy and DM I2C drivers
Tested on a Zynq board, whose I2C driver is not ported
yet to DM
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Return the error code of the set_features function only if
the error code is not ENOTSUPP. Otherwise, if this function
is not supported, it will return and fail to initialize the
NAND.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Convert the EINVAL error into ENOTSUPP when the GET/SET_FEATURES
is not supported.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Only H3 and H5 have 4 PHYS so restrict rst_mask only for them
by checking PHY id as 3 and update the proper bits.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
usb_clk_cfg is setting CTRL_PHYGATE bit value in probe
which is BIT 0 for sun4i, 6i and 8 for a83t but all
these were handling in phy ops init exit calls.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
On newer Allwinner SoC, there is a pair of EHCI/OHCI USB hosts
for OTG host mode. USB PHY passby must be configured for its
corresponding PHY. so we can call for PHY#0. on the other hand
in past usb-phy code the same thing can be restricted for
Lower SoC's, other than H3/H5/A64.
Now there is no need to restrict usb passby since the phy driver
is DT enabled, and the respective phy calls will trigger based
DT information initiated by the drivers.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Sometimes when a monitor without EDID information is plugged, the DE2
won't be probed (because of lack of timing information), but the HDMI
node is probed, thus a SimpleFB node with invalid information will be
populated.
Also detect whether DE2 is probed when creating SimpleFB node.
Fixes: be5b96f0e4 ("sunxi: setup simplefb for Allwinner DE2")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
the MMC2 come with the capability to do crypto by EMCE.
Add MMC support for H6. EMCE support is not added yet.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
CREG GPIO is a driver for weird soc-specific output ports, which are
controlled by some fields in memory mapped register.
Example:
31 9 7 5 0 < bit number
| | | | |
[ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register
^ ^
| |
write 0x2 == set output to "1" (activate)
write 0x3 == set output to "0" (deactivate)
As of tooday we only support fixed (hardcoded) bit per gpio line,
activate / deactivatei and shift values. Fix that by read them from
device tree to be able to use this driver for other boards.
Remove "hsdk" prefix from compatible string as this driver can be
used with different boards like HSDK, AXS101, AXS103, etc.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Highlights this time:
- Many small fixes to improve spec compatibility (found by SCT)
- Almost enough to run with sandbox target
- GetTime() improvements
- Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJbWHUwAAoJECszeR4D/txgKlUP/3Lu6pxScwzL7TsSD6OFZQ6M
qQq2FH89XOA6/3r04RXrJZoHwOKIH5uj7ea6FlitpS1sQ4UOCQhp/lJJuJennHHj
+veeuzI1sKTCX8Kd9ptrZDEF3G8lbF/zSyCFa1MOd1ONDVsTgSO9fOGmiqcC9FBF
UrUH7dzXlE2CWs/mv/UikCBI7rYF+NOFJNuwHVXfsW4PyQ/7uaNsa7Rl3mXYb/Lr
gjdcJkeHZAmFv/r84tGS9AFv+m0So9AGEYD7MeQDt02hSOuH9/nu4HgPmiwln3Fn
3sFA3+daMrlFNi6kFw10S0sjKz94nN+Arm6cIXlvGaoc/wnPM2wEcKOSiXhzVM8d
CoP/26N/ETRoI9P01C2WyTrKjo0O0aFwp3ubfmmbdcaKr/pyjAJgb3BnqXBfAr7T
OjsE086jtHzdyKYKXDIz8+ZxSo4VsiDjBzDK7LVA0L5KtqAFFa+OYjlgEMJnQCk3
YJfj+rhxfpjzFI7x5BAgq0q3XQRvAJS8QcUq+V2todQ3JkUlCIaVUNQLWAfNJN0q
ze/WR8l4nwj5YFo8XiEbFHpQi/1bkR6cSzyjlBKUqrtHUUEu32vWlzZpNi6HzPMq
cP7gehboFlcCSr8T2UMjBTE1LWI35eWNQQoiNRrS2UVcTH9h1vXMFV9PT+I82BBl
ivJ+YwF9nU1JdS8CG3n7
=ePTT
-----END PGP SIGNATURE-----
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-07-25
Highlights this time:
- Many small fixes to improve spec compatibility (found by SCT)
- Almost enough to run with sandbox target
- GetTime() improvements
- Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
Remove additional trailing whitespaces in prompt reported by kconfiglib:
warning: DM_PMIC_SANDBOX (defined at drivers/power/pmic/Kconfig:133) has
leading or trailing whitespace in its prompt
warning: <choice> (defined at dts/Kconfig:204) has leading or trailing
whitespace in its prompt
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Felix Brack <fb@ltec.ch>
The driver sets the weekday incorrectly when called by the
'date set' command.
Sunday is 1, Saturday is 7 unlike in U-Boot (see data sheet
https://www.nxp.com/docs/en/data-sheet/MC146818.pdf, table 3).
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
TPM_V1 was already compiled by default. Now that both can be compiled
at the same time, compiled them both by default.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
While there is probably no reason to do so in a real life situation, it
will allow to compile test both stacks with the same sandbox defconfig.
As we cannot define two 'tpm' commands at the same time, the command for
TPM v1 is still called 'tpm' and the one for TPM v2 'tpm2'. While this
is the exact command name that must be written into eg. test files, any
user already using the TPM v2 stack can continue to do so by just writing
'tpm' because as long as TPM v1 support is not compiled, U-Boot prompt
will search for the closest command named after 'tpm'.
The command set can also be changed at runtime (not supported yet, but
ready to be), but as one can compile only either one stack or the other,
there is still one spot in the code where conditionals are used: to
retrieve the v1 or v2 command set.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: In sandbox_tpm2_fill_buf() use NULL not \0 to ensure NULL
terminated string due to LLVM warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
The TPM_DRIVER_SELECTED symbol was used in one of the initial series
about TPMv2 but its use has been dropped, making these selects
useless, remove them.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When Sandbox and the TPM stack are both selected, compile Sandbox TPM
driver by default.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch updates the zynq gem driver to support livetree.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Now CPSW driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use PHY API phy_get_ofnode() helper to get PHY DT node.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use PHY API phy_get_ofnode() helper to get PHY DT node.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in
case of Ethernet PHYs which are linked to UCLASS_ETH device using
"phy-handle" DT property and when Ethernet PHY driver needs to read some
additional information from DT. In such cases following happens (in
general):
- network drivers
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
<-- phydev is connected to dev which is UCLASS_ETH device
if (priv->phy_of_handle > 0)
dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
<-- phydev->dev->node is overwritten by phy-handle DT node
- PHY driver in .config() callback
int node = dev_of_offset(dev);
<-- PHY driver uses overwritten dev->node
const void *fdt = gd->fdt_blob;
if (fdtdec_get_bool(fdt, node, "property"))
...
As result, UCLASS_ETH device can't be used any more for DT accessing.
This patch adds additional ofnode node field to struct phy_device which can
be set explicitly by network drivers and used by PHY drivers, so
overwriting can be avoided. Also add helper function phy_get_ofnode()
which will check and return phy_device->node or dev_ofnode(phydev->dev) for
backward compatibility with existing drivers.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
We want to be able to include some other system headers in phy.h but
that requires us to have included common.h in the top-level first.
Also, common.h includes config.h as the first thing it does, so don't
include it directly.
Series-to: u-boot
Series-cc: Grygorii Strashko <grygorii.strashko@ti.com>
Seried-cc: ti
Series-process-log: sort, uniq
Cover-letter:
Prepare for net: phy: prevent uclass_eth device "node" field overwriting
Prepare for [1] so that it doesn't break the build for a bunch of
boards. There are a number of reasons this series broke the build
but none of them depend on changes in the series, so fix up those
situations ahead of applying that series.
[1] https://patchwork.ozlabs.org/cover/940104/
END
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Switch to use more generic ofnode API instead of FDT API.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
supported (see note below Table 5 (4-Level Strap Pins)).
It further advises that if a board has this pin strapped in mode 1 and
mode 2, then bit[7] of Configuration Register 4 (address 0x0031) must
be cleared to 0. This is to ensure proper operation of PHY.
Since it is not possible to detect in software if RX_DV/RX_CTRL pin is
incorrectly strapped, add a device-tree property to advertise this and
allow corrective action in software.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Add driver model support to the mvgbe driver. As a temporary measure
both DM and non-DM uses are supported. Once all the users have been
converted the non-DM support can be dropped.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Extract some function bodies to helper functions that can be reused in
the DM/non-DM implementations.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Ask the OS for each of its interfaces and for each one, bind a U-Boot
device and then probe it. This will allocate the priv data structure
that is then populated.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We don't necessarily know how many MAC addresses we'll need, so implement
a ROM read so we always have something valid.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With systemd stable interface names, eth0 will almost never exist.
Instead of using that name in the sandbox.dts, use an index.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Instead of doing a simple string compare against "lo", look for the flag
that indicates a localhost interface.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In raw mode, handle ctrl-c as normal. This allows normal ctrl-c behavior
such as aborting a command that is timing out without completely
terminating the sandbox executable.
In [1], Simon disabled this. His reason for it was that it interferes
with piping test scripts. Piping should be done in cooked mode, so this
change should still not interfere.
[1] commit 8969ea3e9f ("sandbox: Disable Ctrl-C")
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Pass an empty buffer instead of NULL if the hwconfig environment
variable isn't set.
Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Make the code structure more general so that more socs can be
added easily and also remove speed limitation restriction.
Add the ls1012a sata support as well.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
(with and without CONFIG_OF_LIVE on zynqmp zcu102)
Reviewed-by: York Sun <york.sun@nxp.com>
The EFI subsystem accesses the real time clock and is enabled by default.
So we should drop any CONFIG_CMD_DATE dependency from the real time clock
drivers.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
The NAND framework makes sure to pass in the buffer with at least
chip->buf_align alignment. Currently, the Denali NAND driver only
requests 16 byte alignment. This causes unaligned cache operations
for the DMA transfer.
[Error Example]
=> nand read 81000010 0 1000
NAND read: device 0 offset 0x0, size 0x1000
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
4096 bytes read: OK
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
rtc_to_tm() and rtc_mktime() are required for some RTC drivers, at least
PL031. Without this patch, we also need to enable CONFIG_CMD_DATE even if
we don't want or need this command.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Assigning a parameter which is not used afterwards has not effect.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the missing gpio phy reset binding to the gpio and
reset time configuration
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This code is useful for testing the existance of devices that
do not have card detect capabilities. This breaks out the core
functionality and leaves the actual init logic and error reporting
in mmc_start_init().
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefano Babic <sbabic@denx.de>
If the bootcounter address is in a cached memory,
a flush of dcache must occur after updateing the bootcounter.
Issue found on i.MX6 where bootcounter is put into the internal
(cached) IRAM.
Signed-off-by: Stefano Babic <sbabic@denx.de>
rk3066 and rk3188 has two I2C controller implementations.
Current I2C driver wan't work with legacy implementation.
Switching between controllers is performed using a bit inside
GFR_SOC_CON1 register. The bit setting is performed by pinctrl
driver. The patch ask pinctrl to do settings.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fix warnings by including the rk3228 variant in the compatible-list]:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
HSE and LSE bypass shall support both analog and digital signals.
This patch add a way to select digital bypas case in the device tree
and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register
during clock tree initialization.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add ADC clock gating, that may be used by STM32 ADC.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch add clk_enable/clk_disable/clk_get_rate support for
- DSI_PX
- LTDC_PX
- DSI_K (only get rate)
These clocks are needed for LTDC and DSI drivers with latest device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
the function compute the VCO PLL freq, used in
- stm32mp1_read_pll_freq()
- pll_set_rate()
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
# Conflicts:
# drivers/clk/clk_stm32mp1.c
This patch define RCC_PLLNCFGR2_SHIFT to reuse it in
the pll function for set rate.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Following next kernel rcc bindings, we must use a MFD
RCC driver which is able to bind both clock and reset
drivers.
We can reuse and adapt RCC MFD driver already available
for MCU SoCs (F4/F7/H7).
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Use new API syscon_node_to_regmap in sysreset_syscon driver
for compatible "syscon-reboot"; that's avoid the need of explicit
syscon binding for "regmap" handle.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
For qemu-x86 the date command produces wrong days of the week:
Date: 2018-07-06 (Saturday) Time: 18:02:03
Date: 2018-07-07 (unknown day) Time: 21:02:06
According to a comment in the Linux driver the mc146818 only updates the
day of the week if the register value is non-zero.
Sunday is 1, saturday is 7 unlike in U-Boot (see data sheet
https://www.nxp.com/docs/en/data-sheet/MC146818.pdf).
So let's use our library function to determine the day of the week.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Our implementation of rtc_to_tm() cannot handle dates of more than
0x7fffffff seconds after 1970-01-01.
Adopt the Linux kernel implementation.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The Shared Memory Manager driver implements an interface for allocating
and accessing items in the memory area shared among all of the
processors in a Qualcomm platform.
Adapted from the Linux driver (4.17)
Changes from the original Linux driver:
* Removed HW spinlock mechanism, which is irrelevant
in U-boot particualar use case, which is just reading from the smem.
* Adapted from Linux driver model to U-Boot's.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is a uclass for Shared memory manager drivers.
A Shared Memory Manager driver implements an interface for allocating
and accessing items in the memory area shared among all of the
processors.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
QEMU provides an emulated ARM AMBA PrimeCell PL031 RTC.
The patch sets the base address in the board include file according to the
definition in hw/arm/virt.c of the QEMU source. It defines the Kconfig
option for the existing driver, and enables the RTC driver in
qemu_arm64_defconfig and qemu_arm_defconfig as well as the date command.
We need an RTC to provide the GetTime() runtime service in the UEFI
subsystem.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Tested-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
This patch adds a delay when regulators are disabled.
This delay is set to 5 ms to cover all use cases.
The worst use case actually seen is during a SD card power cycle.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
In case of phy are provided from a PHY provider nodes as following:
usbphyc: usb-phy@5a006000 {
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc_clk USBPHY_K>;
resets = <&rcc_rst USBPHY_R>;
#address-cells = <1>;
#size-cells = <0>;
usbphyc_port0: usb-phy@0 {
reg = <0>;
phy-supply = <&vdd_usb>;
vdda1v1-supply = <®11>;
vdda1v8-supply = <®18>
#phy-cells = <0>;
};
usbphyc_port1: usb-phy@1 {
reg = <1>;
phy-supply = <&vdd_usb>;
vdda1v1-supply = <®11>;
vdda1v8-supply = <®18>
#phy-cells = <1>;
};
};
and PHY are called as following:
usbh_ehci: usbh-ehci@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&rcc_clk USBH>;
resets = <&rcc_rst USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_NONE>;
companion = <&usbh_ohci>;
phys = <&usbphyc_port0>;
phy-names = "usb";
status = "okay";
};
generic_phy_get_by_index() must be updated to first look for
PHY phandle as previously and in case of error looks for PHY
provider by finding the parent's current node which is the PHY
provider.
args (ofnode_phandle_args struct) must also be updated by inserting
the phy index into the PHY provider as args[0].
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Correctly manage the SDMMC reset and card cycle power
to fully handle the power cycle added in the MMC uclass
and avoid issue with level-shifter with some uSDCARD.
3 states managed in driver:
1/ reset: SDMMC disable, signal HiZ
2/ power-cycle: SDMMC disable, signals drive to 0
3/ power-on: SDMMC enabled
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Disable the use of function zynq_loadfs when compiling
the driver for the SPL, as the following filesystem
functions are not found by the linker:
- fs_set_blk_dev
- fs_read
- fs_set_blk_dev
- fs_read
- fs_read
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Watchdog can be started before probe and u-boot should just take control
over it. That's why do not stop watchdog in probe to cover cases where
watchdog can expire before probe and start.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
IP itself has no reg/no bit which can be used for this functionality.
Add this note to the driver to make sure that none will be asking for
that. Current method is to setup 1s timeout and hang() which is done via
wdt_expire_now().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Converting GPIO to DM requires to do changes in reset subsystem
that's why support for Microblaze soft reset via sysreset and GPIO
sysreset support was added.
These two patches enables enabling GPIO DM.
Microblaze soft reset is bind at last reset method.
GPIO reset is handled via sysreset with adding this fragment to DT.
gpio-restart {
compatible = "gpio-restart";
gpios = <&reset_gpio 0 0 0>;
/* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */
};
hard-reset-gpio property is not documented and also handled.
Conversion is required.
Unfortunately do_reset is required for SPL that's why use only soft
microblaze reset for now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Xilinx Axi wdt driver conversion to driver model & Kconfig update
for the same.
Signed-off-by: Shreenidhi Shedi <yesshedi@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is enabling GPIO_DM support to have an option to use this
driver together with zynq gpio driver.
!DM part is kept there till Microblaze is cleanup which will be done
hopefully soon.
Just a note:
There is no reason to initialize uc-priv->name because it is completely
unused.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Microblaze is storing reset vector at address 0x0.
It means soft reset can be done by just jumping to this address.
This code was in platform code but sysreset interface is providing
enough capabilities to have more options how to reset the system. It can
go from gpio reset through watchdog reset till soft reset.
The driver has not compatible string because this is cpu specific and DM
core is not able to detect compatible string in DT root that's why this
driver will be instantiated from platform code by calling
device_bind_driver(gd->dm_root, "mb_soft_reset", "reset_soft",
NULL);
It should be bind as the last reset method to ensure that hw reset is
called before this.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Linux kernel has binding for gpio-restart node.
This patch is adding basic support without supporting any optional
properties.
This driver was tested on Microblaze system where gpio is connected to
SoC reset logic.
Output value is handled via gpios cells values.
In gpio_reboot_request() set_value is writing 1 because
dm_gpio_set_value() is capable to changing it when it is ACTIVE_LOW.
...
if (desc->flags & GPIOD_ACTIVE_LOW)
value = !value;
...
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There should be proper bank name setup to distinguish between different
gpio drivers. Use dev->name for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove bogus zynq_gpio_getplat_data() and read driver data directly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Relocate gpio ops as was done by:
"dm: Add support for all targets which requires MANUAL_RELOC"
(sha1: 484fdf5ba0)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Relocate sysreset ops as was done by:
"dm: Add support for all targets which requires MANUAL_RELOC"
(sha1: 484fdf5ba0)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Relocate watchdog ops as was done by:
"dm: Add support for all targets which requires MANUAL_RELOC"
(sha1: 484fdf5ba0)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
uclass name is used by dev_read_alias_seq which return seq number when
aliases are used.
Code fragment:
168 int dev_read_alias_seq(struct udevice *dev, int *devnump)
169 {
170 ofnode node = dev_ofnode(dev);
171 const char *uc_name = dev->uclass->uc_drv->name;
172 int ret;
173
174 if (ofnode_is_np(node)) {
175 ret = of_alias_get_id(ofnode_to_np(node), uc_name);
Also this patch enables DM_UC_FLAG_SEQ_ALIAS to be in sync with Linux
which is also using watchdog name for watchdog aliases.
drivers/watchdog/watchdog_core.c:215:
ret = of_alias_get_id(wdd->parent->of_node, "watchdog");
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch basically adds two new commands for loadig secure
images.
1. zynq rsa adds support to load secure image which can be both
authenticated or encrypted or both authenticated and encrypted
image in xilinx bootimage(BOOT.bin) format.
2. zynq aes command adds support to decrypt and load encrypted
image back to DDR as per destination address. The image has
to be encrypted using xilinx bootgen tool and to get only the
encrypted image from tool use -split option while invoking
bootgen.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Explanation from Simon Glass
"Private data is created when the device is probed and freed when the
device is removed.
Platform data is created when the device is bound, and survives
probe/remove cycles.
Strictly speaking, platform data should be used to hold the decoded
device tree properties. Private data should be used for run-time
things the device needs to keep track of."
Based on description the driver needs to be switch to use platdata
instead of priv.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch fixed the same if/else part error by adding the required
source select on the basis of is_pre_src check.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit adds paired dev info for winbond w25q16jv
(tested w25q16jvssiq with a i.mx6 board)
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add support for the Macronix mx25l1633e nor flash. (Tested on a imx6 board)
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board)
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit adds the following flashes to the id-table
- W25Q16JV
- W25Q32JV
- W25Q64JV
- W25Q128JV
- W25Q256JV
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch adds qspi driver support for ZynqMP SoC. This
driver is responsible for communicating with qspi flash
devices.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
[jagan: removed GQSPI_MIO_NUM_ macros]
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch is for the startup block issue in the spi controller.
SPI clock is passing through STARTUP block to FLASH. STARTUP block
don't provide clock as soon as QSPI provides command. So, first
command fails.
This patch added support to read JEDEC id in xilinx_spi_xfer ().
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch modify xilinx_spi_xfer() function and add rxfifo() and
txfifo() functions to add the modularity so that these functions
can be used by other functions within the same file.
This patch also added support to read fifo_size from dts.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch added support to read register base address from DTS file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add support for the GMAC found in the Allwinner R40/V40 SoC.
The R40 GMAC interface is not controlled by the syscon register but
has a separate configuration register in the CCU.
The clock gate and reset bits are in a different register compared
to the other SoCs supported by this driver.
The driver uses the -gmac suffix for the R40 because the R40 also
has a different 100 MBit MAC (EMAC).
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Use driver data->variant information to select device specific
pin mux and phy clock settings.
Suggested by Jagan Teki
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
If the variant is not set and therefore NULL, do not attempt to print
the variant.
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Commit dd27918c22 ("dm: mmc: sunxi: Add support for driver model")
only added the allwinner,sun5i-a13-mmc compatible string for this
driver. The DM initialisation code here also works with (at least) A10
and A20, so add the appropriate compatible strings as per Linux 4.17's
driver.
Tested on A10 Cubieboard and A20 pcDuino3 Nano with CONFIG_DM_MMC.
(A20 worked already, because sun7i-a20.dtsi specifies both the A13 and
A20 strings.)
Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
When doing "i2c dev 4; i2c probe" with ENET daughter card connected
on iMX8QXP MEK board, we met a i2c bus busy issue, that the BBF of
lpi2c always show busy, but the master is idle, and stop is detected
(SDF set).
This patch addes a handling to re-init the lpi2c master for this
case. Then the issue can be worked around.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
In xfer function, both bus_i2c_read and bus_i2c_write will
send a STOP command. This causes a problem when reading register
data from i2c device.
Generally two operations comprise the register data reading:
1. Write the register address to i2c device.
START | chip_addr | W | ACK | register_addr | ACK |
2. Read the Data from i2c device.
START | chip_addr | R | ACK | DATA | NACK | STOP
The STOP command should happen at the end of the transfer, otherwise
we will always get data from register address 0
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
For LPI2C IP, NACK is detected by the rising edge of the ninth clock.
In current uboot driver, once NACK is detected, it will reset and then
disable LPI2C master. As a result, we can never see the falling edge
of the ninth clock.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory
to u-boot include directory as a common header file.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case. This scrubbing implementation turns the caches on temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns them
off again. This provides satisfactory performance.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
This function was never used in SPL and the default implementation of
dram_bank_mmu_setup() does the same thing. The only difference is the
part which configures OCRAM as cachable, which doesn't really work as
it covers more than the OCRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Use "%p" to print cmdbuf.
Compilation warning as below:
CC spl/drivers/spi/cadence_qspi_apb.o
LD spl/lib/built-in.o
drivers/spi/cadence_qspi_apb.c: In function ‘cadence_qspi_apb_indirect_write_setup’:
drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
cmdlen, (unsigned int)cmdbuf);
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Use "%zu" for size_t data type.
Compilation warning as below:
In file included from include/linux/bug.h:7:0,
from include/common.h:26,
from drivers/spi/cadence_qspi.c:8:
drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’:
drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’ [-Wformat=]
debug("%s: len=%d [bytes]\n", __func__, data_bytes);
^
include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’
#define pr_fmt(fmt) fmt
^~~
include/log.h:142:2: note: in expansion of macro ‘debug_cond’
debug_cond(_DEBUG, fmt, ##args)
^~~~~~~~~~
drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’
debug("%s: len=%d [bytes]\n", __func__, data_bytes);
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
In the device tree, the address for the led is located
in the parent node (for exemple leds), not in the led node
(for exemple led@0).
The commit "led: bcm6328: convert to use live dt"
(sha1: 8994551760)
change this behaviour and read the address in the led node.
We fix this by reading the base address for led
in the parent node.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
In the device tree, the address for cpu is located in
the node "cpus", not in the cpu node (for exemple cpu@0).
So when probing cpu, the cpu address must be read in the
cpu parent.
The commit "cpu: bmips: convert to use live dt"
(sha1: c444afbbef)
change this behaviour and read the address in the
cpu node when probing cpu.
We fix this by reading the address in the cpu parent.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
The omap_gpio driver has a TODO that says when every board is converted
to DM and DT, the omap_gpio_bind can stop using calloc and switch
to auto-alloc.
This patch converts this driver to auto-calloc when DT is enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
Add support for loading U-Boot on the Broadcom 7445 SoC. This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Add code to reset all reset signals as in Ethernet DT node. A reset
property is an optional feature, so only print out a warning and do not
fail if a reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add code to reset all reset signals as in serial DT node. A reset
property is an optional feature, so do not fail if a reset property is
not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add code to reset all reset signals as in mmc DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET, so can use
CONFIG_IS_ENABLED(DM_RESET) checking in reset.h later.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit adds Actions Semi OWL family UART support. This driver
relies on baudrate configured by primary bootloaders.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a way to decode a memory region, including the memory type (sram or
sdram) and its start address and size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new device_bind_ofnode() function which can bind a device given its
ofnode. This allows binding devices more easily with livetree nodes.
Signed-off-by: Simon Glass <sjg@chromium.org>
We have a 32-bit version of this function. Add a 64-bit version as well so
we can easily read 64-bit ints from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
On the A64 the clock for the first USB controller is actually the parent
of the clock for the second controller, so turning them off in that order
makes the system hang.
Fix this by only turning off *both* clocks when the *last* OHCI controller
is brought down. This covers the case when only one controller is used.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional usb from u-boot.
Signed-off-by: Oleksandr Tymoshenko <gonzo@FreeBSD.org>
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
Make the initialization sequence consistent with the Linux kernel
driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
This fixes sporadic timeout on initial packet Tx (usually ARP), with an
error message like:
timeout: packet not sent
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
phyread can timeout and val will contain random value. Initialize it to
zero not to report random value in case of error.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional video in u-boot.
Signed-off-by: Oleksandr Tymoshenko <gonzo@FreeBSD.org>
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
With the introduction of early timer support in the TSC driver,
the capability of getting clock rate from device tree was lost
unfortunately. Now we bring such functionality back, but with a
limitation that when TSC is used as early timer, specifying clock
rate from device tree does not work.
This fixes random boot failures seen on QEMU targets: printing "TSC
frequency is ZERO" and reset forever.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.
unfortunately these are fixed due to lack of separate
clock, reset drivers.
Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.
This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.
We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) << 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be
the first member in private data struct.
Fixes 831cc98b1 ("usb: sunxi: Simplify ccm reg base code")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tom Rini <trini@konsulko.com>
The claim/release bus function must not reset the whole SPI core because
settings regarding wordlen, clock-frequency and so on made by
set_wordlen, set_mode, set_speed get lost with this action. Resulting in
a non-functional SPI.
Without DM the failure didn't came up since after the spi_reset within
claim bus all the setup (wordlen, mode, ...) was called, in DM they are
called by the spi uclass.
We change now the things as following for having a working SPI instance
in DM:
- move the spi_reset(...) to the probe call in DM for having a known
hardware state after probe. Without DM we don't have a probe call, so we
issue the reset as before during the claim_bus call.
- in release bus we just reset the modulctrl to the reset-value (spi-
slave)
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This bug is the combination of dwc2 USB controller and lan78xx
USB ethernet controller, which is the combination in use on
the Raspberry Pi Model 3 B+.
When the host attempts to receive a packet, but a packet has not
arrived, the lan78xx controller responds by setting BIR
(Bulk-In Empty Response) to NAK. Unfortunately, this hangs
the USB controller and requires the USB controller to
be reset.
The fix proposed is to have the lan78xx controller respond
by setting BIR to ZLP.
Signed-off-by: Andrew Thomas <andrew.thomas@oracle.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
For now, the existing SPL MXS NAND driver only supports to identify
ONFi-compliant NAND chips. In order to allow identifying
non-ONFi-compliant chips add `mxs_flash_full_ident()` which uses the
`nand_get_flash_type()` functionality from `nand_base.c` to lookup
for supported NAND chips in the chip ID list.
For compatibility reason the full identification support is only
available if the config option `CONFIG_SPL_NAND_IDENT` is enabled.
The lookup was tested on a custom i.MX6ULL board with a Toshiba
TC58NVG1S3HTAI0 NAND chip.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
The existing `mxs_flash_ident()` is limited to identify ONFi compliant
NAND chips only. In order to support non-ONFi NAND chips refactor the
function and rename it to `mxs_flash_onfi_ident()`.
A follow-up patch will add `mxs_flash_full_ident()` which allows to use
the chip ID list to lookup for supported NAND flashs.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Add the config option `CONFIG_SPL_NAND_IDENT` for using the NAND chip ID list
to identify the NAND flash in SPL.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
`nand_get_flash_type()` allows identification of supported NAND flashs.
The function is useful in SPL (like mxs_nand_spl.c) to lookup for a NAND
flash (which does not support ONFi) instead of using nand_simple.c and
hard-coding all required NAND parameters.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
The PFUZE3000 uses registers addresses up to 0xff.
The DM pfuze100 driver supports both pfuze100 and pfuze3000. Allow it
to use the device type to return the correct number of registers.
Also rename the too generic PMIC_NUM_OF_REGS enumeration value for
pfuze3000 to match the other "PFUZE3000_" prefixed enumerations and the
pfuze100 enumeration value PFUZE100_NUM_OF_REGS.
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
This aligns behavior with the mainline driver, such that:
- If fsl,use-minimal-ecc is requested it will use data from
data sheet/ONFI. If this is not available the driver will fail.
- If nand-ecc-strength/nand-ecc-step-size are specified those
value will be used.
- By default maximum possible ECC strength is used
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Support driver data from device tree. Also support fsl,use-minimal-ecc
similar to Linux' GPMI NAND driver.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
In preparation for device tree support separate board init
from controller init similar to other raw NAND drivers.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
This function initializes DMA descriptors so mxs_nand_init_dma is
more precise. It also frees up the rather generic name mxs_nand_init.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Move GPMI and BCH register structs to the driver struct mxs_nand_info
in prepartion for device tree support.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Add support for minimum ECC strength supported by the NAND chip.
This aligns with the behavior when using the fsl,use-minimum-ecc
device tree property in Linux.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Report correct ECC parameters back to the stack. Do not report
bytes as we have it not immeaditly available and the Linux version
also does not report it. It seems to have no aversive effect.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Calculate BCH geometry at start and store the information in
a structure. This avoids recalculation on every page access
and allows to calculate ECC relevant information in one place.
This patch does not change ECC layout or driver behavior in
any way.
The patch aligns the driver somewhat with the Linux GPMI NAND
driver which drives the same IP.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Add config option which allows to enable on flash bad block table
support. This has the same effect as when using the device tree
property "nand-on-flash-bbt" in Linux.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Instead of completing initialization via scan_bbt callback use
NAND self init to initialize the GPMI (MXS) NAND controller.
Suggested-by: Scott Wood <oss@buserror.net>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
In preparation to convert the driver to use NAND self init
provide a new minimal init for SPL builds. As a side effect
this also reduces size of SPL by about 4KiB.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
commit 8480792287
("spi: omap3: Skip set_mode, set_speed from claim") did break SPI
support on my AM335x board.
The named commit:
- ignored the responsible arguments (speed, mode)
The set speed/mode function must use the supplied function arguments to
work properly. With this commit we take those arguments and transfer
them to the priv-data.
- used wrong udevice pointer for getting priv data
the udevice-pointer within function argument is already the spi-bus
device, so it is wrong looking here for some parent (ocp-bus in this
case) and getting priv-pointer from there.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Otherwise the frequency is zero and the clock divider cannot be setup by
'omap3_spi_set_speed' function.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
CS GPIO activation low/high is determinated by the device tree
so we don't need to take in accoung in cs_activate and cs_deactivate
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch replaced "return 0" with "return status" to fix the
incorrect return value error reported by the coverity.
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
In Linux, the clock rate of the UART is given by the clock driver.
If you try to follow that in U-Boot, you would end up with adding
more u-boot,dm-pre-reloc properties, and also the clock driver would
be too big for SPL, which is used for UniPhier ARMv7 platform.
The current solution is to add 'clock-frequency' property to the
UART nodes, but it does not exist in the DT files in Linux. I do
not want to let DT diverge for U-Boot.
Check the SoC compatible and set the clock rate according to it.
This will be helpful to sync DT between Linux and U-Boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use the clk framework to initialize clocks from drivers that need them
instead of having hardcoded frequencies and initializations from board
code.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The SARADC driver was merged after the following commit :
commit d35812368a ("regmap: change regmap_init_mem() to take ofnode instead udevice")
Thus breaking build, this patch fixes the regmap_init_mem accordingly.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
At present the code overruns the bar[] array. Fix this.
At the same time, drop the leading / from the "/spl" path so that we can
run U-Boot SPL with:
spl/u-boot-spl
rather than requiring:
/path/to/spl/u-boot-spl
Reported-by: Coverity (CID: 131199)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Move the strdup() call so that it is only done when we know we will bind
the device.
Reported-by: Coverity (CID: 131216)
Signed-off-by: Simon Glass <sjg@chromium.org>
The recent DTs have the PHY reset GPIO in the PHY node rather than
the ethernet MAC node, support extracting the PHY reset GPIO info
from both the PHY node and ethernet MAC node.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The recent DTs have the PHY reset GPIO in the PHY node rather than
the ethernet MAC node, support extracting the PHY reset GPIO info
from both the PHY node and ethernet MAC node.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The RAVB only supports 100Full and 1000Full operation, it does not support
10Full or any Half-duplex modes. The PHY could still advertise those features
though, so filter out the PHY features accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Do not stop the clock in the start callback in case of failure, keep
them running to also keep the PHY running. The failure could be ie.
PHY failing to negotiate link and if the clock get shut down, another
attempt at bringing the link up would fail. The clock right now are
started in probe function and stopped in remove function, which is
the correct behavior.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The sh_pfc_{read,write}() must operate on the register address directly
rather than on an offset, fix this to prevent illegal access.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
There are multiple GPIO banks with up to 32 pins / bank. When
using 'gpio status -a' to read the pins, this patch displays
both GPIO<bank>_<index> similar to how the device trees
display in addition to displaying gpio_#
Signed-off-by: Adam Ford <aford173@gmail.com>
When enabling BLOCK_CACHE on devices with limited RAM during SPL,
some devices may not boot. This creates an option to enable
block caching in SPL by defaults off. It is dependent on SPL_BLK
Fixes: 46960ad6d0 ("block: Have BLOCK_CACHE default to y in some cases")
Signed-off-by: Adam Ford <aford173@gmail.com>
The naming with "UART" is obviously wrong, we fix this here.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This adds a DM video driver for U-Boot as the EFI payload. The driver
makes use of all necessary information from the passed EFI GOP info
to create a linear framebuffer device, as if it were initialized by
U-Boot itself.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
This function is used only inside this driver that's why should be
static.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This issue was found when OF_LIVE was enabled that there are scrambled
chars on the console like this:
Chip ID: zu3eg
Watchdog: Started��j� sdhci@ff160000: 0, sdhci@ff170000: 1
In: serial@ff010000
I found a solution for this problem exactly the same as I found later in
serial_msm fixed by:
"serial: serial_msm: initialize uart only before relocation"
(sha1: 7e5ad796bc)
What it is happening is that output TX fifo still contains chars to be
sent and _uart_zynq_serial_init() resets TX fifo even in the middle of
transfer.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change logic and put char to fifo till there is a space in output fifo.
Origin logic was that output fifo needs to be empty. It means only one
char was in output queue.
Also remove unused ZYNQ_UART_SR_TXEMPTY macro.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Coding style is checking to use BIT macros instead of shifts.
The patch is also fixing the rest of macros which should be BITs instead
of hex numbers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use u32 instead of int for max_bank, bank_min and bank_max. These values
can't be negative that's why no reason to use signed type.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Code around tuning_loop_counter variable expects to go below zero.
That's why this variable can't use unsigned type.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixes the mmc tuning command failures
when tuning pattern data needs to read back for
comparision against the expected bit pattern.
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This function is required for adding bootstage support.
Also enable it directly for ZynqMP R5 configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
struct sunxi_ccm_reg doesn't have ahb_reset0_cfg on sun4i and sun5i,
thus compilation fails with:
drivers/usb/host/ohci-sunxi.c:96:26: error: 'struct sunxi_ccm_reg' has
no member named 'ahb_reset0_cfg'
Access this reg using its offset to fix this issue.
Fixes commit 1ed9c1118 ("usb: sunxi: ehci: get rid of ifdefs")
and commit 56830cee3 ("usb: sunxi: ohci: get rid of ifdefs")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Functions can return NULL in case of error that's why checking return
value is needed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In case of phyread()/phy_setup_op() timeout code is working with
uninitialized phyreg variable. Initialize this variable to make sure
that code it not working with random value.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
wait_for_bit_le32 returns negative value on failure. Fix phy...() to
handle these failures properly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Combine repeated code from smi_reg_read/smi_reg_write into a common
function smi_wait_ready.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block,
the DMA reset never succeeds when a MII PHY is used (no problem with a
GMII PHY). The designware_eth_init() function sets the
DMAMAC_SRST bit in the DMA_BUS_MODE register, and then
polls until this bit clears. When a MII PHY is used, with the current
driver, this bit never clears and the driver therefore doesn't work.
The reason is that the PS bit of the GMAC_CONTROL register should be
correctly configured for the DMA reset to work. When the PS bit is 0,
it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells
the MAC we have a MII PHY.
Doing a DMA reset clears all registers, so the PS bit is cleared as
well. This makes the DMA reset work fine with a GMII PHY. However,
with MII PHY, the PS bit should be set.
We have identified this issue thanks to two SPEAr600 platform:
- One equipped with a GMII PHY, with which the existing driver was
working fine.
- One equipped with a MII PHY, where the current driver fails because
the DMA reset times out.
Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When connecting to from a CPU direct to a 88e6097 typically RGMII is
used. In order for traffic to actually pass we need to force the link up
so the CPU MAC on the other end will see the link.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This makes sure the DMA buffers are properly aligned for the
hardware.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add driver for Socionext AVE ethernet controller that includes MAC and
MDIO bus supporting RGMII/RMII modes.
The driver behaves the ethernet driver model (DM_ETH) with devicetree.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
VCAP tables must be initialized even if no advanced classification
is used. If no initialization is performed, then ECC error will
be observed by the user when the first packet enters the l2switch.
The error is marked in MPIC_EISR0 -bit 29 which means - Internal RAM
multi-bit ECC error.
This patch fixes the aforementioned ECC error by performing the
initialization of VCAP tables.
Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If you send a final packet just before stopping the interface (e.g. a final
ACK as part of the UDP fastboot protocol), then that packet isn't reliably
delivered onto the wire.
Reap packets prior to stopping the interface to ensure any which are
in-flight make it out. Also remove buffer and len from the call to
cpdma_process() as we weren't using them on their return.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add support for Cortina CS4223 10G PHY
- As per the CS4223 specs, an EEPROM module is
connected to the PHY. At startup the PHY reads
the firmware line and tries to load the firmware
into the internal memory.
- This driver reads the EEPROM status
and checks if firmware has been loaded
Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Put the enetaddr data in the same order as it was before the change in
commit ace1520cb5 ("net: sunxi-emac: Write HW address via function")
Reported-by: Udo Maslo <u.maslo@web.de>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Bus translations should be applied when reading the address of the sgmii
phy registers from the DT. Use ofnode_get_addr_index instead of the
plain ofnode_read_u32_default to fix this.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
clock when OHCI1 is in use.
Fixes commit dd3228170a ("usb: sunxi: Switch to use generic-phy")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
If U-Boot gets used as coreboot payload all pci resources got
assigned by coreboot. If a dts without any pci ranges gets used
the dm is not able to access pci device memory. To get things
working make use of a 1:1 mapping for bus <-> phy addresses.
This change makes it possible to get the e1000 U-Boot driver
working on a sandybridge device where U-Boot is used as coreboot
payload.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If we use U-Boot as coreboot payload with a generic dts without
any ranges specified we fail in pci pre_probe and our pci bus
is not usable.
So convert decode_regions(..) into a void function and do the simple
error handling there.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message and checkpatch warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This fixes the following compiler warning:
"warning: cast from pointer to integer of different size
[-Wpointer-to-int-cast]"
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.
This fixes booting on a skylake based system.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed wrong indention of labels]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Added the following:
1. defconfig for LS1012AFRWY Secure boot
2. PfE Validation support
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add WARN_ONCE definition to allow single time notification
of warnings to the user.
Taken from Linux kernel (4.17) with slight changes
(Removed __section(.data.once))
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
[trini: Drop the musb and dwc3 compat versions]
Signed-off-by: Tom Rini <trini@konsulko.com>
When dealing with filesystems that come from block devices we can get a
noticeable performance gain in some use cases from having the block
cache enabled. The code paths are valid in other cases when we have BLK
set and may provide wins in raw reads in some use cases, so have this be
default when BLK is enabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
Equivalent code that disables the hidden i2c0 slave already exists in
the Turris Omnia platform specific code. But this hidden i2c0 slave that
interferes the i2c bus is not board specific. Armada 38x SoCs and at
least some Kirkwood variants are affected as well. Add code to disable
this slave to the i2c bus driver to make it work on all affected
hardware.
Use the bind callback because we want this to always run at boot,
regardless of whether U-Boot uses the i2c bus.
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
I just stumbled over some cluttered UBI messages. It seems some newline
chars are missing in the current U-Boot UBI source. Lets fix this
in U-Boot as well (Linux has those fixes already).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Since commit 0e373c0ade ("spl: add SPL_RESET_SUPPORT"),
reset is supported in SPL, enable this flag for STM32F SoCs family.
This allows to remove a specific case in RCC mfd driver.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Split the rtc_{get,set,reset} functions so that the bodies can be used
in a DM driver.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This flash IC is used in some chromebook models
manufactured by Bitland.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The clean_bar() function resets the SPI NOR BAR register to 0, but
does not set the flash->curr_bar to 0 , therefore those two can get
out of sync, which could ultimatelly result in corrupted flash content.
The simplest test case is this:
=> mw 0x10000000 0x1234abcd 0x4000
=> sf probe
=> sf erase 0x1000000 0x10000
=> sf write 0x10000000 0x1000000 0x10000
=> sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000
That is, erase a sector above the 16 MiB boundary and write it with
random pre-configured data. What will actually happen without this
patch is the sector will be erased, but the data will be written to
BAR 0 offset 0x0 in the flash.
This is because the erase command will call write_bar()+clean_bar(),
which will leave flash->bank_curr = 1 while the hardware BAR registers
will be set to 0 through clean_bar(). The subsequent write will also
trigger write_bar()+clean_bar(), but write_bar checks if the target
bank == flash->bank_curr and if so, does NOT reconfigure the BAR in
the SPI NOR. Since flash->bank_curr is still 1 and out of sync with
the HW, the condition matches, BAR programming is skipped and write
ends up at address 0x0, thus corrupting flash content.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change to use devfdt_get_addr_index() function to get fdt address.
Original code has compilation warning below:
drivers/spi/cadence_qspi.c: In function ‘cadence_spi_ofdata_to_platdata’:
drivers/spi/cadence_qspi.c:297:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
plat->regbase = (void *)data[0];
^
drivers/spi/cadence_qspi.c:298:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
plat->ahbbase = (void *)data[2];
^
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
If compile with support for the efi loader we need to mark the pages
allocated for the framebuffer as reserved so the kernel won't attempt
to use them for other uses.
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Also fix bad accents in my name.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Also fix bad accents in my name.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Also fix bad accents in my name.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Also fix bad accents in my name.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen tool.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support to load secure bitstreams(authenticated or
encrypted or both). As of now, this feature is added and tested only
for xilinx bitstreams and the secure bitstream was generated using
xilinx bootgen tool, but the command is defined in more generic way.
Command example to load authenticated and device key
encrypted bitstream is as follows
"fpga loads 0 100000 2000000 0 1"
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add new compatible to the Ethernet AVB driver for R8A77990 E3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add new compatible to the Uniphier SD driver for R8A77990 E3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add new compatible to the GPIO driver for R8A77990 E3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds initial pinctrl driver to support for the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The PE clock have two parents, add support for picking the correct
one and deriving the clock from it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The PLL rate could be in the GHz range, which could overflow a 32bit
data type. Since the hardware is 64bit anyway, pass the clock rates
as 64bit number internally to avoid this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The mul and div arguments were reported in reverse order in the debug
message, swap them to fix this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds HS200 suuport for ZynqMP and enables
the same for ZC1751 DC1 board which has eMMC on it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use live-tree functions.
Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no reason to specify header with full soc name.
Symlink is setup automatically (arch -> arch-zynqmp)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Convert USB fastboot code to use shared fastboot protocol.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Introduce 'oem format' which matches the USB implementation, guard this
with CONFIG_FASTBOOT_CMD_OEM_FORMAT so that you can configure it out.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Introduce CONFIG_IMAGE_SPARSE and CONFIG_CMD_MMC_SWRITE so the "mmc
swrite" command is separated from the fastboot code.
Move image-sparse from common to lib so it's clear it's library code.
Rename CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE to CONFIG_IMAGE_SPARSE_FILLBUF_SIZE
and migrate it to Kconfig.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add FASTBOOT_FLASH_NAND_TRIMFFS to Kconfig; note there are no in-tree
users of it.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rename fb_mmc_flash_write/fb_mmc_erase/fb_nand_flash_write/fb_nand_erase to
fastboot_... as they form a public interface
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move FASTBOOT_VERSION to include/fastboot.h so when we merge the UDP code
we only have one definition.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Rename fb_set_reboot_flag to fastboot_set_reboot_flag so it matches
all other fastboot code in the global name space. Fix the guards around
them so that they're dependent on FASTBOOT, not just USB_FUNCTION_FASTBOOT.
Move the weak implementation of fastboot_set_reboot_flag to fb_common.c
so we can call it from non-USB fastboot code.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Compiling on a 64 bit target the arguments to _fb_nand_write are
incompatible:
drivers/fastboot/fb_nand.c: In function ‘_fb_nand_write’:
drivers/fastboot/fb_nand.c:101:42: warning: passing argument 3 of ‘nand_write_skip_bad’ from incompatible pointer type [-Wincompatible-pointer-types]
return nand_write_skip_bad(mtd, offset, &length, written,
^
In file included from drivers/fastboot/fb_nand.c:16:0:
include/nand.h:107:5: note: expected ‘size_t * {aka long unsigned int *}’ but argument is of type ‘unsigned int *’
int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
^~~~~~~~~~~~~~~~~~~
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
CONFIG_FASTBOOT_GPT_NAME and CONFIG_FASTBOOT_MBR_NAME are always defined
by Kconfig if you're compiling this code, so remove these redundant
defaults.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add newlines so we format our output correctly.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jocelyn Bohr <bohr@google.com>
Ensure that when selecting FASTBOOT_FLASH you end up with a buildable
configuration. Prior to this you could select NAND without MTDPARTS
and end up with an image which (surprisingly) excluded NAND.
Also fix dependencies on FASTBOOT_GPT_NAME/FASTBOOT_MBR_NAME which require
you have EFI_PARTITION/DOS_PARTITION enabled.
Delete redundant FASTBOOT_FLASH_NAND_DEV from Kconfig - it was only ever
used as a guard and the value was ignored in all cases, we're using
FASTBOOT_FLASH_NAND as the guard now.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Add drivers/fastboot/fb_common.c, where fastboot_okay/fail are implemented
so we can call them from a non-USB implementation.
Introduce fastboot_response which takes varargs parameters so we can
use it to generate formatted response strings. Refactor fastboot_okay/fail
to use it.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Add the response string as a parameter to fastboot_okay/fail, instead
of modifying a global, to match the contract expected by the AOSP
U-Boot code.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Separate CMD_FASTBOOT from FASTBOOT and move code and configuration to
drivers/fastboot.
Switch dependencies on FASTBOOT to USB_FUNCTION_FASTBOOT as anyone who wants
FASTBOOT before this series wants USB_FUNCTION_FASTBOOT. Split
USB_FUNCTION_FASTBOOT from FASTBOOT so they retain their existing
behaviour.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There are memory leaks of usb request and its buffer for ep0,
in_ep, and out ep. Fix memory leaks of usb request and its buffer.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
The xhci wrapper-driver for Rockchip searches the DTS to find its
child node compatbile with 'rockchip,rk3399-usb3-phy' to retrieve the
base-address of the PHY. However, this is currently broken (and
always has been), returning NULL. However, the (wrongly) retrieved
base-address is never used.
We thus remove this code for now.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
In xhci_set_configuration(), 'Context Entries' field in the slot
context was cleared with mask LAST_CTX_MASK, but it should have
taken the endianness into consideration.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
If a full speed hub connects to a high speed hub which supports MTT,
the MTT field of its slot context will be set to 1 when xHCI driver
setups an xHCI virtual device in xhci_setup_addressable_virt_dev().
Once usb core fetch its hub descriptor, and need to update the xHC's
internal data structures for the device, the HUB field of its slot
context will be set to 1 too, meanwhile MTT is also set before, this
will cause configure endpoint command fail. In the case, we should
clear MTT to 0 for full speed hub according to section 6.2.2.
This keeps in sync with Linux kernel commit:
096b110: usb: xhci: fix config fail of FS hub behind a HS hub with MTT
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Per xHCI spec chapter 6.2.2 table 6-7, as input, software shall
initialize the dev_state field to '0'. Though this does not seem
to cause any issue with most xHC implementations, let's do this
to conform with the spec.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Matthias Blankertz <matthias.blankertz@cetitec.com>
If a USB 3.0 hub is plugged into the root port of the xHC, the xHCI
driver will issue a 'Configure Endpoint' command to the xHC for it
to update its internal data structure for this hub device. The hub
attributes are in the slot context so we need tell xHC to update the
slot context by setting the add context flags of the input control
context to only cover the slot context.
At present the add context flags is or'ed with the slot context bit,
but it should really be accurately set to the slot context, as the
variable that holds the value of the add context flags comes from
whatever was set in the last command execution, which may contain
additional contexts that 'Configure Endpoint' command should not
touch. Some xHC implementations like x86 don't complain such, but
it was observed on Renesas RCar Gen3 platform that the RCar xHC
complains with a 'TRB error' completion codes as the response.
Reported-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Matthias Blankertz <matthias.blankertz@cetitec.com>
During the execution of xhci_deregister xHCI registers are accessed. If
the clock is already deactivated when xhci_deregister is called this can
lead to undefined behavior. Change the order to deregister the device
before deactivating the clock.
Signed-off-by: Matthias Blankertz <matthias.blankertz@cetitec.com>
ftsmc020_init is not used anymore.
So it can be removed.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
The compatible string of ftsdc010_mci.c is different from
the mmc driver in Linux Kernel. Modify it for consistency.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Fix warnings as below when compile in 64-bit.
warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Fix warning as below when compile in 64-bit.
warning: format '%u' expects argument of type
'unsigned int', but argument 6 has type 'size_t
{aka long unsigned int}
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Mvebu AHCI is AHCI driver which uses SCSI under the hood.
This patch adjusts AHCI setup to support SCSI by creating
a SCSI device as a child. Since the functions of creating
SCSI device need the kconfig option DM_SCSI, so let
AHCI_MVEBU select DM_SCSI.
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This workaround was added for A8040/7040 A0.
A8040/7040 A0 is no longer supported so this workaround
can be removed.
Signed-off-by: David Sniatkiwicz <davidsn@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Currently mvebu sata driver is in arch/arm/mach_mvebu directory, this
patch moves it to drivers/ata directory with renaming "sata.c" to
"ahci_mvebu.c" which is aligned to Linux.
New ahci driver's kconfig option is added as AHCI_MVEBU which selects
SCSI_AHCI and is based on AHCI.
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
When the pin control driver selects SD/eMMC function for
a pin group, there is additional configuration to be done
for this case - switch the PHY to work with SDHCI interface.
This patch adds the missing functionality into the pin
control driver.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Evan Wang <xswang@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
For pinctrl driver of mvebu, the compatible strings
supported are defined differently from Linux version.
The patch aligned the compatible string with
Linux 4.17-rc4.
Signed-off-by: Evan Wang <xswang@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Allwinner USB PHY handling can be done through driver-model
generic-phy so add the generic-phy ops to relevant places
on host and musb sunxi driver and enable them in respective
SOC's.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
The sunxi otg phy has a bug where it wrongly detects a high speed squelch
when reset on the root port gets de-asserted with a lo-speed device.
The workaround for this is to disable squelch detect before de-asserting
reset, and re-enabling it after the reset de-assert is done. Add a sunxi
specific phy function to allow the sunxi-musb glue to do this.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Allwinner A23 has 2 USB PHY's and 0x04 has phy ctrl offset.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Allwinner A33 has 2 USB PHY's and 0x10 has phy ctrl offset.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Add PHY configs for Allwinner A10/A13/A20 which are SUN4I.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Unlike, other Allwinner SUN4I Phy supporting SOC, A83T has
2 USB PHY's and second one is HSIC. So phy control need to
configure to handle these HSIC and SIDDQ requirement.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
ID and VBUS detection code require when musb changing
between Host and/or Peripheral modes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
USB PHY implementation for Allwinner SOC's can be handling
in to single driver with different phy configs.
This driver handle all Allwinner USB PHY's start from 4I to
50I(except 9I). Currently added A64 compatibility more will
add in next coming patches.
Current implementation is unable to get pinctrl, clock and reset
details from DT since the dm code on these will add it future.
Driver named as phy-sun4i-usb.c since the same PHY logic
work for all Allwinner SOC's start from 4I to A64 except 9I
with different phy configurations.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Like other Allwinner SoC, the H3/H5/A64 is missing the config register
from the musb hardware block. Use a known working value for it
like other SoC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Unlike other Allwinner SOC's H3/H5/V3s OTG support 4 endpoints
with relevant fifo configs, rest all have 5 endpoints.
So add the fifo configs and defer them based on driver_data.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Filling musb_hdrc pdata using structure will unnecessary
add extra ifdefs, so fill them inside probe call for
better code understanding and get rid ifdefs using
devicetree compatible.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
- add proper macros for musb_config members
- use bool 'true' for multipoint and dyn_fifo instead of numerical 1
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
Move struct sunxi_ccm_reg pointer to private structure
so-that accessing ccm reg base become more proper way
and avoid local initialization in each function.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
SDMMC_CMD_CPSMEN bit is wrongly check and set in
SDMMC_ARG register instead of SDMMC_CMD register.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add possibility to update the serial parity used.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Rename USART_ISR_FLAG_xxx bits to USART_ISR_xxx bits and
USART_ICR_OREF to USART_ICR_ORECF in order to match datasheets.
Sort defines by descendant order.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for early debug printf, before the availability of
driver model and device tree support.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Serial port configuration was missing from previous implementation.
It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
The uart is already initialized prior to relocation,
reinitialization after relocation is unnecessary.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Failure to set the clocks will causes data abort exception when
trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock
setting failed.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
