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Merge git://git.denx.de/u-boot-x86

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This commit is contained in:
Tom Rini 2018-06-13 11:43:59 -04:00
commit 66398944f5
32 changed files with 358 additions and 212 deletions
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6
arch/x86/Kconfig
View file

@ -735,6 +735,12 @@ config I8259_PIC
slave) interrupt controllers. Include this to have U-Boot set up
the interrupt correctly.
config PINCTRL_ICH6
bool
help
Intel ICH6 compatible chipset pinctrl driver. It needs to work
together with the ICH6 compatible gpio driver.
config I8254_TIMER
bool
default y

3
arch/x86/cpu/Makefile
View file

@ -18,7 +18,8 @@ obj-y += cpu.o cpu_x86.o
ifndef CONFIG_$(SPL_)X86_64
AFLAGS_REMOVE_call32.o := -mregparm=3 \
$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
AFLAGS_call32.o := -fpic -fshort-wchar
AFLAGS_call32.o := -fpic -fshort-wchar \
$(if $(CONFIG_EFI_STUB_64BIT),-m64)
extra-y += call32.o
endif

1
arch/x86/cpu/baytrail/Kconfig
View file

@ -12,6 +12,7 @@ config INTEL_BAYTRAIL
imply AHCI_PCI
imply ICH_SPI
imply INTEL_ICH6_GPIO
imply PINCTRL_ICH6
imply MMC
imply MMC_PCI
imply MMC_SDHCI

2
arch/x86/cpu/baytrail/cpu.c
View file

@ -80,7 +80,7 @@ static void set_max_freq(void)
perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
/*
* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
* Set guaranteed vid [22:16] from IACORE_VIDS to bits [7:0] of
* the PERF_CTL
*/
msr = msr_read(MSR_IACORE_VIDS);

5
arch/x86/cpu/intel_common/mrc.c
View file

@ -242,11 +242,6 @@ static int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
version >> 24 , (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
#if CONFIG_USBDEBUG
/* mrc.bin reconfigures USB, so reinit it to have debug */
early_usbdebug_init();
#endif
return 0;
}

127
arch/x86/cpu/irq.c
View file

@ -16,16 +16,75 @@
DECLARE_GLOBAL_DATA_PTR;
/**
* pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number
*
* @priv: IRQ router driver's priv data
* @reg: PIRQ routing register offset from the base address
* @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
*/
static inline int pirq_reg_to_linkno(struct irq_router *priv, int reg)
{
int linkno = 0;
if (priv->has_regmap) {
struct pirq_regmap *map = priv->regmap;
int i;
for (i = 0; i < priv->link_num; i++) {
if (reg - priv->link_base == map->offset) {
linkno = map->link;
break;
}
map++;
}
} else {
linkno = reg - priv->link_base;
}
return linkno;
}
/**
* pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset
*
* @priv: IRQ router driver's priv data
* @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
* @return: PIRQ routing register offset from the base address
*/
static inline int pirq_linkno_to_reg(struct irq_router *priv, int linkno)
{
int reg = 0;
if (priv->has_regmap) {
struct pirq_regmap *map = priv->regmap;
int i;
for (i = 0; i < priv->link_num; i++) {
if (linkno == map->link) {
reg = map->offset + priv->link_base;
break;
}
map++;
}
} else {
reg = linkno + priv->link_base;
}
return reg;
}
bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
{
struct irq_router *priv = dev_get_priv(dev);
u8 pirq;
int base = priv->link_base;
if (priv->config == PIRQ_VIA_PCI)
dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
dm_pci_read_config8(dev->parent,
pirq_linkno_to_reg(priv, link), &pirq);
else
pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base));
pirq = readb((uintptr_t)priv->ibase +
pirq_linkno_to_reg(priv, link));
pirq &= 0xf;
@ -40,22 +99,23 @@ int pirq_translate_link(struct udevice *dev, int link)
{
struct irq_router *priv = dev_get_priv(dev);
return LINK_V2N(link, priv->link_base);
return pirq_reg_to_linkno(priv, link);
}
void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
{
struct irq_router *priv = dev_get_priv(dev);
int base = priv->link_base;
/* IRQ# 0/1/2/8/13 are reserved */
if (irq < 3 || irq == 8 || irq == 13)
return;
if (priv->config == PIRQ_VIA_PCI)
dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
dm_pci_write_config8(dev->parent,
pirq_linkno_to_reg(priv, link), irq);
else
writeb(irq, (uintptr_t)priv->ibase + LINK_N2V(link, base));
writeb(irq, (uintptr_t)priv->ibase +
pirq_linkno_to_reg(priv, link));
}
static struct irq_info *check_dup_entry(struct irq_info *slot_base,
@ -78,7 +138,7 @@ static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
{
slot->bus = bus;
slot->devfn = (device << 3) | 0;
slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
slot->irq[pin - 1].link = pirq_linkno_to_reg(priv, pirq);
slot->irq[pin - 1].bitmap = priv->irq_mask;
}
@ -89,6 +149,7 @@ static int create_pirq_routing_table(struct udevice *dev)
int node;
int len, count;
const u32 *cell;
struct pirq_regmap *map;
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
@ -112,10 +173,43 @@ static int create_pirq_routing_table(struct udevice *dev)
return -EINVAL;
}
ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
if (ret == -1)
return ret;
priv->link_base = ret;
cell = fdt_getprop(blob, node, "intel,pirq-link", &len);
if (!cell || len != 8)
return -EINVAL;
priv->link_base = fdt_addr_to_cpu(cell[0]);
priv->link_num = fdt_addr_to_cpu(cell[1]);
if (priv->link_num > CONFIG_MAX_PIRQ_LINKS) {
debug("Limiting supported PIRQ link number from %d to %d\n",
priv->link_num, CONFIG_MAX_PIRQ_LINKS);
priv->link_num = CONFIG_MAX_PIRQ_LINKS;
}
cell = fdt_getprop(blob, node, "intel,pirq-regmap", &len);
if (cell) {
if (len % sizeof(struct pirq_regmap))
return -EINVAL;
count = len / sizeof(struct pirq_regmap);
if (count < priv->link_num) {
printf("Number of pirq-regmap entires is wrong\n");
return -EINVAL;
}
count = priv->link_num;
priv->regmap = calloc(count, sizeof(struct pirq_regmap));
if (!priv->regmap)
return -ENOMEM;
priv->has_regmap = true;
map = priv->regmap;
for (i = 0; i < count; i++) {
map->link = fdt_addr_to_cpu(cell[0]);
map->offset = fdt_addr_to_cpu(cell[1]);
cell += sizeof(struct pirq_regmap) / sizeof(u32);
map++;
}
}
priv->irq_mask = fdtdec_get_int(blob, node,
"intel,pirq-mask", PIRQ_BITMAP);
@ -199,7 +293,7 @@ static int create_pirq_routing_table(struct udevice *dev)
* routing information in the device tree.
*/
if (slot->irq[pr.pin - 1].link !=
LINK_N2V(pr.pirq, priv->link_base))
pirq_linkno_to_reg(priv, pr.pirq))
debug("WARNING: Inconsistent PIRQ routing information\n");
continue;
}
@ -237,7 +331,7 @@ static void irq_enable_sci(struct udevice *dev)
}
}
int irq_router_common_init(struct udevice *dev)
int irq_router_probe(struct udevice *dev)
{
int ret;
@ -256,11 +350,6 @@ int irq_router_common_init(struct udevice *dev)
return 0;
}
int irq_router_probe(struct udevice *dev)
{
return irq_router_common_init(dev);
}
ulong write_pirq_routing_table(ulong addr)
{
if (!gd->arch.pirq_routing_table)

2
arch/x86/cpu/ivybridge/Kconfig
View file

@ -13,11 +13,13 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
imply AHCI_PCI
imply ICH_SPI
imply INTEL_ICH6_GPIO
imply PINCTRL_ICH6
imply SCSI
imply SCSI_AHCI
imply SPI_FLASH
imply USB
imply USB_EHCI_HCD
imply USB_XHCI_HCD
imply VIDEO_VESA
if NORTHBRIDGE_INTEL_IVYBRIDGE

2
arch/x86/cpu/ivybridge/Makefile
View file

@ -8,7 +8,6 @@ else
obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o
obj-y += early_me.o
obj-y += lpc.o
obj-y += model_206ax.o
obj-y += northbridge.o
ifndef CONFIG_SPL_BUILD
obj-y += sata.o
@ -18,4 +17,5 @@ ifndef CONFIG_$(SPL_)X86_32BIT_INIT
obj-y += sdram_nop.o
endif
endif
obj-y += model_206ax.o
obj-y += bd82x6x.o

15
arch/x86/cpu/ivybridge/model_206ax.c
View file

@ -393,10 +393,6 @@ static void configure_mca(void)
msr_write(IA32_MC0_STATUS + (i * 4), msr);
}
#if CONFIG_USBDEBUG
static unsigned ehci_debug_addr;
#endif
static int model_206ax_init(struct udevice *dev)
{
int ret;
@ -404,17 +400,6 @@ static int model_206ax_init(struct udevice *dev)
/* Clear out pending MCEs */
configure_mca();
#if CONFIG_USBDEBUG
/* Is this caution really needed? */
if (!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif
#if CONFIG_USBDEBUG
set_ehci_debug(ehci_debug_addr);
#endif
/* Enable the local cpu apics */
enable_lapic_tpr();

2
arch/x86/cpu/quark/Makefile
View file

@ -2,6 +2,6 @@
#
# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
obj-y += car.o dram.o irq.o msg_port.o quark.o
obj-y += car.o dram.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o

48
arch/x86/cpu/quark/irq.c
View file

@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
* Copyright (C) 2015 Google, Inc
*/
#include <common.h>
#include <dm.h>
#include <asm/irq.h>
#include <asm/arch/device.h>
#include <asm/arch/quark.h>
int quark_irq_router_probe(struct udevice *dev)
{
struct quark_rcba *rcba;
u32 base;
qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct quark_rcba *)base;
/*
* Route Quark PCI device interrupt pin to PIRQ
*
* Route device#23's INTA/B/C/D to PIRQA/B/C/D
* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
*/
writew(PIRQC, &rcba->rmu_ir);
writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
&rcba->d23_ir);
writew(PIRQD, &rcba->core_ir);
writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
&rcba->d20d21_ir);
return irq_router_common_init(dev);
}
static const struct udevice_id quark_irq_router_ids[] = {
{ .compatible = "intel,quark-irq-router" },
{ }
};
U_BOOT_DRIVER(quark_irq_router_drv) = {
.name = "quark_intel_irq",
.id = UCLASS_IRQ,
.of_match = quark_irq_router_ids,
.probe = quark_irq_router_probe,
};

26
arch/x86/cpu/quark/quark.c
View file

@ -7,6 +7,7 @@
#include <mmc.h>
#include <asm/io.h>
#include <asm/ioapic.h>
#include <asm/irq.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
@ -313,12 +314,37 @@ static void quark_usb_init(void)
writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
}
static void quark_irq_init(void)
{
struct quark_rcba *rcba;
u32 base;
qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct quark_rcba *)base;
/*
* Route Quark PCI device interrupt pin to PIRQ
*
* Route device#23's INTA/B/C/D to PIRQA/B/C/D
* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
*/
writew(PIRQC, &rcba->rmu_ir);
writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
&rcba->d23_ir);
writew(PIRQD, &rcba->core_ir);
writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
&rcba->d20d21_ir);
}
int arch_early_init_r(void)
{
quark_pcie_init();
quark_usb_init();
quark_irq_init();
return 0;
}

2
arch/x86/cpu/queensbay/Makefile
View file

@ -2,5 +2,5 @@
#
# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
obj-y += fsp_configs.o irq.o
obj-y += fsp_configs.o
obj-y += tnc.o

64
arch/x86/cpu/queensbay/irq.c
View file

@ -1,64 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
* Copyright (C) 2015 Google, Inc
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/arch/device.h>
#include <asm/arch/tnc.h>
int queensbay_irq_router_probe(struct udevice *dev)
{
struct tnc_rcba *rcba;
u32 base;
dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct tnc_rcba *)base;
/* Make sure all internal PCI devices are using INTA */
writel(INTA, &rcba->d02ip);
writel(INTA, &rcba->d03ip);
writel(INTA, &rcba->d27ip);
writel(INTA, &rcba->d31ip);
writel(INTA, &rcba->d23ip);
writel(INTA, &rcba->d24ip);
writel(INTA, &rcba->d25ip);
writel(INTA, &rcba->d26ip);
/*
* Route TunnelCreek PCI device interrupt pin to PIRQ
*
* Since PCIe downstream ports received INTx are routed to PIRQ
* A/B/C/D directly and not configurable, we have to route PCIe
* root ports' INTx to PIRQ A/B/C/D as well. For other devices
* on TunneCreek, route them to PIRQ E/F/G/H.
*/
writew(PIRQE, &rcba->d02ir);
writew(PIRQF, &rcba->d03ir);
writew(PIRQG, &rcba->d27ir);
writew(PIRQH, &rcba->d31ir);
writew(PIRQA, &rcba->d23ir);
writew(PIRQB, &rcba->d24ir);
writew(PIRQC, &rcba->d25ir);
writew(PIRQD, &rcba->d26ir);
return irq_router_common_init(dev);
}
static const struct udevice_id queensbay_irq_router_ids[] = {
{ .compatible = "intel,queensbay-irq-router" },
{ }
};
U_BOOT_DRIVER(queensbay_irq_router_drv) = {
.name = "queensbay_intel_irq",
.id = UCLASS_IRQ,
.of_match = queensbay_irq_router_ids,
.probe = queensbay_irq_router_probe,
};

39
arch/x86/cpu/queensbay/tnc.c
View file

@ -98,6 +98,43 @@ int arch_cpu_init(void)
return x86_cpu_init_f();
}
static void tnc_irq_init(void)
{
struct tnc_rcba *rcba;
u32 base;
pci_read_config32(TNC_LPC, LPC_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct tnc_rcba *)base;
/* Make sure all internal PCI devices are using INTA */
writel(INTA, &rcba->d02ip);
writel(INTA, &rcba->d03ip);
writel(INTA, &rcba->d27ip);
writel(INTA, &rcba->d31ip);
writel(INTA, &rcba->d23ip);
writel(INTA, &rcba->d24ip);
writel(INTA, &rcba->d25ip);
writel(INTA, &rcba->d26ip);
/*
* Route TunnelCreek PCI device interrupt pin to PIRQ
*
* Since PCIe downstream ports received INTx are routed to PIRQ
* A/B/C/D directly and not configurable, we have to route PCIe
* root ports' INTx to PIRQ A/B/C/D as well. For other devices
* on TunneCreek, route them to PIRQ E/F/G/H.
*/
writew(PIRQE, &rcba->d02ir);
writew(PIRQF, &rcba->d03ir);
writew(PIRQG, &rcba->d27ir);
writew(PIRQH, &rcba->d31ir);
writew(PIRQA, &rcba->d23ir);
writew(PIRQB, &rcba->d24ir);
writew(PIRQC, &rcba->d25ir);
writew(PIRQD, &rcba->d26ir);
}
int arch_early_init_r(void)
{
int ret = 0;
@ -106,5 +143,7 @@ int arch_early_init_r(void)
ret = disable_igd();
#endif
tnc_irq_init();
return ret;
}

5
arch/x86/dts/chromebook_link.dts
View file

@ -26,14 +26,12 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
cpu@0 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <0>;
intel,apic-id = <0>;
u-boot,dm-pre-reloc;
};
cpu@1 {
@ -41,7 +39,6 @@
compatible = "intel,core-gen3";
reg = <1>;
intel,apic-id = <1>;
u-boot,dm-pre-reloc;
};
cpu@2 {
@ -49,7 +46,6 @@
compatible = "intel,core-gen3";
reg = <2>;
intel,apic-id = <2>;
u-boot,dm-pre-reloc;
};
cpu@3 {
@ -57,7 +53,6 @@
compatible = "intel,core-gen3";
reg = <3>;
intel,apic-id = <3>;
u-boot,dm-pre-reloc;
};
};

81
arch/x86/dts/cougarcanyon2.dts
View file

@ -5,6 +5,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-router/intel-irq.h>
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
@ -27,6 +29,39 @@
stdout-path = "/serial";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <1>;
intel,apic-id = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <2>;
intel,apic-id = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <3>;
intel,apic-id = <3>;
};
};
microcode {
update@0 {
#include "microcode/m12306a2_00000008.dtsi"
@ -66,10 +101,56 @@
#address-cells = <1>;
#size-cells = <1>;
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,actl-8bit;
intel,actl-addr = <0x44>;
intel,pirq-link = <0x60 8>;
intel,pirq-regmap = <
PIRQA 0
PIRQB 1
PIRQC 2
PIRQD 3
PIRQE 8
PIRQF 9
PIRQG 10
PIRQH 11
>;
intel,pirq-mask = <0xcee0>;
intel,pirq-routing = <
/* Panther Point PCI devices */
PCI_BDF(0, 2, 0) INTA PIRQA
PCI_BDF(0, 20, 0) INTA PIRQA
PCI_BDF(0, 22, 0) INTA PIRQA
PCI_BDF(0, 22, 1) INTB PIRQB
PCI_BDF(0, 22, 2) INTC PIRQC
PCI_BDF(0, 22, 3) INTD PIRQD
PCI_BDF(0, 25, 0) INTA PIRQA
PCI_BDF(0, 26, 0) INTA PIRQA
PCI_BDF(0, 27, 0) INTB PIRQA
PCI_BDF(0, 28, 0) INTA PIRQA
PCI_BDF(0, 28, 1) INTB PIRQB
PCI_BDF(0, 28, 2) INTC PIRQC
PCI_BDF(0, 28, 3) INTD PIRQD
PCI_BDF(0, 28, 4) INTA PIRQA
PCI_BDF(0, 28, 5) INTB PIRQB
PCI_BDF(0, 28, 6) INTC PIRQC
PCI_BDF(0, 28, 7) INTD PIRQD
PCI_BDF(0, 29, 0) INTA PIRQA
PCI_BDF(0, 31, 2) INTB PIRQB
PCI_BDF(0, 31, 3) INTC PIRQC
PCI_BDF(0, 31, 5) INTB PIRQB
PCI_BDF(0, 31, 6) INTC PIRQC
>;
};
spi0: spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
intel,spi-lock-down;
spi-flash@0 {
reg = <0>;
compatible = "winbond,w25q64bv", "spi-flash";

2
arch/x86/dts/crownbay.dts
View file

@ -151,7 +151,7 @@
#size-cells = <1>;
irq-router {
compatible = "intel,queensbay-irq-router";
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,actl-addr = <0x58>;
intel,pirq-link = <0x60 8>;

2
arch/x86/dts/galileo.dts
View file

@ -97,7 +97,7 @@
#size-cells = <1>;
irq-router {
compatible = "intel,quark-irq-router";
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,actl-addr = <0x58>;
intel,pirq-link = <0x60 8>;

21
arch/x86/include/asm/irq.h
View file

@ -22,6 +22,11 @@ enum pirq_config {
PIRQ_VIA_IBASE
};
struct pirq_regmap {
int link;
int offset;
};
/**
* Intel interrupt router control block
*
@ -29,6 +34,8 @@ enum pirq_config {
*
* @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
* @link_base: link value base number
* @link_num: number of PIRQ links supported
* @has_regmap: has mapping table between PIRQ link and routing register offset
* @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
* IRQ N is available to be routed
* @lb_bdf: irq router's PCI bus/device/function number encoding
@ -39,6 +46,9 @@ enum pirq_config {
struct irq_router {
int config;
u32 link_base;
int link_num;
bool has_regmap;
struct pirq_regmap *regmap;
u16 irq_mask;
u32 bdf;
u32 ibase;
@ -52,17 +62,6 @@ struct pirq_routing {
int pirq;
};
/* PIRQ link number and value conversion */
#define LINK_V2N(link, base) (link - base)
#define LINK_N2V(link, base) (link + base)
#define PIRQ_BITMAP 0xdef8
/**
* irq_router_common_init() - Perform common x86 interrupt init
*
* This creates the PIRQ routing table and routes the IRQs
*/
int irq_router_common_init(struct udevice *dev);
#endif /* _ARCH_IRQ_H_ */

6
arch/x86/lib/Makefile
View file

@ -24,7 +24,7 @@ obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
obj-y += northbridge-uclass.o
obj-$(CONFIG_I8259_PIC) += i8259.o
obj-$(CONFIG_I8254_TIMER) += i8254.o
obj-y += pinctrl_ich6.o
obj-$(CONFIG_PINCTRL_ICH6) += pinctrl_ich6.o
obj-y += pirq_routing.o
obj-y += relocate.o
obj-y += physmem.o
@ -58,10 +58,10 @@ CFLAGS_reloc_ia32_efi.o += -fpic -fshort-wchar
# When building for 64-bit we must remove the i386-specific flags
CFLAGS_REMOVE_reloc_x86_64_efi.o += -mregparm=3 -march=i386 -m32
CFLAGS_reloc_x86_64_efi.o += -fpic -fshort-wchar
CFLAGS_reloc_x86_64_efi.o += -fpic -fshort-wchar -m64
AFLAGS_REMOVE_crt0_x86_64_efi.o += -mregparm=3 -march=i386 -m32
AFLAGS_crt0_x86_64_efi.o += -fpic -fshort-wchar
AFLAGS_crt0_x86_64_efi.o += -fpic -fshort-wchar -m64
extra-$(CONFIG_EFI_STUB_32BIT) += crt0_ia32_efi.o reloc_ia32_efi.o
extra-$(CONFIG_EFI_STUB_64BIT) += crt0_x86_64_efi.o reloc_x86_64_efi.o

6
configs/cougarcanyon2_defconfig
View file

@ -3,13 +3,18 @@ CONFIG_SYS_TEXT_BASE=0xFFE00000
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
CONFIG_TARGET_COUGARCANYON2=y
# CONFIG_HAVE_INTEL_ME is not set
# CONFIG_ENABLE_MRC_CACHE is not set
CONFIG_SMP=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_PART=y
@ -31,6 +36,7 @@ CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB_STORAGE=y

8
configs/efi-x86_defconfig
View file

@ -13,12 +13,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTM is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SF_TEST is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@ -30,10 +26,10 @@ CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_OF_EMBED=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_DM_ETH is not set
CONFIG_DEBUG_EFI_CONSOLE=y
CONFIG_SPI=y
CONFIG_ICH_SPI=y
# CONFIG_REGEX is not set
CONFIG_EFI=y
# CONFIG_EFI_LOADER is not set

4
doc/README.x86
View file

@ -256,7 +256,9 @@ the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
this image to the SPI-0 flash according to the board manual just once and we are
all set. For programming U-Boot we just need to program SPI-1 flash.
all set. For programming U-Boot we just need to program SPI-1 flash. Since the
default u-boot.rom image for this board is set to 2MB, it should be programmed
to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
---

6
doc/device-tree-bindings/misc/intel,irq-router.txt
View file

@ -22,6 +22,12 @@ Required properties :
- intel,pirq-link : Specifies the PIRQ link information with two cells. The
first cell is the register offset that controls the first PIRQ link routing.
The second cell is the total number of PIRQ links the router supports.
- intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links,
encoded as 2 cells a group for each link. The first cell is the PIRQ link
number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing
register offset from the interrupt router's base address. If this property
is omitted, it indicates a consecutive register offset from the first PIRQ
link, as specified by the first cell of intel,pirq-link.
- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
8259 PIC. Bit N is 1 means IRQ N is available to be routed.
- intel,pirq-routing : Specifies all PCI devices' IRQ routing information,

33
drivers/pci/pci-uclass.c
View file

@ -810,8 +810,8 @@ error:
return ret;
}
static int decode_regions(struct pci_controller *hose, ofnode parent_node,
ofnode node)
static void decode_regions(struct pci_controller *hose, ofnode parent_node,
ofnode node)
{
int pci_addr_cells, addr_cells, size_cells;
int cells_per_record;
@ -820,8 +820,11 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
int i;
prop = ofnode_get_property(node, "ranges", &len);
if (!prop)
return -EINVAL;
if (!prop) {
debug("%s: Cannot decode regions\n", __func__);
return;
}
pci_addr_cells = ofnode_read_simple_addr_cells(node);
addr_cells = ofnode_read_simple_addr_cells(parent_node);
size_cells = ofnode_read_simple_size_cells(node);
@ -883,7 +886,7 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
bd_t *bd = gd->bd;
if (!bd)
return 0;
return;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
@ -908,13 +911,12 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
#endif
return 0;
return;
}
static int pci_uclass_pre_probe(struct udevice *bus)
{
struct pci_controller *hose;
int ret;
debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
bus->parent->name);
@ -923,12 +925,7 @@ static int pci_uclass_pre_probe(struct udevice *bus)
/* For bridges, use the top-level PCI controller */
if (!device_is_on_pci_bus(bus)) {
hose->ctlr = bus;
ret = decode_regions(hose, dev_ofnode(bus->parent),
dev_ofnode(bus));
if (ret) {
debug("%s: Cannot decode regions\n", __func__);
return ret;
}
decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
} else {
struct pci_controller *parent_hose;
@ -1185,6 +1182,11 @@ static int _dm_pci_bus_to_phys(struct udevice *ctlr,
struct pci_region *res;
int i;
if (hose->region_count == 0) {
*pa = bus_addr;
return 0;
}
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
@ -1248,6 +1250,11 @@ int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
ctlr = pci_get_controller(dev);
hose = dev_get_uclass_priv(ctlr);
if (hose->region_count == 0) {
*ba = phys_addr;
return 0;
}
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];

31
drivers/timer/tsc_timer.c
View file

@ -21,6 +21,17 @@
DECLARE_GLOBAL_DATA_PTR;
static unsigned long cpu_mhz_from_cpuid(void)
{
if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
return 0;
if (cpuid_eax(0) < 0x16)
return 0;
return cpuid_eax(0x16);
}
/*
* According to Intel 64 and IA-32 System Programming Guide,
* if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
@ -343,13 +354,21 @@ static void tsc_timer_ensure_setup(void)
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
fast_calibrate = cpu_mhz_from_msr();
if (!fast_calibrate) {
fast_calibrate = quick_pit_calibrate();
if (!fast_calibrate)
panic("TSC frequency is ZERO");
}
fast_calibrate = cpu_mhz_from_cpuid();
if (fast_calibrate)
goto done;
fast_calibrate = cpu_mhz_from_msr();
if (fast_calibrate)
goto done;
fast_calibrate = quick_pit_calibrate();
if (fast_calibrate)
goto done;
panic("TSC frequency is ZERO");
done:
gd->arch.clock_rate = fast_calibrate * 1000000;
}
}

5
drivers/usb/host/xhci-pci.c
View file

@ -23,9 +23,8 @@ static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
hcor = (struct xhci_hcor *)((uintptr_t) hccr +
HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
(u32)hccr, (u32)hcor,
(u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
debug("XHCI-PCI init hccr %p and hcor %p hc_length %d\n",
hccr, hcor, (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
*ret_hccr = hccr;
*ret_hcor = hcor;

6
lib/efi/Makefile
View file

@ -7,9 +7,11 @@ obj-$(CONFIG_EFI_STUB) += efi_info.o
CFLAGS_REMOVE_efi_stub.o := -mregparm=3 \
$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
CFLAGS_efi_stub.o := -fpic -fshort-wchar -DEFI_STUB
CFLAGS_efi_stub.o := -fpic -fshort-wchar -DEFI_STUB \
$(if $(CONFIG_EFI_STUB_64BIT),-m64)
CFLAGS_REMOVE_efi.o := -mregparm=3 \
$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
CFLAGS_efi.o := -fpic -fshort-wchar -DEFI_STUB
CFLAGS_efi.o := -fpic -fshort-wchar -DEFI_STUB \
$(if $(CONFIG_EFI_STUB_64BIT),-m64)
extra-$(CONFIG_EFI_STUB) += efi_stub.o efi.o

8
lib/efi/efi_stub.c
View file

@ -281,7 +281,8 @@ efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table)
ret = efi_init(priv, "Payload", image, sys_table);
if (ret) {
printhex2(ret); puts(" efi_init() failed\n");
printhex2(ret);
puts(" efi_init() failed\n");
return ret;
}
global_priv = priv;
@ -294,7 +295,8 @@ efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table)
size = 0;
ret = boot->get_memory_map(&size, NULL, &key, &desc_size, &version);
if (ret != EFI_BUFFER_TOO_SMALL) {
printhex2(BITS_PER_LONG);
printhex2(EFI_BITS_PER_LONG);
putc(' ');
printhex2(ret);
puts(" No memory map\n");
return ret;
@ -303,7 +305,7 @@ efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table)
desc = efi_malloc(priv, size, &ret);
if (!desc) {
printhex2(ret);
puts(" No memory for memory descriptor: ");
puts(" No memory for memory descriptor\n");
return ret;
}
ret = setup_info_table(priv, size + 128);

1
scripts/Makefile.lib
View file

@ -399,6 +399,7 @@ cmd_acpi_c_asl= \
$(obj)/dsdt.c: $(src)/dsdt.asl
$(call cmd,acpi_c_asl)
$(Q)sed -i -e "s,dsdt_aml_code,AmlCode," $@
# Bzip2
# ---------------------------------------------------------------------------

1
scripts/config_whitelist.txt
View file

@ -4581,7 +4581,6 @@ CONFIG_USART1
CONFIG_USART_BASE
CONFIG_USART_ID
CONFIG_USBBOOTCOMMAND
CONFIG_USBDEBUG
CONFIG_USBD_CONFIGURATION_STR
CONFIG_USBD_CTRL_INTERFACE_STR
CONFIG_USBD_DATA_INTERFACE_STR