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serial: zynq: Write chars till output fifo is full

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Change logic and put char to fifo till there is a space in output fifo.
Origin logic was that output fifo needs to be empty. It means only one
char was in output queue.
Also remove unused ZYNQ_UART_SR_TXEMPTY macro.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Michal Simek 2018-06-14 09:43:34 +02:00
parent c9a2c47b91
commit e90d2659e4
1 changed files with 2 additions and 2 deletions
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4
drivers/serial/serial_zynq.c
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@ -15,8 +15,8 @@
#include <linux/compiler.h>
#include <serial.h>
#define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */
#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
@ -93,7 +93,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs)
static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
return -EAGAIN;
writel(c, &regs->tx_rx_fifo);