Commit graph

1011 commits

Author SHA1 Message Date
Ryan Chen
c39c9a94cb clock:aspeed: Sync with Linux kernel clock header define
v2: modify title description aspeed:clock -> clock:aspeed

Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09 16:57:35 -04:00
Ryan Chen
15b87feb2b cosmetic: aspeed: ast2500: Rename clock header
Rename the ast2500-scu.h to aspeed-clock.h.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-09-09 16:57:35 -04:00
Frank Wunderlich
9f25aa13ea clk: mt7622: add needed clocks for ssusb-node
MT7622 needs additional clock definitions to work properly

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24 14:11:31 -04:00
Frank Wunderlich
a300d696ca reset: drop unnecessary comment for pciesys
after review from sam this comment should be removed

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-24 14:11:31 -04:00
Tom Rini
1aa3966173 Merge tag 'u-boot-clk-24Aug2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Add CCF clocks definitions for iMX6Q enet (ETH)
- Several fixes for CCF framework - the most notable is the one, which
  adds get_rate helper to clk-mux.c
- Improvements for clk command - better visibility and alignment.
2020-08-24 09:06:02 -04:00
Lukasz Majewski
ebd3f1f0d0 clk: ccf: Add missing #include <dm/uclass.h> to clk-mux.c
After adding custom get_rate helper function it was necessary to include
<dm/uclass.h> to avoid warnings about missing uclass_get_device_by_name.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Series-to: u-boot
2020-08-24 11:36:34 +02:00
Dario Binacchi
12d152620d clk: ccf: mux: change the get_rate helper
The previous version of the get_rate helper does not work if the mux
clock parent is changed after the probe. This error has not been
detected because this condition has not been tested. The error occurs
because the set_parent helper does not change the parent of the clock
device but only the clock selection register. Since changing the parent
of a probed device can be tricky, the new version of the get_rate helper
provides the rate of the selected clock and not that of the parent.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
e3b5d74c77 clk: ccf: mux: fix access to the sandbox register
The tests developed for the mux clock are run on the sandbox. They don't
call the clk_mux_set_parent routine and therefore they do not detect
this error.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
40559d2774 clk: ccf: mux: fix typo
Close the opening bracket.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
76eaa2d0ed clk: ccf: mux: change include order
Apply u-boot coding style on include files order.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
7b0830d41f clk: fix the console output of clk_register
The parent->name variable can be used only in case the
uclass_get_device_by_name routine returns successfully.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
16bdc85b48 clk: set flags in the ccf registration routines
The top-level framework flags are passed as parameter to the common
clock framework (ccf) registration routines without being used.
Checks of the flags setting added by the patch have been added in the
ccf test.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-08-24 11:03:26 +02:00
Dario Binacchi
cd16c57bd0 dm: test: clk: add the test for the ccf gated clock
Unlike the other clock types, in the case of the gated clock, a new
driver has been developed which does not use the registering routine
provided by the common clock framework.
The addition of the ecspi0 clock to sandbox therefore allows testing
the ccf gate clock.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 11:03:26 +02:00
Lukasz Majewski
32f462ba3b clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clock
After commit 673f659732 ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF need
to provide PTP clock.

On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux
kernel's CCF.

Code in this change models the simplest case when enet reference clock is
generated from 'osc' clock.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24 11:03:26 +02:00
Lukasz Majewski
8d540ccb11 clk: imx: Add support for pllv3 enet clock
This code has been ported from Linux kernel v5.5.5 (tag) and has been
adjusted to U-Boot's DM.

It adds support for correct recognition of IMX_PLLV3_ENET flag in the
clk-pllv3.c driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24 11:03:26 +02:00
Lukasz Majewski
d71fac8479 clk: imx6: Add definition for IMX6QDL_CLK_ENET clock
After commit 673f659732 ("net: fec_mxc: support i.MX8M with CLK_CCF") all
NXP boards, which are not IMX8 and in the same time are supporting CCF
need to provide IMX6QDL_CLK_ENET.

This change defines the missing clock in i.MX6Q's CCF.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-08-24 11:03:26 +02:00
Heinrich Schuchardt
6befc1f900 clk: ICS8N3QV01 remove superfluous code
Do not calculate a unused value of n which is overwritten in both branches
of the subsequent if statement.

Identified by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-08-24 11:03:26 +02:00
Masahiro Yamada
702e57e113 treewide: convert devfdt_get_addr_ptr() to dev_read_addr_ptr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To help this tedious work, this commit converts devfdt_get_addr_ptr()
to dev_read_addr_ptr() by coccinelle. I also removed redundant casts
because dev_read_addr_ptr() returns an opaque pointer.

To generate this commit, I ran the following semantic patch
excluding include/dm/.

  <smpl>
  @@
  type T;
  expression dev;
  @@
  -(T *)devfdt_get_addr_ptr(dev)
  +dev_read_addr_ptr(dev)
  @@
  expression dev;
  @@
  -devfdt_get_addr_ptr(dev)
  +dev_read_addr_ptr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:53:37 -06:00
Ovidiu Panait
3fe69d3764 dm: core: Fix devfdt_get_addr_ptr return value
According to the description of devfdt_get_addr_ptr, this function should
return NULL on failure, but currently it returns (void *)FDT_ADDR_T_NONE.

Fix this by making devfdt_get_addr_ptr return NULL on failure, as
described in the function comments. Also, update the drivers currently
checking (void *)FDT_ADDR_T_NONE to check for NULL.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 07:59:14 -06:00
Tom Rini
2e6132d835 Xilinx changes for v2020.10-rc3
- Fix fdtfile variable setup
 - Fix bootm_*/fdt_high/initrd_high variables handling
 - Fix Kconfig dependencies for Xilinx drivers
 - Fix booting u-boot from lowest memory
 - Fix firmware payload argument count for Versal
 - Fix dfu configurations
 - Fix mio_bank property handling
 - Fix and align code around ID detection
 - Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG
 - Simplify logic around reading MAC from eeprom
 - Decrease malloc length for zynqmp mini qspi
 - Enable preboot for ZynqMP and Versal
 
 i2c:
 - Fix i2c eeprom partitions handling
 
 mmc:
 - Fix logic around HS mode enabling and use proper functions
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Merge tag 'xilinx-for-v2020.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2020.10-rc3

- Fix fdtfile variable setup
- Fix bootm_*/fdt_high/initrd_high variables handling
- Fix Kconfig dependencies for Xilinx drivers
- Fix booting u-boot from lowest memory
- Fix firmware payload argument count for Versal
- Fix dfu configurations
- Fix mio_bank property handling
- Fix and align code around ID detection
- Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG
- Simplify logic around reading MAC from eeprom
- Decrease malloc length for zynqmp mini qspi
- Enable preboot for ZynqMP and Versal

i2c:
- Fix i2c eeprom partitions handling

mmc:
- Fix logic around HS mode enabling and use proper functions
2020-08-20 14:46:43 -04:00
Michal Simek
29af2ac48c clk: versal: Move pm_query_id out of clock driver
There is no reason to have firmware specific structure in clock driver.
Move it to generic location and also initialize enum values which is based
on https://lore.kernel.org/linux-arm-kernel/20200318125003.GA2727094@kroah.com/
recommended way to go to make sure that values guaranteed by compiler.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-20 10:57:46 +02:00
Frank Wunderlich
fee276ee31 reset: add basic reset controller for pciesys
bind reset controller to pciesys

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-19 17:38:15 -04:00
Chuanjia Liu
c5bfe694e7 clk: mediatek: add pciesys support for MT7622 SoC
This patch adds pciesys support in clock driver for
MediaTek MT7622 SoC.

Signed-off-by: Henry Yen <henry.yen@mediatek.com>
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
2020-08-19 17:37:37 -04:00
Tom Rini
4d23857abd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- add DM based reset driver for SiFive SoC's.
2020-08-04 11:07:38 -04:00
Tom Rini
bb3694d5b1 - doc: fix qemu-mips build instructions
- MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
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Merge tag 'mips-pull-2020-08-03' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

- doc: fix qemu-mips build instructions
- MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
2020-08-04 11:07:16 -04:00
Simon Glass
fb989e0c6c clk: Drop dm.h header file in clk-provider.h
This header file should not be included in other header files. Remove it
and use a forward declaration and un-inlining of dev_get_clk_ptr()
instead.

Fix up the kendryte header files to avoid build errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-08-03 22:19:54 -04:00
Sagar Shrikant Kadam
d04a46426b sifive: reset: add DM based reset driver for SiFive SoC's
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Sagar Shrikant Kadam
d2e4398637 fu540: prci: use common reset indexes defined in binding header
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Stefan Roese
b113c9b570 clk: clk_octeon: Add simple MIPS Octeon clock driver
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC
family. Its for IO clock rate passing via DT in some of the Octeon
driver, like I2C. So that we don't need to use the non-mainline API
octeon_get_io_clock().

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
2020-08-03 21:11:41 +02:00
Tom Rini
4e05c167a7 binman support for FIT
new UCLASS_SOC
 patman switch 'test' command
 minor fdt fixes
 patman usability improvements
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Merge tag 'dm-pull-20jul20-take2a' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

binman support for FIT
new UCLASS_SOC
patman switch 'test' command
minor fdt fixes
patman usability improvements
2020-07-27 11:15:37 -04:00
Masahiro Yamada
2548493ab4 treewide: convert devfdt_get_addr() to dev_read_addr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  expression dev;
  @@
  -devfdt_get_addr(dev)
  +dev_read_addr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-25 14:46:57 -06:00
Masahiro Yamada
8613c8d897 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()
Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.

One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:

    priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
    if (!priv->regs)
            return -EINVAL;

devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.

dev_read_addr_ptr() returns NULL on error, so this error check
will work.

I generated this commit by the following command:

 $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
   xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'

I manually fixed drivers/usb/host/ehci-mx6.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-25 14:46:57 -06:00
Adam Ford
e9a52c4439 clk: renesas: Add R8A774A1 clock tables
This sync's the clock tables with the official release from
Linux 5.8-RC2 and update r8a774a1_mstp_table from Ref Manual
v1.00.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25 11:16:39 +02:00
Tom Rini
7208396bbf Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"
This reverts commit 5d3a21df66, reversing
changes made to 56d37f1c56.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24 08:42:06 -04:00
Tom Rini
5d3a21df66 binman support for FIT
new UCLASS_SOC
 patman switch 'test' command
 minor fdt fixes
 patman usability improvements
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Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm

binman support for FIT
new UCLASS_SOC
patman switch 'test' command
minor fdt fixes
patman usability improvements
2020-07-23 15:56:06 -04:00
Johannes Krottmayer
19933b66f4 drivers: clk: rockchip: clk_rk3328: Add SPI support
Add SPI support for the RK3328 clock driver

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:00 +08:00
Masahiro Yamada
60e7fa8b3b treewide: convert devfdt_get_addr() to dev_read_addr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  expression dev;
  @@
  -devfdt_get_addr(dev)
  +dev_read_addr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20 11:37:47 -06:00
Masahiro Yamada
3c12c62ba5 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()
Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.

One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:

    priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
    if (!priv->regs)
            return -EINVAL;

devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.

dev_read_addr_ptr() returns NULL on error, so this error check
will work.

I generated this commit by the following command:

 $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
   xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'

I manually fixed drivers/usb/host/ehci-mx6.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20 11:37:47 -06:00
Peng Fan
ec04ae4217 clk: imx8m: drop clk settings
We use non-dm code to configure the clk settings in order to simplify
dm clk driver in future, so remove the duplicated code from clk driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
ac9a451828 clk: imx8mp: Update imx8mp ccf clock driver
Add clocks for FEC and flexspi, and add set parent clock callback,
so DTS can assign clocks

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
4b6548d17d clk: imx8mm/8mn: Add USB clocks
Add USB relevant clocks to support usb clock settings for both
DM USB host and gadget drivers

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
ee1f8b226f clk: clk-imx8mn: Update clock tree and support set parent
Add set clock parent support.
Add ENET and flexspi related clocks to support assigned clocks

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
a65409420d clk: imx8mm: Add qspi clock
Add qspi clock

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
7ddb4ef3e1 clk: imx8mm: fix clk set parent
Fix clk set parent, so we could still have correct clocks after
parent changing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Walter Lozano
51f1263d89 dtoc: extend dtoc to use struct driver_info when linking nodes
In the current implementation, when dtoc parses a dtb to generate a struct
platdata it converts the information related to linked nodes as pointers
to struct platdata of destination nodes. By doing this, it makes
difficult to get pointer to udevices created based on these
information.

This patch extends dtoc to use struct driver_info when populating
information about linked nodes, which makes it easier to later get
the devices created. In this context, reimplement functions like
clk_get_by_index_platdata() which made use of the previous approach.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09 22:00:29 -06:00
Walter Lozano
addf358bac core: add support for U_BOOT_DRIVER_ALIAS
Currently when using OF_PLATDATA the binding between devices and drivers
is done trying to match the compatible string in the node with a driver
name. However, usually a single driver supports multiple compatible strings
which causes that only devices which its compatible string matches a
driver name get bound.

To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro,
which generates no code at all, but allows an easy way to declare driver
name aliases. Thanks to this, dtoc could be improve to look for the driver
name based on its alias when it populates the U_BOOT_DEVICE entry.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09 18:57:22 -06:00
Walter Lozano
e3e2470fdd drivers: rename drivers to match compatible string
When using OF_PLATDATA, the bind process between devices and drivers
is performed trying to match compatible string with driver names.
However driver names are not strictly defined, and also there are different
names used when declaring a driver with U_BOOT_DRIVER, the name of the
symbol used in the linker list and the used in the struct driver_info.

In order to make things a bit more clear, rename the drivers names. This
will also help for further OF_PLATDATA improvements, such as checking
for valid driver names.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour:
Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-09 18:57:22 -06:00
Amit Singh Tomar
3a21734605 clk: actions: Add Ethernet clocks
This commit adds clocks needed for ethernet operations for
Actions OWL family of SoCs (S700 and S900).

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07 16:09:22 -04:00
Patrick Delaunay
4e62642aef arm: stm32mp: add weak function to save vddcore
Add a weak functions to save the vddcore voltage value provided
in the OPP node when the clock tree is initialized.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Patrick Delaunay
37ad8377af stm32mp1: clk: configure pll1 with OPP
The PLL1 node (st,pll1) is optional in device tree, the max supported
frequency define in OPP node is used when the node is absent.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Sean Anderson
082faeb865 dm: Fix error handling for dev_read_addr_ptr
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-01 15:01:21 +08:00
Sean Anderson
f9c7d4f99f clk: Add K210 clock support
Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. Clocks parameters are stored in
several arrays, and are then instantiated at run-time. There are some
translation macros (FOOIFY()) which allow for more dense packing.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
2020-07-01 15:01:21 +08:00
Sean Anderson
1a198cf886 clk: Add a bypass clock for K210
This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
2020-07-01 15:01:21 +08:00
Sean Anderson
019ef9a3f3 clk: Add K210 pll support
This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
2020-07-01 15:01:21 +08:00
Sean Anderson
675d79073c clk: Fix clk_get_by_* handling of index
clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
predicate instead of the index. Other clk_get_by_* functions got the clock
correctly, but passed a predicate instead of the index to clk_get_by_tail.
This could lead to confusing error messages.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
2020-07-01 15:01:21 +08:00
Sean Anderson
5e8317a9fa clk: Check that ops of composite clock components exist before calling
clk_composite_ops was shared between all devices in the composite clock
driver.  If one clock had a feature (such as supporting set_parent) which
another clock did not, it could call a null pointer dereference.

This patch does three things
1. It adds null-pointer checks to all composite clock functions.
2. It makes clk_composite_ops const and sets its functions at compile-time.
3. It adds some basic sanity checks to num_parents.

The combined effect of these changes is that any of mux, rate, or gate can
be NULL, and composite clocks will still function normally. Previously, at
least mux had to exist, since clk_composite_get_parent was used to
determine the parent for clk_register.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2020-07-01 15:01:21 +08:00
Sean Anderson
78ce0bd3ac clk: Always use the supplied struct clk
CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.

The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks.  This allows child clocks to make calls like clk_get_parent()
without issue.

imx avoided the above problem by using a custom get_rate function with
composite clocks.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2020-07-01 15:01:21 +08:00
Tom Rini
5fdb3c0e7e - net: pcnet: cleanup and add DM support
- Makefile: add rule to build an endian-swapped U-Boot image
   used by MIPS Malta EL variants
 - CI: add Qemu tests for MIPS Malta
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Merge tag 'mips-pull-2020-06-29' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips into next

- net: pcnet: cleanup and add DM support
- Makefile: add rule to build an endian-swapped U-Boot image
  used by MIPS Malta EL variants
- CI: add Qemu tests for MIPS Malta
2020-06-30 11:43:18 -04:00
Alexander Kochetkov
5e15dcb4cb rockchip: clk: rk3188: change APLL to safe 600MHz
The commit 84a6a27ae3 ("rockchip: rk3188: init CPU freq in clock
driver") changed ARM clock from 600MHz to 1600MHz. It made boot
unstable due to the fact that PMIC at the start generates insufficient
voltage for operation. See also: commit f4f57c58b5 ("rockchip:
rk3188: Setup the armclk in spl").

Fixes commit 84a6a27ae3 ("rockchip: rk3188: init CPU freq in clock
driver").

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-27 23:23:00 +08:00
Rajan Vaja
2b2012d1c1 clk: versal: Remove alt_ref_clk from clock sources
alt_ref_clk is applicable only for PS extended version.
For PS base version there is no separate alt_ref_clk.
It is tied with ref_clk, so remove it from driver.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24 13:07:57 +02:00
Pragnesh Patel
1ba43d29eb clk: sifive: fu540-prci: Release ethernet clock reset
U-Boot ethernet works with FSBL flow where releasing ethernet clock
reset is part of FSBL itself but with the SPL, We need to release
ethernet clock reset explicitly for U-Boot proper. With this change
Release ethernet clock reset code in FSBL might not be needed or
unaffected.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
378c7094af clk: sifive: fu540-prci: Add ddr clock initialization
Release ddr clock reset once clock is initialized

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Pragnesh Patel
79e49b081f clk: sifive: fu540-prci: Add clock enable and disable ops
Added clock enable and disable functions in prci ops

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Jagan Teki
e1b413d1a9 clk: rk3399: Enable/Disable TCPHY clocks
Enable/Disable TCPHY clock for rk3399 platform.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 18:08:49 +08:00
Jagan Teki
80e191119e clk: rk3399: Set empty for TCPHY assigned-clocks
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.

  assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
  assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;

So, mark them as empty in clock otherwise device probe on
those typec phy driver would fail.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 18:08:49 +08:00
Jagan Teki
f7dd12a7e7 clk: rk3399: Enable/Disable the USB2PHY clk
Enable/Disable the USB2PHY clk for rk3399.

CLK is clear in enable and set in disable functionality.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 18:08:49 +08:00
Jagan Teki
4648108c63 clk: rk3399: Fix eMMC get_clk reg offset
Actual eMMC get_clk register is clksel_con22 instead of
clksel_con21.

Fix it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 17:58:33 +08:00
Jagan Teki
912f633d01 clk: rk3399: Enable/Disable the PCIEPHY clk
Enable/Disable the PCIEPHY clk for rk3399.

CLK is clear in both enable and disable functionality.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22 20:53:20 +08:00
Jagan Teki
30d09a2f17 clk: rk3399: Add enable/disable clks
Yes, most of the high speed peripheral clocks
in rk3399 enabled by default.

But it would be better to handle them via clk
enable/disable API for handling proper reset
conditions like 'usb reset' over command line.

So, enable USB, GMAC clock via enable/disable ops.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil.m@amarulasolutions.com> # roc-rk3399-pc
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22 20:53:20 +08:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
1af3c7f422 common: Drop linux/stringify.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
eb41d8a1be common: Drop linux/bug.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
25a5818ff8 common: Drop asm/ptrace.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
0914011310 command: Remove the cmd_tbl_t typedef
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.

Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.

This requires quite a few header-file additions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 18:36:55 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
90526e9fba common: Drop net.h from common header
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:31 -04:00
Tom Rini
e2b86e23ce - stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
 - stm32mp1: several board and arch updates
 - stm32mp1: activate data cache in SPL and before relocation
 - Many improvment for AV96 board and DHCOR SoM
   (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
    Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
 - clk: stm32mp1: fix CK_MPU calculation
 - DT alignment of stm32mp1 device tree with Linux 5.7-rc2
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Merge tag 'u-boot-stm32-20200514' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
- stm32mp1: several board and arch updates
- stm32mp1: activate data cache in SPL and before relocation
- Many improvment for AV96 board and DHCOR SoM
  (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
   Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
- clk: stm32mp1: fix CK_MPU calculation
- DT alignment of stm32mp1 device tree with Linux 5.7-rc2
2020-05-14 08:44:06 -04:00
Lionel Debieve
36911fca63 clk: stm32mp1: fix CK_MPU calculation
When the CK_MPU used PLL1_MPUDIV, the current rate is
wrong. The clock must use stm32mp1_mpu_div as a shift
value. Fix the check value used to enter PLL_MPUDIV.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Eugeniy Paltsev
80a7674ef9 CLK: ARC: HSDK: add separate clock map for HSDK-4xD
HSDK and HSDK-4xD clock trees are slightly different.
commit 1dfb2ec0d7 ("ARC: HSDK: CGU: add support for timer clock")
introduce regression for HSDK board cause crash when setting
tunnel clock. Fix that.

Fixes: 1dfb2ec0d7 ("ARC: HSDK: CGU: add support for timer clock")
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:09:27 +03:00
Eugeniy Paltsev
96b2142a54 CLK: ARC: HSDK: define clock map with DT binding constants
Define clock map with DT binding constants so clock map can be
discontinuous.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:09:27 +03:00
Eugeniy Paltsev
c6988688ee CLK: ARC: HSDK: make set_clock optional
We don't want to allow change some clocks, i.e. DDR clock.
So allow to have set_clock to be unset in clock map.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:09:26 +03:00
Eugeniy Paltsev
debfe38445 CLK: ARC: HSDK: prepare for multiple clock maps support
The clock trees of HSDK and HSDK-4xD vary so we need to prepare
CGU driver for multiple clock maps support.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:09:26 +03:00
Eugeniy Paltsev
9b67ebd250 CLK: ARC: HSDK: driver cleanup
Minor code cleanup to improve readability. No functional change intended.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:09:26 +03:00
Eugeniy Paltsev
731f12f382 CLK: ARC: HSDK: use appropriate config data types
* constify clocks config data where is possible
* use more appropriate data types for clocks config

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:09:26 +03:00
Eugeniy Paltsev
5a2706524c CLK: ARC: HSDK: drop unused offset
Drop creg_div_oft offset as it doesn't vary (due to it is used for
CPU PLL only).

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:09:26 +03:00
Eugeniy Paltsev
46d295f362 CLK: ARC: HSDK: avoid code duplication
hsdk_axi_clk_cfg and hsdk_tun_clk_cfg clock divider structures
and functions for their processing are almost the same so
merge them to avoid code duplication.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:09:25 +03:00
Tom Rini
143414c03f i.MX for 2020.07
----------------
 
 - imxrt: fix LCD clock, fix doc
 - new board: Coral Dev
 - imx8: enable Cache in SPL. SNVS, update SCFW API
 - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
 - MX6ULL : is_imx6ull to include i.MX6ULZ
 - Net: add config to enable TXC delay
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
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Merge tag 'u-boot-imx-20200502' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.07
----------------

- imxrt: fix LCD clock, fix doc
- new board: Coral Dev
- imx8: enable Cache in SPL. SNVS, update SCFW API
- imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
- MX6ULL : is_imx6ull to include i.MX6ULZ
- Net: add config to enable TXC delay

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
2020-05-04 09:29:42 -04:00
Tom Rini
04da42770b Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- dts clean up to use -u-boot for px30, rk3399 boards
- dts sycn from upstream kernel for rk3328, rk3399
- add rockchip rng driver
- new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
2020-05-04 07:28:14 -04:00
Giulio Benetti
ea0f768e2c clk: imx: clk-imxrt1050: fix lcdif clock gate
LCDIF clock gate was wrong so set it according to RM.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01 19:03:25 +02:00
Jagan Teki
96993d7c35 clk: rk3399: Set empty for HCLK_SD assigned-clocks
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have HCLK_SD assigned-clocks which are usually required for
Linux and don't require to handle them in U-Boot.

 assigned-clocks = <&cru HCLK_SD>;

So, mark them as empty in clock otherwise device probe on
those SD controllers would fail.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Tom Rini
6d7dacf726 Xilinx changes for v2020.07-rc2
mmc:
 - Fix dt property handling via generic function
 
 clk:
 - Fix versal watchdog clock setting
 
 nand:
 - Fix zynq nand command comparison
 
 xilinx:
 - Enable ubifs
 - Sync board_late_init configurations with initrd_high setup
 - Make custom distro boot more verbose
 
 zynq:
 - Kconfig alignments
 - Fix nand cse configuration
 
 zynqmp:
 - Fix zcu104 low level qspi configuration
 - Small DT updates
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Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2020.07-rc2

mmc:
- Fix dt property handling via generic function

clk:
- Fix versal watchdog clock setting

nand:
- Fix zynq nand command comparison

xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose

zynq:
- Kconfig alignments
- Fix nand cse configuration

zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-30 11:34:01 -04:00
Tom Rini
221c4d9826 - fix sd-emmc controller A init on G12A/G12B/SM1 SoCs
- add GXBB USB PHY driver
 - enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards
 - fix USB PHYs Power-Up on on VIM3/VIM3L boards
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Merge tag 'u-boot-amlogic-20200428' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- fix sd-emmc controller A init on G12A/G12B/SM1 SoCs
- add GXBB USB PHY driver
- enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards
- fix USB PHYs Power-Up on on VIM3/VIM3L boards
2020-04-28 10:09:16 -04:00
Neil Armstrong
75dcc2d484 clk: meson: g12a: add missing SD_EMMC_A controller gates
Add missing SD_EMMC_A controller gates needed for probe of the A
controller, otherwise leading to a freeze of the SoC after b3d69aa596.

Fixes: b3d69aa596 ("clk: meson: reset mmc clock on probe")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-28 10:23:10 +02:00
T Karthik Reddy
7eab624baf clk: versal: Fix watchdog clock issue
Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt
driver. Skip reading clock rate for the mux based clocks with
parent clock id is zero.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
2020-04-27 13:57:17 +02:00
Eugeniy Paltsev
1dfb2ec0d7 ARC: HSDK: CGU: add support for timer clock
Add support for additional timer clock which belongs to tunnel
domain.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:25 +03:00
Amit Singh Tomar
8b520ac153 clk: actions: Add common clock driver
This patch converts S900 clock driver to something common that can
be used for other SoCs, for instance S700(few of clk registers are same).

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
4939beea8e arm: dts: sync dts for Action Semi S900
Synchronize device tree bindings with v5.5-rc6 tag with commit id
"b3a987b0264d".

Also, it removes older clock binding defined for S900 along with undocumented
compatible string "actions,s900-serial" from serial driver and adapts clock
driver to cater to new bindings.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Marek Behún
239f424f49 clk: armada-37xx-periph: fix DDR PHY clock divider values
Register value table for DDR PHY clock divider are wrong. They should be
0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current
values do not make sense, since 2 cannot be achieved, because the
register is only 1 bit long (mask is set to 1).

This fixes clk dump reporting DDR PHY clock rate differently from Linux.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Giulio Benetti
ac4e7610da clk: imx: add i.IMXRT1020 clk driver
Add i.MXRT1020 clk driver support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-04-18 14:54:28 +02:00
Giulio Benetti
ecd8497bcb clk: imx: clk-imxrt1050: add set_parent() callback
Need to add set_parent() callback to allow dts assigned-clock-parents to
work so let's add it accordingly.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-04-18 12:54:43 +02:00
Giulio Benetti
caac71b725 clk: imx: clk-imxrt1050: setup PLL5 for video in non-SPL
mxsfb needs PLL5 as source, so let's setup it at its default frequency
specified in RM(650Mhz).

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-04-18 12:54:43 +02:00
Giulio Benetti
d303f9c356 clk: imx: clk-imxrt1050: fix typo in clock name "video:"
"video:" must be "video", ":" is a typo.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-04-18 12:54:43 +02:00
Giulio Benetti
8cefbe98b1 clk: imx: pllv3: add enable_bit
pllv3 PLLs have powerdown/up bits but enable bits too. Specifically
"enable bit" enable the pll output, so when dis/enabling pll by
setting/clearing power_bit we must also set/clear enable_bit.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-04-18 12:54:43 +02:00
Tom Rini
0f238dab6d Merge tag 'arc-fixes-for-2020.07-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc
This is pretty minor set of changes mostly touching HSDK board:

 * Enable on-chip reset controller on HSDK
 * Add possibility to turn-on & off L2$ on more
   recent ARC HS processors.
 * AXI tunnel clock calculation on HSDK
2020-04-16 17:14:44 -04:00
Eugeniy Paltsev
7b50db8242 ARC: HSDK: CGU: fix tunnel clock calculation
We set wrong tunnel PLL frequency when we request 125MHz tunnel clock.
Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-16 23:37:10 +03:00
Patrick Delaunay
5c9c9bc957 dm: core: remove the duplicated function dm_ofnode_pre_reloc
The content dm_ofnode_pre_reloc() is identical with ofnode_pre_reloc()
defined in drivers/core/ofnode.c and used only three times:
- drivers/core/lists.c:lists_bind_fdt()
- drivers/clk/at91/pmc.c::at91_clk_sub_device_bind
- drivers/clk/altera/clk-arria10.c::socfpga_a10_clk_bind

So this function dm_ofnode_pre_reloc can be removed and replaced
by these function calls by ofnode_pre_reloc().

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2020-04-16 08:07:58 -06:00
Patrick Delaunay
654706be84 configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOT
Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp
specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT
introduced by the commit 535d76a121 ("armv8: layerscape: Add TFABOOT
support").
This config CONFIG_TFABOOT is activated for the trusted boot chain,
when U-Boot is loaded by TF-A.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-04-15 09:08:37 +02:00
Tom Rini
8914831860 Merge branch 'next'
Pull in changes that have been pending in our 'next' branch.  This
includes:
- A large number of CI improvements including moving to gcc-9.2 for all
  platforms.
- amlogic, xilinx, stm32, TI SoC updates
- USB and i2c subsystem updtaes
- Re-sync Kbuild/etc logic with v4.19 of the Linux kernel.
- RSA key handling improvements
2020-04-13 11:27:00 -04:00
Tom Rini
1ebf50d9bb - clk: meson-g12a: missing break
- sync all Amlogic DT from Linux v5.6-rc2
 - MMC clock fixups
 - add support for Libre Computer AML-S905D-PC and AML-S912-PC
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Merge tag 'u-boot-amlogic-20200406' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic into next

- clk: meson-g12a: missing break
- sync all Amlogic DT from Linux v5.6-rc2
- MMC clock fixups
- add support for Libre Computer AML-S905D-PC and AML-S912-PC
2020-04-08 08:48:31 -04:00
Tom Rini
1f47e2aca4 Xilinx changes for v2020.07
common:
 - Align ENV_FAT_INTERFACE
 - Fix MAC address source print log
 - Improve based autodetection code
 
 xilinx:
 - Enable netconsole
 
 Microblaze:
 - Setup default ENV_OFFSET/ENV_SECT_SIZE
 
 Zynq:
 - Multiple DT updates/fixes
 - Use DEVICE_TREE environment variable for DTB selection
 - Switch to single zynq configuration
 - Enable NOR flash via DM
 - Minor SPL print removal
 - Enable i2c mux driver
 
 ZynqMP:
 - Print multiboot register
 - Enable cache commands in mini mtest
 - Multiple DT updates/fixes
 - Fix firmware probing when driver is not enabled
 - Specify 3rd backup RAM boot mode in SPL
 - Add SPL support for zcu102 v1.1 and zcu111 revA
 - Redesign debug uart enabling and psu_init delay
 - Enable full u-boot run from EL3
 - Enable u-boot.itb generation without ATF with U-Boot in EL3
 
 Versal:
 - Enable distro default
 - Enable others SPI flashes
 - Enable systems without DDR
 
 Drivers:
 - Gem:
   - Flush memory after freeing
   - Handle mdio bus separately
 - Watchdog:
   - Get rid of unused global data pointer
   - Enable window watchdog timer
 - Serial:
   - Change reinitialization logic in zynq serial driver
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Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2020.07

common:
- Align ENV_FAT_INTERFACE
- Fix MAC address source print log
- Improve based autodetection code

xilinx:
- Enable netconsole

Microblaze:
- Setup default ENV_OFFSET/ENV_SECT_SIZE

Zynq:
- Multiple DT updates/fixes
- Use DEVICE_TREE environment variable for DTB selection
- Switch to single zynq configuration
- Enable NOR flash via DM
- Minor SPL print removal
- Enable i2c mux driver

ZynqMP:
- Print multiboot register
- Enable cache commands in mini mtest
- Multiple DT updates/fixes
- Fix firmware probing when driver is not enabled
- Specify 3rd backup RAM boot mode in SPL
- Add SPL support for zcu102 v1.1 and zcu111 revA
- Redesign debug uart enabling and psu_init delay
- Enable full u-boot run from EL3
- Enable u-boot.itb generation without ATF with U-Boot in EL3

Versal:
- Enable distro default
- Enable others SPI flashes
- Enable systems without DDR

Drivers:
- Gem:
  - Flush memory after freeing
  - Handle mdio bus separately
- Watchdog:
  - Get rid of unused global data pointer
  - Enable window watchdog timer
- Serial:
  - Change reinitialization logic in zynq serial driver

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-07 17:13:35 -04:00
Jerome Brunet
b3d69aa596 clk: meson: reset mmc clock on probe
On some SoCs, depending on the boot device, the MMC clock block may be
left in a weird state by the ROM code, in which no decent clock may be
provided. Reset the related register to make sure a sane MMC clock is
ready for the controller.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06 09:56:35 +02:00
Heinrich Schuchardt
87a8f96759 clk: meson-g12a: missing break
Add missing break for CLKID_PCIE_PLL in switch statement.

Reported by CppCheck.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Fixes: 08e09c263f ("clk: meson-g12a: Add PCIE PLL support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06 09:56:35 +02:00
Chee Hong Ang
32d630fc1d clk: socfpga: Read the clock parent's register base in probe function
This commit (82de42fa14) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because the
parent clocks will only be probed after the child's ofdata_to_platdata().
To resolve this, the clock parent's register base will only be retrieved
by the child in probe() method instead of ofdata_to_platdata().

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-05 19:07:13 -04:00
Jagan Teki
b1bcd61665 clk: rk3399: Set empty for vopl assigned-clocks
During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.

But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.

So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-02 15:44:56 +02:00
Marek Vasut
061ef41fcf clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2
The fdtdec_get_addr() does not take into account values set in #address-cells
and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit
systems. This is true for most DTs, however there are exceptions. Switch to
fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells
values into consideration, otherwise the reset controller node register
offset is incorrectly parsed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-30 03:49:23 +02:00
Patrick Delaunay
0c90e0cf63 clk: stm32mp1: add SPI5_K support
Add clock support for SPI5, as this instance is available on extension
connector of ST board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:18:09 +01:00
Patrick Delaunay
69ffb5577a clk: stm32mp1: correct CKSELR masks
Correct three masks used to access on the RCC register
RCC_QSPICKSELR, RCC_FMCCKSELR and RCC_ADCCKSELR: only 3 bits.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:18:09 +01:00
Heinrich Schuchardt
38a2a48cd9 x86: remove dead code in intel_clk_get_rate()
If all branches of a switch statement have a return instruction, all
subsequent lines are unreachable.

Identified with cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-05 18:19:40 +08:00
Rajan Vaja
65bcca9f52 versal: drivers: clk: Fix invalid clock name queries
The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling versal_pm_clock_get_name() in versal_get_clock_info() function.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-28 12:04:10 +01:00
Tom Rini
f2a73d6867 - add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
 - fix STM32 image format for big endian hosts in mkimage
 - solve warnings in device tree and code for stm32mp1 boards
 - remove fdt_high and initrd_high for stm32 and stih boards
 - add support of STM32MP15x Rev.Z
 - update stm32mp1 readme
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Merge tag 'u-boot-stm32-20200214' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme
2020-02-14 07:31:47 -05:00
Patrick Delaunay
eb49dce0d8 clk: stm32mp1: solve type issue in stm32mp1_lse_enable and stm32mp1_clktree
Solve type issue in stm32mp1_lse_enable and stm32mp1_clktree.

This patch solves the warnings when compiling with W=1
on stm32mp1 board:

clk_stm32mp1.c: In function ‘stm32mp1_lse_enable’:
clk_stm32mp1.c:1238:15: warning: comparison of integer expressions
  of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
  [-Wsign-compare]
clk_stm32mp1.c:1239:13: warning: comparison of integer expressions
  of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
  [-Wsign-compare]

clk_stm32mp1.c: In function ‘stm32mp1_clktree’:
clk_stm32mp1.c:1814:17: warning: comparison of integer expressions
  of different signedness: ‘int’ and ‘unsigned int’
  [-Wsign-compare]

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-13 18:47:00 +01:00
Eugeniy Paltsev
defd1e71d0 CLK: HSDK: fix HDMI clock calculation
HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-02-12 20:47:39 +03:00
Eugeniy Paltsev
b8f3ce0137 CLK: HSDK: Check for PLL bypass firstly
Pll bypass has priority over enable/disable.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-02-12 20:47:14 +03:00
Tom Rini
9a8942b53d sandbox conversion to SDL2
TPM TEE driver
 Various minor sandbox video enhancements
 New driver model core utility functions
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Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
2020-02-11 10:58:41 -05:00
Simon Glass
b4d00b256e x86: Add a clock driver for Intel devices
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.

This driver can be expanded later as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07 22:41:24 +08:00
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
61b29b8268 dm: core: Require users of devres to include the header
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Simon Glass
fb8c0d595f clk: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Jagan Teki
b52a199e32 arm: rockchip: Add common cru.h
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.

So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.

The rest of rockchip cru files will add it in future.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-30 11:44:01 +08:00
Giulio Benetti
041b06a7c3 clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26 21:57:08 +01:00
Giulio Benetti
d37ecaba88 clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()
Guard 'mfd==0' to prevent 'divide by zero' issue in
clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd
should never be 0 at all.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26 21:57:08 +01:00
Giulio Benetti
3391e77729 clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26 21:57:08 +01:00
Sean Anderson
90cbfa50c2 clk: Fix error checking of dev_read_addr_ptr
dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-01-26 12:03:06 +01:00
Giulio Benetti
efbdad3838 clk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA is enabled
clk_get_by_name() requires clk_get_by_id() that is not available if
CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else
condition of #if CONFIG_IS_ENABLED(OF_PLATDATA).

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26 12:03:06 +01:00
Peng Fan
5dcac2b9b3 clk: show more error info when uclass_get_device_by_name
It will ease debug when uclass_get_device_by_name failed with
more error info printed out.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-26 12:03:06 +01:00
Fabien Parent
832685f07c clk: mediatek: use unsigned type for returning the clk rate
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.

This commit change the return type of mtk_clk_find_parent_rate to
ulong.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2020-01-26 12:03:06 +01:00
Tom Rini
07add22cab Merge tag '2020-01-20-ti-2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
K3 J721E:
* DMA support.
* MMC and ADMA support.
* EEPROM support.
* J721e High Security EVM support.
* USB DT nodes

K3 AM654:
* Fixed boot due to pmic probe error.
* USB support and DT nodes.
* ADMA support

DRA7xx/AM57xx:
* BBAI board support
* Clean up of net platform code under board/ti

AM33/AM43/Davinci:
* Reduce SPL size for omap3 boards.
* SPL DT support for da850-lcdk
* PLL divider fix for AM335x
2020-01-20 14:54:55 -05:00
Lokesh Vutla
ea67b26e3f clk: sci-clk: add slack to clk-set-rate passed to firmware
Add slack to the clock frequency parameters passed to firmware within
clk_set_rate. min-freq is changed to 0 and max-rate is changed to
ULONG_MAX. This fixes certain issues with pll clock rounding when the
firmware is not able to set the frequency exactly to the target, the
current implementation fails if the available frequency is even 1Hz off
the target. With the change, the firmware still tries its best to set
the frequency as close as possible to the target.

Reported-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:29 +05:30
Simon Glass
049f8d6f4a common: Move get_tbclk() to time.h
This function related to timer and most of the timer functions are in
time.h, so move this function there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:27:30 -05:00
Simon Glass
d96c26040e common: Move clock functions into a new file
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:27:29 -05:00
Sam Shih
d8588ba55f clk: mediatek: fix clock-rate overflow problem
This patch fix clock-rate overflow problem in mediatek
clock driver common part.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Sam Shih
72ab603b20 clk: mediatek: add driver for MT7622
This patch add clock driver for MediaTek MT7622 SoC.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
6bf6d81c11 clk: fixed_rate: add dummy enable() function
This is used to avoid clk_enable() return -ENOSYS.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
d646420e29 clk: add APIs to get (optional) clock by name without a device
Sometimes we may need get (optional) clock without a device,
that means use ofnode.
e.g. when the phy node has subnode, and there is no device created
for subnode, in this case, we need these new APIs to get subnode's
clock.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
bd7c798605 clk: check valid clock by clk_valid()
Add valid check for clk->dev, it's useful when get optional
clock even when the clk point is valid, but its dev will be
NULL.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
0f9b2b3ddf clk: fix error check for devm_clk_get_optional()
If skip all return error number, it may skip some real error cases,
so only skip the error when the clock is not provided in DTS

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
5f82a940a0 clk: mediatek: mt7629: add support for ssusbsys
The SSUSB IP's clocks come from ssusbsys module on mt7629,
so add its driver

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
mingming lee
0670adb27a clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
2020-01-16 09:39:45 -05:00
mingming lee
f62168d3c3 clk: mediatek: add set_clr_upd mux type flow
Add new set_clr_upd mux type and related operation to
mtk common clock driver to support mt8512
2020-01-16 09:39:45 -05:00
mingming lee
c196110777 clk: mediatek: add driver support for MT8512
Add clock driver for MediaTek MT8512 SoC, include topckgen,
apmixedsys and infracfg support.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Giulio Benetti
4ca28e98ac clk: imx: add i.IMXRT1050 clk driver
Add i.MXRT1050 clk driver support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Giulio Benetti
824c371f9b clk: imx: pfd: add set_rate()
Implement set_rate() for pfd.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
efadf790f3 clk: imx: pllv3: add support for PLLV3_AV type
Add support for PLLV3 AV type.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Giulio Benetti
d0ceb93547 clk: imx: pllv3: add PLLV3_SYS support
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
generic enable()/disable(). Add a different driver because ops are
different respect to GENERIC/USB.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
9841fee581 clk: imx: pllv3: add set_rate() support
Add generic set_rate() support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
cbb20014a3 clk: imx: pllv3: add disable() support
Add disable() support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
f4b7094250 clk: imx: pllv3: add enable() support
Before set_rate() pllv3 needs enable() to power the pll up.
Add enable() taking into account different power_bit and
different powerup_set, because some pll needs its power_bit to be
set or reset to be powered on.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Giulio Benetti
4abd8076c8 clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB
div_mask is different for GENERIC and USB pll, so set it according.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
16faa599e6 clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks
Better to register the 2 clock as 2 different drivers because they work
slightly differently depending on power_bit and powerup_set bits coming
on next patches.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Anatolij Gustschin
f35237e1e4 clk: imx8qxp: extend to support getting I2C IPG clock
Since commit d02be21d30 ("i2c: imx_lpi2c: add ipg clk") getting
I2C clocks doesn't work. Add I2C IPG clock IDs to related switch
statements to fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-14 22:48:37 +01:00
Tom Rini
c00bd81ae0 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xx
- A small PR with MC8309 fixes from Rasmus.
2020-01-09 13:42:43 -05:00
Tom Rini
d6b92b9742 dm: Increased separation of ofdata_to_platdata() and probe methods
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Merge tag 'dm-pull-8jan20' of git://git.denx.de/u-boot-dm

dm: Increased separation of ofdata_to_platdata() and probe methods
2020-01-09 08:52:21 -05:00
Tom Rini
7086de4948 Pull request for UEFI sub-system for efi-2020-04-rc1
This pull request provides:
 
 * support for FIT images for UEFI binaries
 * drivers for hardware random number generators
 * an implementation of the EFI_RNG_PROTOCOL
 * a sub-command for efidebug to display configuration tables
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Merge tag 'efi-2020-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-04-rc1

This pull request provides:

* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
2020-01-08 18:57:11 -05:00
Tom Rini
deb287b561 ---------------------------------------------------------------------
Add i.MX8MP SoC and EVK board
 Update README for i.MX8MN EVK and fix mmc env
 Add pca9450 driver
 --------------------------------------------------------------------
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
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Merge tag 'u-boot-imx-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

---------------------------------------------------------------------
Add i.MX8MP SoC and EVK board
Update README for i.MX8MN EVK and fix mmc env
Add pca9450 driver
--------------------------------------------------------------------

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
2020-01-08 15:24:50 -05:00
Peng Fan
c4cc283498 clk: imx: add i.MX8MP clk driver
Add i.MX8MP clk driver for i.MX8MP CLK driver model usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08 13:20:09 +01:00
Peng Fan
6ddde48b49 clk: imx: add imx_clk_mux2_flags
Add imx_clk_mux2_flags which will be used by i.MX8MP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08 13:20:09 +01:00
Rasmus Villemoes
fddf876a8f mpc83xx_clk: always treat MPC83XX_CLK_PCI as invalid
The current mpc83xx_clk driver is broken for any board for which
mpc83xx_has_pci() is true, i.e. anything not MPC8308:

When is_clk_valid() reports that MPC83XX_CLK_PCI is valid,
init_all_clks() proceeds to call init_single_clk(), but that doesn't
know about either MPC83XX_CLK_PCI or has any handling of the
TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence
init_single_clk() ends up returning -EINVAL, and the whole board hangs
in serial_init().

The quickest fix is to simply pretend that clock is invalid for
all, since nobody can have been relying on it. Adding proper support
seems to be a bit more involved than just handling TYPE_SCCR_ONOFF:

- The power-on-reset value of SCCR[PCICM] is 0, so
  mpc83xx_clk_enable() would probably need to be tought to enable the
  clock.

- The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2
  depending on the CFG_CLKIN_DIV configuration input, but that can't
  be read from software, so to properly fill out
  ->speed[MPC83XX_CLK_PCI] I think one would need guidance from
  Kconfig or dtb.

Partially fixes: 07d538d281 clk: Add MPC83xx clock driver

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
2020-01-08 08:14:36 +01:00
Simon Glass
b2b1100a3b aspeed: ast2500: Read clock ofdata in the correct method
At present the clock driver reads its ofdata in the probe() method. This
is not correct although it is often harmless.

However in this case it causes a problem, something like this:

- ast_get_scu() is called (from somewhere) to get the SCI address
- this probes the clock
   - first sets up ofdata (which does nothing at present)
   - DM marks clock device as active
   - DM calls pinctrl
      - pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe()
      - ast_get_scu() probes the clock, but sees it already marked as
           probed
      - ast_get_scu() accesses the clock's private data, with scu as NULL
   - DM calls clock probe function ast2500_clk_probe() which reads scu

By putting the read of scu into the correct method, scu is read as part of
ofdata setup, and everything is OK.

Note: This problem did not matter until now since DM always probed all
parents before reading a child's ofdata. The fact that pinctrl is a child
of clock seems to trigger this strange bug.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-01-07 16:02:38 -07:00
Sughosh Ganu
82ebf0f6a0 clk: stm32mp1: Add a clock entry for RNG1 device
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07 18:08:21 +01:00
Ley Foon Tan
c168fc71a3 clk: agilex: Add clock driver for Agilex
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Tom Rini
2f02845817 Fixes for 2020.01
-----------------
 
 - imx8qxp_mek: increase buffer sizes and args number
 - Fixes for imx7ulp
 - imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
 - colibri_imx7: reserve DDR memory for Cortex-M4
 - vining2000: fixes and convert to ethernet DM
 - imx8m: fix rom version check to unbreak some B0 chips
 - tbs2910: Disable VxWorks image booting support
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Merge tag 'u-boot-imx-20191209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.01
-----------------

- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
2019-12-09 10:32:08 -05:00
Frieder Schrempf
f5edb0d86d clk: imx: imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
The 24MHz oscillator clock is referenced by "clock-osc-24m" and not
"osc_24m".

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-12-06 13:57:42 +01:00
mingming lee
9072400775 clk: mediatek: add driver for MT8518
Add clock driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
Simon Glass
1045315df0 common: Move get_ticks() function out of common.h
This function belongs in time.h so move it over and add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
2189d5f1e8 Move strtomhz() to vsprintf.h
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.

Use the vsprintf.h include file explicitly where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:09 -05:00
Finley Xiao
fe9efbca7b rockchip: clk: Add clk driver for rk3308
Add clk controller driver for RK3308 SOC.

This patch depends on Elaine's pll patch[0].

[0]http://patchwork.ozlabs.org/patch/1183718/

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Elaine Zhang
bbda2ed584 rockchip: clk: pll: add common pll setting funcs
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Heiko Stuebner
a5ada25e42 rockchip: clk: fix wrong CONFIG_IS_ENABLED handling
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so
without the leading CONFIG_. The clock drivers all wrongly check for
CONFIG_RESET_ROCKCHIP, fix that

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Heiko Stuebner
a04f6fd17f rockchip: clk: rv1108: remove duplicate reset init
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.

So we can get rid of the open-coded reset init and just fix
the correct cru reference.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
d49a526750 rockchip: clk: add px30 clock driver
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:07 +08:00
Tom Rini
5f7ff6d63e u-boot-imx-20191105
-------------------
 i.MX8MN SoC support
 ROM API image download support
 i.MX8MM enet enabling
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Merge tag 'u-boot-imx-20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191105
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
2019-11-12 07:18:23 -05:00
Tom Rini
086e391bc4 Merge tag 'u-boot-rockchip-20191110' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
2019-11-11 14:19:32 -05:00
Simon South
2cbdb6e051 clk: rockchip: rk3328: Configure CPU clock
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.

Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Keerthy
e0aa873bc7 clk: clk-ti-sci: Notify AVS driver upon setting clock rate
Notify AVS driver upon setting clock rate so that voltage
is changed accordingly.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Peng Fan
ddf66d2159 clk: imx: imx8mm: add set_parent callback
Add set_parent callback, then assigned-clock-parents in dts could
be work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05 10:27:18 +01:00
Peng Fan
3bdd558737 clk: imx8mm: add enet clk
Add enet ref/timer/PHY_REF/root clk which are required to make enet
function well.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05 10:27:18 +01:00
Peng Fan
a3aff5e5f3 clk: imx: add i.MX8MN ccf driver
Add i.MX8MM ccf driver support.
Modifed from Linux Kernel 5.3.0-rc1, drop some entries
that not used in U-Boot and adapt to U-Boot CCF style.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Lukasz Majewski <lukma@denx.de>
2019-11-05 10:27:18 +01:00
Tom Rini
412326d1bc Merge tag 'u-boot-clk-23Oct2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Add I2C clocks for i.MX6Q CCF driver
- Fix check in clk_set_default_parents()
- Managed API to get clock from device tree
- Fixes for core clock code (including sandbox regression tests)
2019-10-30 13:13:46 -04:00
Tom Rini
ffc379b42c - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
 - mtmips: add new drivers for clock, reset-controller and pinctrl
 - mtmips: add support for high speed UART
 - mtmips: update/enhance drivers for SPI and ethernet
 - mtmips: add support for MMC
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Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips

- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
2019-10-25 20:07:24 -04:00
Weijie Gao
77ed3c42fe clk: add clock driver for MediaTek MT76x8 platform
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Michal Simek
039c740d66 arm64: zynqmp: Switch to xlnx-zynqmp-clk header
Use prepared header instead of hardcoded values.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
6596270ecb arm64: versal: Rename versal_pm_request to xilinx_pm_request
Use generic name instead of Versal specific because this should be also
used on ZynqMP.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Michal Simek
0f3604a2b3 arm64: versal: Clean pm_api_id usage
Copy enum values from platform code to firmware code. IDs are shared
between ZynqMP and Versal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Jean-Jacques Hiblot
9a52be129c test: clk: test clock self assignment
Make sure that the clock self-assignment works by having a clock of
clk-sbox be configured automatically when clk-sbox is probed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
fd1ba29652 drivers: clk: Fix using assigned-clocks in the node of the clock it sets up
This fixes the case where assigned-clocks is used to define a clock
defaults inside this same clock's node. This is used sometimes to setup a
default parents and/or rate for a clock.

example:
muxed_clock: muxed_clock {
	clocks = <&clk_provider 0>, <&clk_provider 1>;
	#clock-cells = <0>;
	assigned-clocks = <&muxed_clock>;
	assigned-clock-parents = <&clk_provider 1>;
};

It doesn't work in u-boot because the assigned-clocks are setup *before*
the clock is probed. (clk_set_parent() will likely crash or fail if called
before the device probe function)
Making it work by handling "assigned-clocks" in 2 steps: first before the
clk device is probed, and then after the clk device is probed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
dd2e0ce2a4 test: clk: Update tests to also check the managed API
Add a few more clocks the clk_sandbox clock provider and get them using
the managed API.
Make sure they are released when the device is removed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
52720c536f drivers: clk: Add a managed API to get clocks from the device-tree
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the
device-tree. The clocks is automatically released and the data structure
freed when the device is unbound.
Also add devm_clk_put() to release the clock and free the data structure
manually.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
8a1661f20e drivers: clk: Handle gracefully NULL pointers
Prepare the way for a managed CLK API by handling NULL pointers without
crashing nor failing.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Lukasz Majewski
727fa4539c clk: Add support for I2C clocks on NXP's imx6q SoC which use CCF
This change adds support for I2C clock modeled in CCF. This code intention
is to only enable those clocks in the I2C driver with default settings.
For that reason the "busy" versions of clocks reuse the generic approach
and would need to be updated when one wants to adjust the I2C clock
frequency in U-Boot.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
02e2a2ad2f clk: Fix error check in clk_set_default_parents()
According to the documentation in clk.h, clk_set_parent() return the new
rate of the clock or a negative error code.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Neil Armstrong
2168a52e2b clk: meson-sm1: add compatible
The SM1 clock controller is almost identical to the G12A and
so far the differences don't matter.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18 14:26:59 +02:00
Neil Armstrong
a0513b40cc clk: meson: g12a: add support for VPU/HDMI clocks
Add necessary clock support to set up clock for the VPU and
HDMI support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 10:46:08 +02:00
Tero Kristo
260777fc23 clk: cdce9xx: add support for cdce9xx clock synthesizer
Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11 13:32:39 -04:00
Tom Rini
44fb0d6c9f Xilinx/FPGA changes for v2020.01
FPGA:
 - Enable fpga loading on Versal
 - Minor fix
 
 Microblaze:
 - Fix LMB configurations to support initrds
 - Some other cleanups
 
 Zynq:
 - Minor config/dt changes
 - Add distro boot support for usb1 and mmc1
 - Remove Xilinx private boot commands and use only distro boot
 
 ZynqMP:
 - Kconfig cleanups, defconfig updates
 - Update some dt files
 - Add firmware driver for talking to PMUFW
 - Extend distro boot support for jtag
 - Add new IDs
 - Add system controller configurations
 - Convert code to talk firmware via mailbox or SMCs
 
 Versal:
 - Add board_late_init()
 - Add run time DT memory setup
 - Add DFU support
 - Extend distro boot support for jtag and dfu
 - Add clock driver
 - Tune mini configurations
 
 Xilinx:
 - Improve documentation (boot scripts, dt binding)
 - Enable run time initrd_high calculation
 - Define default SYS_PROMPT
 - Add zynq/zynqmp virtual defconfig
 
 Drivers:
 - Add Xilinx mailbox driver for talking to firmware
 - Clean zynq_gem for Versal
 - Move ZYNQ_HISPD_BROKEN to Kconfig
 - Wire genphy_init() in phy.c
 - Add Xilinx gii2rgmii bridge
 - Cleanup zynq_sdhci
 - dwc3 fix
 - zynq_gpio fix
 - axi_emac fix
 
 Others:
 - apalis-tk1 - clean config file
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Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.01

FPGA:
- Enable fpga loading on Versal
- Minor fix

Microblaze:
- Fix LMB configurations to support initrds
- Some other cleanups

Zynq:
- Minor config/dt changes
- Add distro boot support for usb1 and mmc1
- Remove Xilinx private boot commands and use only distro boot

ZynqMP:
- Kconfig cleanups, defconfig updates
- Update some dt files
- Add firmware driver for talking to PMUFW
- Extend distro boot support for jtag
- Add new IDs
- Add system controller configurations
- Convert code to talk firmware via mailbox or SMCs

Versal:
- Add board_late_init()
- Add run time DT memory setup
- Add DFU support
- Extend distro boot support for jtag and dfu
- Add clock driver
- Tune mini configurations

Xilinx:
- Improve documentation (boot scripts, dt binding)
- Enable run time initrd_high calculation
- Define default SYS_PROMPT
- Add zynq/zynqmp virtual defconfig

Drivers:
- Add Xilinx mailbox driver for talking to firmware
- Clean zynq_gem for Versal
- Move ZYNQ_HISPD_BROKEN to Kconfig
- Wire genphy_init() in phy.c
- Add Xilinx gii2rgmii bridge
- Cleanup zynq_sdhci
- dwc3 fix
- zynq_gpio fix
- axi_emac fix

Others:
- apalis-tk1 - clean config file
2019-10-09 16:22:03 -04:00
Siva Durga Prasad Paladugu
95105089af clk: versal: Add clock driver support
This patch adds clock driver support for Versal platform. The clock driver
queries and performs clock operations using PLM firmware by communicating
with it using SMC calls.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:41:24 +02:00
Rajan Vaja
14723ed544 zynqmp: firmware: Add Xilinx ZynqMP firmware driver
Add simple ZynqMP firmware drive to populate child nodes under
zynqmp_firmware DT node.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:11:14 +02:00
Tudor Ambarus
b96b175cbb ARM: at91: Rename sama5_sfr.h to at91_sfr.h
The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-10-08 09:16:11 +03:00
Kever Yang
445f85fc8e rockchip: clk: rk3399: remove clk_enable()
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
7be113ba79 rockchip: clk: rk3368: remove clk_enable()
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
899c3b3523 rockchip: clk: rk3328: remove clk_enable()
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Kever Yang
c7ed19047e rockchip: clk: rk3288: remove clk_enable()
There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11 16:16:12 +08:00
Eddie James
38c9f08b41 clk: aspeed: Add support for SD clock
Add code to enable the SD clock on the ast2500 SoC.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-05 15:27:31 +08:00
Tom Rini
80505e59df - add missing g12b clock driver compatible, fixing odroid-n2 usb support
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Merge tag 'u-boot-amlogic-20190828' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- add missing g12b clock driver compatible, fixing odroid-n2 usb support
2019-08-29 07:25:48 -04:00
Mark Kettenis
d0e8c4ad51 clk: meson-g12b: add compatible
The G12B clock controller is almost identical to the G12A and
so far the differences don't matter.  Adding the G12B compatible
makes USB work on the Odroid-N2.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-28 10:14:31 +02:00
Patrick Delaunay
4de076ed09 stm32mp1: clk: use gd to store frequency information
Use existing gd structure to store frequency information
which can be used in drivers or arch without new request.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Patrick Delaunay
7879a7d09c stm32mp1: clk: remove debug traces
Remove many debug trace.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27 11:19:23 +02:00
Adam Ford
a074667d52 Kconfig: Varios: Fix more SPL, TPL dependencies
Several options are presenting themselves on a various boards
where the options are clearly not used.  (ie, SPL/TPL options
when SPL or TPL are not defined)

This patch is not attempting to be a complete list of items, but
more like low hanging fruit.  In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.

This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-26 11:46:29 -04:00
Tom Rini
50b4b80f59 Merge tag 'u-boot-rockchip-20190823' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- remove rk3288 fennec board
- remove SPL raw image support for Rockchip SoCs
- add common misc_init_r() for ethaddr from cpuid
- enable USB HOST support for rk3328
- unify code for finding a valid gpt in part driver
2019-08-24 08:33:27 -04:00
Kever Yang
2fcff365e0 rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0
Required to successfully probe the ehci generic driver

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23 15:27:40 +08:00
Peng Fan
f62ec5c4bb clk: imx: add i.MX8MM clk driver
Add i.MX8MM clk driver support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22 00:10:15 +02:00
Peng Fan
543fdc2a16 clk: imx: add i.MX8M composite clk support
Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22 00:10:14 +02:00
Peng Fan
bbb5871b8d clk: imx: add pll14xx driver
Add pll14xx driver for i.MX8MM usage, modifed
from Linux Kernel 5.3.0-rc1

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22 00:10:14 +02:00
Peng Fan
ccab06689a clk: imx: expose CCF entry for all
Expose CCF entry, then we could avoid expand the SoC support list

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22 00:10:14 +02:00
Peng Fan
c66f4f5e30 sandbox: clk: add clk enable/disable test code
Since we added clk enable_count and prograte clk child enabling
operation to clk parent, so add a new function sandbox_clk_enable_count
to get enable_count for test usage.

And add test code to get the enable_count after we enable/disable
the device clk.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22 00:10:09 +02:00
Peng Fan
0520be0f67 clk: prograte clk enable/disable to parent
On i.MX8MM, thinking such as clk path
OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device

Only enabling CCGR GATE is not enough, we also need to enable PLL GATE
to make sure the clk path work. So when enabling CCGR GATE,
we could prograte to enabling PLL GATE to make life easier.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22 00:10:09 +02:00
Peng Fan
e6849e2fd8 clk: introduce enable_count
As what Linux Kernel 5.3.0 provides when enable/disable clk,
there is an enable_count in clk_core_disable/enable. Introduce
enable_count to track the clk enable/disable count when
clk_enable/disable for CCF. And Initialize enable_count to 0 when
register the clk.

And clk tree dump with enable_count will be supported, it will
be easy for us to check the clk status with enable_count

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22 00:10:09 +02:00
Sekhar Nori
acbb7cd4d3 clk: add support for clk_is_match()
Add support for clk_is_match() which is required to
know if two clock pointers point to the same exact
physical clock.

Also add a unit test for the new API.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:38 -04:00
Marek Vasut
ca6da6dd93 clk: renesas: Add R8A77980 V3H clock tables
Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Ryder Lee
2d88b5a38e clk: MediaTek: add hifsys entry for MT7623 SoC.
This adds high speed interface subsystem - hifsys (i.e. PCIe and USB)
for MT7623 SoC and enables its reset controller.

The control block is shared with ethsys and accordingly rename the
related defines.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
2019-08-07 15:31:03 -04:00
Tom Rini
898c40c0d6 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Port more CCF code to work with i.MX8 devices.
2019-08-02 13:29:46 -04:00
Heinrich Schuchardt
0c0cdc8610 clk: meson: remove duplicate logic
First thing we check in meson_clk_set_rate_by_id() is current_rate == rate.
There is not need to check it again.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-31 12:11:04 +02:00
Peng Fan
8f611dc71c clk: sandbox: add composite clk
Add composite clk to sandbox driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
2b12957d01 clk: gate: support sandbox
Introduce io_gate_val for sandbox clk gate test usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
0009763588 clk: add composite clk support
Import clk composite clk support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
91944ef09d dm: clk: ignore default settings when node not valid
When the device not binded with a node, we need ignore
the parents and rate settings.

Cc: Simon Glass <sjg@chromium.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
4b91ec076d clk: imx: gate2 add set rate
Add set rate for imx clk-gate2

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
b6c56d90b8 clk: imx: import clk heplers
Import some clk helpers from Linux Kernel for i.MX8MM usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
4f305bf1b6 clk: fixed_rate: export clk_fixed_rate
Export the structure for others to use.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
fe69b030de clk: divider set rate supporrt
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
1c64330318 clk: add clk-gate support
Import clk-gate support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
4b044082c1 clk: mux: add set parent support
Add set parent support for clk mux

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
5b27ff8986 clk: use clk_dev_binded
Preparing to support composite clk.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
2457612d6d clk: introduce clk_dev_binded
When support Clock Common Framework, U-Boot use dev for
clk tree information, there is no clk->parent. When
support composite clk, it contains mux/gate/divider,
but the mux/gate/divider is not binded with device.
So we could not use dev_get_uclass_priv to get the correct
clk_mux/gate/divider. So add clk_dev_binded to let
choose the correct method.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Tom Rini
c957be9ba0 Merge tag 'u-boot-rockchip-20190729' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean up and migrate to use common rockchip spl board file
- Clean up and migrate to use common rockchip board file
- Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
2019-07-29 09:02:15 -04:00
Kever Yang
84a6a27ae3 rockchip: rk3188: init CPU freq in clock driver
Init CPU frquency in clock driver instead of in SPL board file,
this will help for use common board file later.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29 10:25:27 +08:00
Tom Rini
df9a7a195b u-boot-imx-20190719
- CCF for i.MX6
 - nandbcb command to write SPL into NAND
 - Switch to DM (i.MX28)
 - Boards: Toradex, engicam, DH
 - Fixes for i.MX8
 - Fixes for i.MX7ULP
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
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Merge tag 'u-boot-imx-20190719' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20190719

- CCF for i.MX6
- nandbcb command to write SPL into NAND
- Switch to DM (i.MX28)
- Boards: Toradex, engicam, DH
- Fixes for i.MX8
- Fixes for i.MX7ULP

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
2019-07-27 09:35:05 -04:00
Sekhar Nori
e497fabb91 clk: initialize clk->data when using default xlate
Right now when using clk_of_xlate_default(), clk->data
remains un-initialized because clk_get_bulk() does not
initialize memory on allocation of clock structure.

This can cause problems when data is used to match if
two clocks pointers are exactly the same underlying
clocks, for example.

Fix it by initializing clk->data to 0.

Suggested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-07-24 12:54:08 -07:00
Tom Rini
ff8c23e784 - add rtc driver for stm32mp1
- add remoteproc driver for stm32mp1
 - use kernel qspi compatible string for stm32
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Merge tag 'u-boot-stm32-20190723' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- add rtc driver for stm32mp1
- add remoteproc driver for stm32mp1
- use kernel qspi compatible string for stm32
2019-07-23 14:16:21 -04:00
Patrick Delaunay
fd7fe1bb8d clk: stm32mp1: Add RTC clock entry
Add RTCAPB and RTC clock support.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-22 11:04:52 +02:00
Tom Rini
79ea03b38a Merge tag 'rockchip-for-v2019.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rk3399 lpddr4 support
- rk3399-rock960 board support improvement
- Eliminate pyelftools dependency by make_fit_atf.py
- clean up rockchip dts to use -u-boot.dtsi
- use ARM arch/generic timer instead of rk_timer
- clean up Kconfig options for board support
2019-07-21 15:40:21 -04:00
Jagan Teki
f556d75aed clk: rockchip: rk3399: Set 400MHz ddr clock
Add support for setting 400MHz ddr clock.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21 00:00:25 +08:00
Jagan Teki
0956568637 clk: rockchip: rk3399: Set 50MHz ddr clock
Add support for setting 50MHz ddr clock.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21 00:00:22 +08:00
Lukasz Majewski
87e460c304 clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]
This patch provides code to implement the CCF clock tree in sandbox. It
uses all the introduced primitives; some generic ones are reused, some
sandbox specific were developed.

In that way (after introducing the real CCF tree in sandbox) the recently
added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested
in their natural work environment.

Usage (sandbox_defconfig and sandbox_flattree_defconfig):
./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf"

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
5da0095e3a clk: sandbox: Adjust clk-mux.c to emulate reading divider value from HW
The generic mux clock code for CCF requires reading the clock multiplexer
value from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the mux structure (accessible only when sandbox is run)
has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
6bb15d6f07 clk: sandbox: Adjust clk-divider to emulate reading its value from HW
The generic divider clock code for CCF requires reading the divider value
from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the divider structure (accessible only when sandbox is
run) has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
1a961c9b32 dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flag
If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate()
provides recalculated clock value without considering the cache setting.

This may be necessary for some clocks tightly coupled with power domains
(i.e. imx8), and prevents from reading invalid cached values.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
1d7993d1d0 clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y
SHA1: 5752b50477da)to provide clocks support as it is used on the Linux
kernel with Common Clock Framework [CCF] setup.

The directory structure has been preserved. The ported code only supports
reading information from PLL, MUX, Divider, etc and enabling/disabling
the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic
to the alias numbering as the information about the clock is read from the
device tree.

One needs to pay attention to the comments indicating necessary for U-Boot's
driver model changes.

If needed, the code can be extended to support the "set" part of the clock
management.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
2796af7368 dm: clk: Define clk_get_by_id() for clk operations
This commit adds the clk_get_by_id() function, which is responsible
for getting the udevice with matching clk->id. Such approach allows
re-usage of inherit DM list relationship for the same class (UCLASS_CLK).
As a result - we don't need any other external list - it is just enough
to look for UCLASS_CLK related udevices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
4aa78300a0 dm: clk: Define clk_get_parent_rate() for clk operations
This commit adds the clk_get_parent_rate() function, which is responsible
for getting the rate of parent clock.
Unfortunately, u-boot's DM support for getting parent is different
(the parent relationship is in udevice) than the one in Common Clock
Framework [CCF] in Linux.

To alleviate this problem - the clk_get_parent_rate() function has been
introduced to clk-uclass.c.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
0c660c2b32 dm: clk: Define clk_get_parent() for clk operations
This commit adds the clk_get_parent() function, which is responsible
for getting the parent's struct clock pointer.

U-Boot's DM support for getting parent is different (the parent
relationship is in udevice) than the one in Common Clock Framework [CCF]
in Linux. To obtain the pointer to struct clk of parent the
pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
36bac0a193 clk: Provide struct clk for fixed rate clock (clk_fixed_rate.c)
Up till now the fixed rate clock ('osc') has been added to UCLASS_CLK
without declaring struct clk. As a result it was only accessible by
iterating the udevice's uclass list.

This is a problem for clock code, which operates on pointers to struct
clk (like clk_get_rate()), not udevices.

After this change struct clk is accessible from udevice and udevice from
struct clk.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Lukasz Majewski
ec8f1c02dd clk: Remove clock ID check in .get_rate() of clk_fixed_*
This check requires the struct clk passed to .get_rate() to be always
cleared out as any clock with valid ID causes -EINVAL return value.

The return code of fixed clocks shall always be returned.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 14:50:30 +02:00
Anup Patel
8633edeb2a clk: sifive: Drop GEMGXL clock driver
The GEMGXL clock driver is now directly part of Cadence MACB
ethernet driver in upstream Linux kernel. There is no separate
GEMGXL clock driver in upstream Linux kernel hence we drop
GEMGXL clock driver from U-Boot as well.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Anup Patel
ed0ef3776c clk: sifive: Sync-up main driver with upstream Linux
The DT bindings of SiFive clock driver in upstream Linux has
changes. As-per latest DT bindings, the clock driver takes two
parent clocks and compatible string has also changed.

This patch sync-up SiFive clock driver implementation as-per
upstream Linux so that we now use latest DT bindings.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Anup Patel
66591a719a clk: sifive: Sync-up DT bindings header with upstream Linux
The location and license header of DT bindings header for SiFive
clock driver has changed in upstream Linux hence this patch.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Anup Patel
c236802696 clk: sifive: Sync-up WRPLL library with upstream Linux
Now that SiFive clock driver is merged in upstream Linux, we
sync-up WRPLL library used by SiFive clock driver with upstream
Linux sources.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Anup Patel
d04c79d2b2 clk: sifive: Factor-out PLL library as separate module
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Jagan Teki
dd7dfa217e clk: rockchip: rk3399: Fix check patch warnings and checks
- CHECK: spaces preferred around that '*'
- CHECK: spaces preferred around that '/'
- CHECK: space preferred before that '|'
- WARNING: macros should not use a trailing semicolon
- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'
- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'
- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'
- WARNING: line over 80 characters
- CHECK: Prefer kernel type 'u8' over 'uint8_t'
- Add proper macro definitions arrangements

Note: there are still line over 80 characters and other warnings but
fixing those making code look unreadable, so I kept it as it is.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Mark Kettenis
555ceca088 rockchip: clk: rk3399: handle clk_enable requests for USB3
The "simple" OF glue layer for the Designware USB3 core enables
all refernced clocks.  These need to be need to be implemented
otherwise the driver fails to probe.  A dummy implementation
that simply returns success is sufficient since the RK3399 comes
out of reset with all clock gates open.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19 11:11:09 +08:00
Tom Rini
0e80dda32c Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- Beelink-x2 STB support (Marcus)
- H6 DDR3, LPDDR3 changes (Andre, Jernej)
- H6 pin controller, USB PHY (Andre)
2019-07-16 11:19:31 -04:00
Andre Przywara
106c1300a5 sunxi: clocks: Add H6 USB clock gates and resets
To enable USB support in U-Boot, add the required clock and reset gates
to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will
pick them up from there automatically.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:13:15 +05:30
Tom Rini
a9a3a37f92 - syscon: add support for power off
- stm32mp1: add op-tee config
 - stm32mp1: add specific commands: stboard and stm32key
 - add stm32 mailbox driver
 - solve many stm32 warnings when building with W=1
 - update stm32 gpio driver
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Merge tag 'u-boot-stm32-20190712' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- syscon: add support for power off
- stm32mp1: add op-tee config
- stm32mp1: add specific commands: stboard and stm32key
- add stm32 mailbox driver
- solve many stm32 warnings when building with W=1
- update stm32 gpio driver
2019-07-14 09:09:49 -04:00
Patrick Delaunay
67d74ce2fa clk: clk_stm32mp1: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/clk/clk_stm32mp1.c: In function 'stm32mp1_clk_get_parent':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
  for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
                ^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:55 +02:00
Patrick Delaunay
dfda7d4c83 stm32mp1: syscon: remove stgen
Reduce difference with kernel Linux device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:18:53 +02:00
Masahiro Yamada
9a2f0e5ccd clk: uniphier: add EMMC clock for LD11, LD20, and PXs3
I also added comments for NAND clocks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:41:55 +09:00
Tom Rini
2702646bc0 - Add Ethernet support for STM32MP1
- Add saveenv support for STM32MP1
 - Add STM32MP1 Avenger96 board support
 - Add SPI driver suport for STM32MP1
 - Add watchdog support for STM32MP1
 - Update power supply check via USB TYPE-C for STM32MP1 discovery board
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Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-boot

- Add Ethernet support for STM32MP1
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
2019-06-11 17:22:22 -04:00
Marcel Ziswiler
16f8b84917 clk: imx8qm: fix usdhc2 clocks
Trying to bring up uSDHC2 the following error message was observed:

MMC:   imx8_clk_set_rate(Invalid clk ID #60)
imx8_clk_set_rate(Invalid clk ID #60)
usdhc@5b030000 - probe failed: -22

This commit fixes this by properly setting resp. clocks.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
2019-06-11 10:42:48 +02:00
Patrick Delaunay
f6ccdda126 stm32mp1: clk: use the correct identifier for ethck
ETHCK_K is the identifier the kernel clock for ETH in kernel
binding, selected by ETHKSELR / gated by ETHCKEN = BIT(7).
U-Boot driver need to use the same identifier, so change ETHCK
to ETHCK_K.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
2019-06-06 17:40:18 +02:00
Patrice Chotard
248278d7f7 clk: stm32mp1: Add SPI1 clock entry
Add missing SPI1 clock needed by SPI1 instance.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-06-06 17:40:17 +02:00
Bin Meng
49191d259f clk: sifive: Add clock driver for GEMGXL MGMT
This adds a clock driver to support the GEMGXL management IP block
found in FU540 SoCs to control GEM TX clock operation mode for
10/100/1000 Mbps.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-06-01 13:33:17 -05:00
Tom Rini
8a802a2eef Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchip
- some fix for rk3399-puma;
- rockchip script make_fit_atf.py cleanup
- Enable TPL for rk3399 orangepi and nanopi4;
- add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
2019-05-31 07:17:09 -04:00
Neil Armstrong
08e09c263f clk: meson-g12a: Add PCIE PLL support
The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed
for USB to operate, add basic support for it and associated gates.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-05-31 09:57:49 +02:00
Christoph Muellner
2461543632 rockchip: clk: rk3399: allow requests for all UART clocks
This patch adds the rate for UART1 and UART3 the same way
as already implemented for UART0 and UART2.

This is required for boards, which have their console output
on these UARTs.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30 18:22:35 +08:00
Patrick Delaunay
c3e828bff2 clk: stm32mp1: add set_rate for DDRPHYC clock
Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23 11:36:47 +02:00
Mario Six
487bb2bc85 mpc83xx_clk: Add enable method
Some DM drivers have hardcoded clk_enable calls when handling
clocks (for example the fsl_esdhc driver).

To work with these drivers, add an enable method to the MCP83xx clock
driver (which does nothing, because the clocks are always enabled).

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:52:34 +02:00
Tom Rini
f30f268a07 Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchip
Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
2019-05-09 12:36:17 -04:00
Tom Rini
504bf790da Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- H6 Beelink GS1 board (Clément)
- Olimex A64-Teres-I board (Jonas)
- sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej)
- Change include order (Jagan)
- EPHY clock changes (Jagan)
- EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
2019-05-08 16:21:43 -04:00
Jagan Teki
dcb63fcd16 clk: Use clk_get_by_index_tail()
clk_get_by_index_tail() now handle common clk get by index
code so use it from clk_get_by_indexed_prop().

Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09 00:44:13 +05:30
Jagan Teki
75f98314f9 clk: Get the CLK by index without device
Getting a CLK by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process CLK operation for child
without udevice but with ofnode.

So add clk_get_by_index_nodev() and move the common code
in clk_get_by_index_tail() to use for clk_get_by_index()

Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09 00:44:13 +05:30
Jagan Teki
db2f696147 clk: sifive: fu540-prci: Change include order
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.

In these scenarios with current order of include files
the fu540-prci driver is unable to find CONFIG_ENV_SIZE.

In file included from arch/riscv/include/asm/u-boot.h:23:0,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/clk.h:11,
                 from include/clk-uclass.h:13,
                 from drivers/clk/sifive/fu540-prci.c:32:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
 #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)

So, fix consists of changing the order of include files
in fu540-prci.c to include first common.h file.

Cc: Anup Patel <Anup.Patel@wdc.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09 00:43:59 +05:30
Kever Yang
5793e8c271 rockchip: clk: rk322x: fix assert clock value
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
e4d0d61275 rockchip: rk322x: add CLK_EMMC_SAMPLE clock support
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Tom Rini
3570ea1f98 Improvements and new features:
- improved SPI driver for better read throughput
 - refactors initialisation of debug UART init
 - restructures header file paths
 - adds pinctrl improvements
 
 Adds Kever as a co-custodian.
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Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchip

Improvements and new features:
- improved SPI driver for better read throughput
- refactors initialisation of debug UART init
- restructures header file paths
- adds pinctrl improvements

Adds Kever as a co-custodian.
2019-05-01 11:52:04 -04:00
Tom Rini
b4ee6daad7 Porting to DM and i.MX8
------------------------
 
 - warp7 to DM
 - kp_imx53 to DM
 - Warnings in DT
 - MX8QM support
 - colibri-imx6ull to DM
 - imx7d-pico to DM
 - ocotp for MX8
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Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx

Porting to DM and i.MX8
------------------------

- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
2019-05-01 07:25:51 -04:00
Kever Yang
15f09a1a83 rockchip: use 'arch-rockchip' as header file path
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Peng Fan
e45efe90cd clk: imx8: add i.MX8QM clk driver
Add i.MX8QM clk driver, SDHC/FEC/UART/I2C supported.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
98c63a7840 clk: imx8: split code into common and soc specific part
To make it easy to add new clk driver for i.MX8, split
the code into common part and SoC specific part.

Make the get/set/enable non static and introduce a num_clks for
soc_clk_dump, because the arrays are moved to clk-imx8qxp.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Tom Rini
ceb6ddbc73 - Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
 - Add support for the Libretech-AC AML-S805X-AC board
 - Add Amlogic AXG reset compatible
 - Add I2C support for Amlogic AXG
 - Fix AXG PIN and BANK pinctrl definitions
 - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
 - Add initial support for Amlogic G12A SoC and U200 board
 - Enable PHY_REALTEK for selected boards
 - Fix Khadas VIM2 README
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Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogic

- Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
- Add support for the Libretech-AC AML-S805X-AC board
- Add Amlogic AXG reset compatible
- Add I2C support for Amlogic AXG
- Fix AXG PIN and BANK pinctrl definitions
- Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
- Add initial support for Amlogic G12A SoC and U200 board
- Enable PHY_REALTEK for selected boards
- Fix Khadas VIM2 README
2019-04-24 12:26:25 -04:00
Fabien Parent
cd52c3253a clk: mediatek: add driver for MT8516
Add clock driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
[trini: Redo whitespace]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
fe913a8bb6 clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:26 -04:00
Jerome Brunet
912af8423f clk: meson: add g12a support
Add basic support for the Amlogic G12A clock controller based on
the AXG driver.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Jerome Brunet
f5abfed8e9 clk: create meson directory and move related drivers
In order to support the Amlogic G12A clock controller,
re-architect the clock files into a meson directory.

No functionnal changes.

MAINTAINERS entry is also updated.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Tom Rini
4b37f36d68 Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Convert DM_MMC and DM_SCSI
- A20, R40, H6 Linux dts(i) sync
- CLK, RESET support for sunxi, sun8_emac net drivers
2019-04-17 09:19:45 -04:00
Jagan Teki
33685372cf clk: sunxi: r40: Fix GMAC reset reg offset
GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1: 68620c9698)

So, fix by updating the reg offset for RST_BUS_GMAC.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-16 16:29:00 +05:30
Hannes Schmelzer
2aff722629 ARM: zynq: Add missing i2c get_rate for fixing i2c SPL
The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C
support because requesting the clock for the I2C ip-block isn't
supported during SPL.

To fixup this we add support requesting clocks for:
- i2c0
- i2c1

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16 11:51:34 +02:00
Tom Rini
cf5eebeb18 fdtdec tests and improvements for carve-outs
pinctrl race-condition fix
 various other fixes in sandbox, sound, mkimage, etc.
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Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dm

fdtdec tests and improvements for carve-outs
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
2019-04-13 08:27:35 -04:00
Tom Rini
015289580f stm32 patches for v2019.07-rc1
- Add trusted boot with TF-A for stm32mp1
 - stm32mp1 dts files sync'ed with Linux version
 - add STM32MP1 Discovery boards (DK1 and DK2)
 - add STMFX gpio expander driver
 - misc improvement for stm3mp1 supports
 - rename stpmu1 to stpmic1 (official name)
 - stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu)
 - add STM32 FMC2 NAND flash controller driver
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Merge tag 'u-boot-stm32-20190412' of https://github.com/patrickdelaunay/u-boot

stm32 patches for v2019.07-rc1
- Add trusted boot with TF-A for stm32mp1
- stm32mp1 dts files sync'ed with Linux version
- add STM32MP1 Discovery boards (DK1 and DK2)
- add STMFX gpio expander driver
- misc improvement for stm3mp1 supports
- rename stpmu1 to stpmic1 (official name)
- stm32_qspi: move to exec_op (spi nor driver for stm32 mpu and mcu)
- add STM32 FMC2 NAND flash controller driver
2019-04-12 15:43:19 -04:00
Patrick Delaunay
abf2678f0f stm32mp1: add trusted boot with TF-A
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
  BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32

The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power

The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12 16:09:13 +02:00
Patrick Delaunay
22319042a3 clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_reloc
Prepare to remove dm_fdt_pre_reloc function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11 20:10:05 -06:00
Patrick Delaunay
7bb94ab1d5 clk: at91: replace dm_fdt_pre_reloc by dm_ofnode_pre_reloc
Prepare to remove dm_fdt_pre_reloc

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11 20:10:05 -06:00
Marek Vasut
72242e5439 clk: renesas: Synchronize Gen3 tables with Linux 5.0
Synchronize R-Car Gen3 clock tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
a3c31e98a1 clk: renesas: Synchronize Gen2 tables with Linux 5.0
Synchronize R-Car Gen2 clock tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
933143997b clk: renesas: Add R8A77965 clock tables
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Jagan Teki
9d1e136734 clk: sunxi: a10: Add CLK_AHB_GMAC
CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-01 21:45:15 +05:30
Marek Vasut
3cb2849c76 clk: renesas: Add support for setting MMCIF clock divider on Gen2
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms.
This allows the MMCIF driver to set higher clock rate if desired.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Marek Vasut
4b135d5464 clk: renesas: Fix swapped div and mul in debug output on Gen2
The $div and $mul values were swapped in the debug output,
fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Marek Vasut
45b01b462f clk: renesas: Fix SDH clock divider decoding on Gen2
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Jagan Teki
aefc0b7a60 clk: sunxi: h3: Implement EPHY CLK and RESET
EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-09 13:16:35 +05:30
Jagan Teki
68620c9698 clk: sunxi: Implement EMAC, GMAC clocks, resets
- Implement EMAC, GMAC clocks via ccu_clk_gate for
  all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
  supported Allwinner SoCs.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-09 13:16:35 +05:30
Jagan Teki
3d83c4a1d4 clk: sunxi: Implement A10 EMAC clocks
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.

Which would eventually used in sunxi_emac.c driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-09 13:16:35 +05:30
Jagan Teki
82111469a5 clk: sunxi: Implement SPI clocks, resets
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
  supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
  Allwinner SoCs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04 18:08:56 +05:30
Tom Rini
35b05146f6 Merge branch 'master' of git://git.denx.de/u-boot-sh
- Gen2/Gen3 fixes for warnings and sdhi
2019-02-28 18:57:17 -05:00
Anup Patel
b630d57d0a clk: Add fixed-factor clock driver
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 09:12:33 +08:00
Anup Patel
c40b6df87f clk: Add SiFive FU540 PRCI clock driver
Add driver code for the SiFive FU540 PRCI IP block.  This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra <wesley@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-27 09:12:33 +08:00
Marek Vasut
18a37a5a8b clk: rmobile: Drop def_bool per SoC
Drop per SoC def_bool on each driver, since this is now implied by
SoC Kconfig option instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Patrick Delaunay
bbd108a082 clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
Patrick Delaunay
8d6310aa0b clk: stm32mp1: add debug information
Add support of clk dump command and
display information during probe (under CONFIG_DISPLAY_CPUINFO).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
Patrick Delaunay
f3a23c2609 clk: stm32mp1: recalculate counter when switching freq
Because stgen is initialized with HSI clock, we need to
recalculate the counter when changing frequency.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
63201281e5 clk: stm32mp1: correct access to RCC_OCENSETR/RCC_OCENCLRR
Remove unnecessary setbits on set/clear registers.
Avoid to deactivate HSI with HSE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
d661f61847 clk: stm32mp1: add IPCC clock
Add support for enable/disable of IPCC clock using AHB3 registers

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
86617dd140 clk: stm32mp1: no more get ck_usbo_48m in device tree
Remove support of ck_usbo_48m clock node in device tree,
but force 48MHz frequency to prepare alignment
with kernel device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:55 -05:00
Simon Glass
5328af1774 rockchip: clk: Add mention of four new clocks
These clocks are needed to get MMC running. We don't actually support
setting them yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
6831616063 clk: Improve debug message in clk_set_default_rates()
It is helpful to print the clock number as well as the index, so that this
can be looked up in the binding file. Update the debug() statement to do
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
Simon Glass
3dbfe5ae61 rockchip: rk3288: Add i2s pinctrl and clock support
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Andre Przywara
13b0867dc3 sunxi: clk: enable clk and reset for CCU devices
Some Allwinner clock devices have parent clocks and reset gates itself,
which need to be activated for them to work.

Add some code to just assert all resets and enable all clocks given.
This should enable the A80 MMC config clock, which requires both to be
activated. The full CCU devices typically don't require resets, and have
just fixed clocks as their parents. Since we treat both as optional and
enabling fixed clocks is a NOP, this works for all cases, without the need
to differentiate between those clock types.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-30 18:21:35 +05:30
Andre Przywara
e0c7ce7e52 sunxi: clk: A80: add MMC clock support
The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.

Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: fix a80 mmc clock config compatible]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:33:08 +05:30
Andre Przywara
bb3e5aa289 sunxi: clk: add MMC gates/resets
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.

We don't advertise the mod clock yet, as this is still handled by the
MMC driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:30:11 +05:30
Jagan Teki
6901aab8e3 clk: sunxi: Add Allwinner A80 CLK driver
Add initial clock driver for Allwinner A80.

- Implement UART bus clocks via ccu_clk_gate table for
  A80, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
337fcdc06b clk: sunxi: Add Allwinner H6 CLK driver
Add initial clock driver for Allwinner H6.

- Implement UART bus clocks via ccu_clk_gate table for
  H6, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
8606f960d4 clk: sunxi: Implement UART resets
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
4acc711930 clk: sunxi: Implement UART clocks
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
6239a6d092 clk: sunxi: Add Allwinner V3S CLK driver
Add initial clock driver for Allwinner V3S.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for V3S, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for V3S, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
78eb2a41f3 clk: sunxi: Add Allwinner R40 CLK driver
Add initial clock driver for Allwinner R40.

- Implement USB bus and USB clocks via ccu_clk_gate
  for R40, so it can accessed in common clk enable
  and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for R40, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
03d87f5909 clk: sunxi: Add Allwinner A83T CLK driver
Add initial clock driver for Allwinner A83T.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for A83T, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for A83T, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
3ab029368a clk: sunxi: Add Allwinner A23/A33 CLK driver
Add initial clock driver for Allwinner A23/A33.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for A23/A33, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for A23/A33, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
4927e2e8d3 clk: sunxi: Add Allwinner A31 CLK driver
Add initial clock driver for Allwinner A31.

- Implement USB ahb1 and USB clocks via ccu_clk_gate table
  for A31, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table
  for A31, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
c8e743c1e8 clk: sunxi: Add Allwinner A10s/A13 CLK driver
Add initial clock driver for Allwinner A10s/A13.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10s/A13, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
6590bd8c47 clk: sunxi: Add Allwinner A10/A20 CLK driver
Add initial clock driver for Allwinner A10/A20.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10/A20, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30