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clk: imx: add i.IMXRT1020 clk driver
Add i.MXRT1020 clk driver support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Giulio Benetti
Stefano Babic
parent
7c0fbf2fe3
commit
ac4e7610da
4 changed files with 296 additions and 0 deletions
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@ -69,6 +69,22 @@ config CLK_IMX8MP
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help
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This enables support clock driver for i.MX8MP platforms.
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config SPL_CLK_IMXRT1020
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bool "SPL clock support for i.MXRT1020"
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depends on ARCH_IMXRT && SPL
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select SPL_CLK
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select SPL_CLK_CCF
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help
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This enables SPL DM/DTS support for clock driver in i.MXRT1020
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config CLK_IMXRT1020
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bool "Clock support for i.MXRT1020"
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depends on ARCH_IMXRT
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select CLK
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select CLK_CCF
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help
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This enables support clock driver for i.MXRT1020 platforms.
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config SPL_CLK_IMXRT1050
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bool "SPL clock support for i.MXRT1050"
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depends on ARCH_IMXRT && SPL
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@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
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obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
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clk-composite-8m.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
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227
drivers/clk/imx/clk-imxrt1020.c
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227
drivers/clk/imx/clk-imxrt1020.c
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@ -0,0 +1,227 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright(C) 2020
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <dt-bindings/clock/imxrt1020-clock.h>
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#include "clk.h"
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static ulong imxrt1020_clk_get_rate(struct clk *clk)
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{
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struct clk *c;
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int ret;
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debug("%s(#%lu)\n", __func__, clk->id);
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ret = clk_get_by_id(clk->id, &c);
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if (ret)
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return ret;
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return clk_get_rate(c);
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}
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static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *c;
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int ret;
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debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
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ret = clk_get_by_id(clk->id, &c);
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if (ret)
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return ret;
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return clk_set_rate(c, rate);
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}
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static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
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{
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struct clk *c;
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int ret;
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debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
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ret = clk_get_by_id(clk->id, &c);
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if (ret)
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return ret;
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if (enable)
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ret = clk_enable(c);
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else
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ret = clk_disable(c);
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return ret;
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}
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static int imxrt1020_clk_disable(struct clk *clk)
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{
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return __imxrt1020_clk_enable(clk, 0);
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}
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static int imxrt1020_clk_enable(struct clk *clk)
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{
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return __imxrt1020_clk_enable(clk, 1);
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}
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static struct clk_ops imxrt1020_clk_ops = {
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.set_rate = imxrt1020_clk_set_rate,
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.get_rate = imxrt1020_clk_get_rate,
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.enable = imxrt1020_clk_enable,
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.disable = imxrt1020_clk_disable,
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};
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static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
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static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", };
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static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", };
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static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
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static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
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static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
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static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
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static int imxrt1020_clk_probe(struct udevice *dev)
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{
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void *base;
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/* Anatop clocks */
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base = (void *)ANATOP_BASE_ADDR;
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clk_dm(IMXRT1020_CLK_PLL2_SYS,
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imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
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base + 0x30, 0x1));
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clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
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imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
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base + 0x10, 0x1));
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/* PLL bypass out */
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clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
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imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
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pll2_bypass_sels,
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ARRAY_SIZE(pll2_bypass_sels),
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CLK_SET_RATE_PARENT));
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clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
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imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
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pll3_bypass_sels,
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ARRAY_SIZE(pll3_bypass_sels),
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CLK_SET_RATE_PARENT));
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clk_dm(IMXRT1020_CLK_PLL3_80M,
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imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
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clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
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imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
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clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M,
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imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
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clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M,
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imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
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clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M,
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imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base + 0x100, 3));
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clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M,
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imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0, 1));
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clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M,
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imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0, 3));
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/* CCM clocks */
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base = dev_read_addr_ptr(dev);
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if (base == (void *)FDT_ADDR_T_NONE)
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return -EINVAL;
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clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
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imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
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pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
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clk_dm(IMXRT1020_CLK_PERIPH_SEL,
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imx_clk_mux("periph_sel", base + 0x14, 25, 1,
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periph_sels, ARRAY_SIZE(periph_sels)));
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clk_dm(IMXRT1020_CLK_USDHC1_SEL,
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imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
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usdhc_sels, ARRAY_SIZE(usdhc_sels)));
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clk_dm(IMXRT1020_CLK_USDHC2_SEL,
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imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
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usdhc_sels, ARRAY_SIZE(usdhc_sels)));
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clk_dm(IMXRT1020_CLK_LPUART_SEL,
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imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
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lpuart_sels, ARRAY_SIZE(lpuart_sels)));
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clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
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imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
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semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
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clk_dm(IMXRT1020_CLK_SEMC_SEL,
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imx_clk_mux("semc_sel", base + 0x14, 6, 1,
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semc_sels, ARRAY_SIZE(semc_sels)));
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clk_dm(IMXRT1020_CLK_AHB_PODF,
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imx_clk_divider("ahb_podf", "periph_sel",
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base + 0x14, 10, 3));
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clk_dm(IMXRT1020_CLK_USDHC1_PODF,
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imx_clk_divider("usdhc1_podf", "usdhc1_sel",
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base + 0x24, 11, 3));
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clk_dm(IMXRT1020_CLK_USDHC2_PODF,
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imx_clk_divider("usdhc2_podf", "usdhc2_sel",
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base + 0x24, 16, 3));
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clk_dm(IMXRT1020_CLK_LPUART_PODF,
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imx_clk_divider("lpuart_podf", "lpuart_sel",
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base + 0x24, 0, 6));
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clk_dm(IMXRT1020_CLK_SEMC_PODF,
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imx_clk_divider("semc_podf", "semc_sel",
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base + 0x14, 16, 3));
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clk_dm(IMXRT1020_CLK_USDHC1,
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imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
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clk_dm(IMXRT1020_CLK_USDHC2,
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imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
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clk_dm(IMXRT1020_CLK_LPUART1,
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imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
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clk_dm(IMXRT1020_CLK_SEMC,
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imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
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#ifdef CONFIG_SPL_BUILD
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struct clk *clk, *clk1;
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clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);
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clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk);
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clk_set_parent(clk1, clk);
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/* Configure PLL3_USB_OTG to 480MHz */
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clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk);
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clk_enable(clk);
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clk_set_rate(clk, 480000000UL);
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clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1);
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clk_set_parent(clk1, clk);
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clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk);
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clk_set_rate(clk, 297000000UL);
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clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk);
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clk_enable(clk);
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clk_set_rate(clk, 528000000UL);
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clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1);
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clk_set_parent(clk1, clk);
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#endif
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return 0;
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}
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static const struct udevice_id imxrt1020_clk_ids[] = {
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{ .compatible = "fsl,imxrt1020-ccm" },
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{ },
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};
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U_BOOT_DRIVER(imxrt1020_clk) = {
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.name = "clk_imxrt1020",
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.id = UCLASS_CLK,
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.of_match = imxrt1020_clk_ids,
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.ops = &imxrt1020_clk_ops,
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.probe = imxrt1020_clk_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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52
include/dt-bindings/clock/imxrt1020-clock.h
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52
include/dt-bindings/clock/imxrt1020-clock.h
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@ -0,0 +1,52 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright(C) 2020
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H
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#define __DT_BINDINGS_CLOCK_IMXRT1020_H
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#define IMXRT1020_CLK_DUMMY 0
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#define IMXRT1020_CLK_CKIL 1
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#define IMXRT1020_CLK_CKIH 2
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#define IMXRT1020_CLK_OSC 3
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#define IMXRT1020_CLK_PLL2_PFD0_352M 4
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#define IMXRT1020_CLK_PLL2_PFD1_594M 5
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#define IMXRT1020_CLK_PLL2_PFD2_396M 6
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#define IMXRT1020_CLK_PLL2_PFD3_297M 7
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#define IMXRT1020_CLK_PLL3_PFD0_720M 8
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#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9
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#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10
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#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11
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#define IMXRT1020_CLK_PLL2_198M 12
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#define IMXRT1020_CLK_PLL3_120M 13
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#define IMXRT1020_CLK_PLL3_80M 14
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#define IMXRT1020_CLK_PLL3_60M 15
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#define IMXRT1020_CLK_PLL2_BYPASS 16
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#define IMXRT1020_CLK_PLL3_BYPASS 17
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#define IMXRT1020_CLK_PLL6_BYPASS 18
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#define IMXRT1020_CLK_PRE_PERIPH_SEL 19
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#define IMXRT1020_CLK_PERIPH_SEL 20
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#define IMXRT1020_CLK_SEMC_ALT_SEL 21
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#define IMXRT1020_CLK_SEMC_SEL 22
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#define IMXRT1020_CLK_USDHC1_SEL 23
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#define IMXRT1020_CLK_USDHC2_SEL 24
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#define IMXRT1020_CLK_LPUART_SEL 25
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#define IMXRT1020_CLK_ARM_PODF 26
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#define IMXRT1020_CLK_LPUART_PODF 27
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#define IMXRT1020_CLK_USDHC1_PODF 28
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#define IMXRT1020_CLK_USDHC2_PODF 29
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#define IMXRT1020_CLK_SEMC_PODF 30
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#define IMXRT1020_CLK_AHB_PODF 31
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#define IMXRT1020_CLK_USDHC1 32
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#define IMXRT1020_CLK_USDHC2 33
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#define IMXRT1020_CLK_LPUART1 34
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#define IMXRT1020_CLK_SEMC 35
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#define IMXRT1020_CLK_PLL2_SYS 36
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#define IMXRT1020_CLK_PLL3_USB_OTG 37
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#define IMXRT1020_CLK_PLL4_AUDIO 38
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#define IMXRT1020_CLK_PLL6_ENET 39
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#define IMXRT1020_CLK_END 40
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#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */
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