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Xilinx changes for v2020.07

Browse source 
common:
 - Align ENV_FAT_INTERFACE
 - Fix MAC address source print log
 - Improve based autodetection code
 
 xilinx:
 - Enable netconsole
 
 Microblaze:
 - Setup default ENV_OFFSET/ENV_SECT_SIZE
 
 Zynq:
 - Multiple DT updates/fixes
 - Use DEVICE_TREE environment variable for DTB selection
 - Switch to single zynq configuration
 - Enable NOR flash via DM
 - Minor SPL print removal
 - Enable i2c mux driver
 
 ZynqMP:
 - Print multiboot register
 - Enable cache commands in mini mtest
 - Multiple DT updates/fixes
 - Fix firmware probing when driver is not enabled
 - Specify 3rd backup RAM boot mode in SPL
 - Add SPL support for zcu102 v1.1 and zcu111 revA
 - Redesign debug uart enabling and psu_init delay
 - Enable full u-boot run from EL3
 - Enable u-boot.itb generation without ATF with U-Boot in EL3
 
 Versal:
 - Enable distro default
 - Enable others SPI flashes
 - Enable systems without DDR
 
 Drivers:
 - Gem:
   - Flush memory after freeing
   - Handle mdio bus separately
 - Watchdog:
   - Get rid of unused global data pointer
   - Enable window watchdog timer
 - Serial:
   - Change reinitialization logic in zynq serial driver
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Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2020.07

common:
- Align ENV_FAT_INTERFACE
- Fix MAC address source print log
- Improve based autodetection code

xilinx:
- Enable netconsole

Microblaze:
- Setup default ENV_OFFSET/ENV_SECT_SIZE

Zynq:
- Multiple DT updates/fixes
- Use DEVICE_TREE environment variable for DTB selection
- Switch to single zynq configuration
- Enable NOR flash via DM
- Minor SPL print removal
- Enable i2c mux driver

ZynqMP:
- Print multiboot register
- Enable cache commands in mini mtest
- Multiple DT updates/fixes
- Fix firmware probing when driver is not enabled
- Specify 3rd backup RAM boot mode in SPL
- Add SPL support for zcu102 v1.1 and zcu111 revA
- Redesign debug uart enabling and psu_init delay
- Enable full u-boot run from EL3
- Enable u-boot.itb generation without ATF with U-Boot in EL3

Versal:
- Enable distro default
- Enable others SPI flashes
- Enable systems without DDR

Drivers:
- Gem:
  - Flush memory after freeing
  - Handle mdio bus separately
- Watchdog:
  - Get rid of unused global data pointer
  - Enable window watchdog timer
- Serial:
  - Change reinitialization logic in zynq serial driver

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2020-04-07 11:58:44 -04:00
commit 1f47e2aca4
426 changed files with 6837 additions and 4492 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
.azure-pipelines.yml
View file

@ -228,11 +228,11 @@ jobs:
TEST_PY_BD: "qemu-x86_64"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-x86_64$"
zynq_zc702:
TEST_PY_BD: "zynq_zc702"
xilinx_zynq_virt:
TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^zynq_zc702$"
BUILDMAN: "^xilinx_zynq_virt$"
xilinx_versal_virt:
TEST_PY_BD: "xilinx_versal_virt"
TEST_PY_ID: "--id qemu"

6
.gitlab-ci.yml
View file

@ -321,13 +321,13 @@ qemu-x86_64 test.py:
BUILDMAN: "^qemu-x86_64$"
<<: *buildman_and_testpy_dfn
zynq_zc702 test.py:
xilinx_zynq_virt test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "zynq_zc702"
TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
BUILDMAN: "^zynq_zc702$"
BUILDMAN: "^xilinx_zynq_virt$"
<<: *buildman_and_testpy_dfn
xilinx_versal_virt test.py:

6
.travis.yml
View file

@ -505,13 +505,13 @@ matrix:
BUILDMAN="^qemu-x86_64$"
TOOLCHAIN="i386"
BUILD_ROM="yes"
- name: "test/py zynq_zc702"
- name: "test/py xilinx_zynq_virt"
env:
- TEST_PY_BD="zynq_zc702"
- TEST_PY_BD="xilinx_zynq_virt"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="arm-softmmu"
TEST_PY_ID="--id qemu"
BUILDMAN="^zynq_zc702$"
BUILDMAN="^xilinx_zynq_virt$"
- name: "test/py xilinx_versal_virt"
env:
- TEST_PY_BD="xilinx_versal_virt"

6
Kconfig
View file

@ -111,6 +111,7 @@ config ENV_VARS_UBOOT_CONFIG
config NR_DRAM_BANKS
int "Number of DRAM banks"
default 1 if ARCH_SUNXI
default 4
help
This defines the number of DRAM banks.
@ -294,6 +295,11 @@ config ERR_PTR_OFFSET
pointer values - up to 'MAX_ERRNO' bytes below this value must be
unused/invalid addresses.
config PLATFORM_ELFENTRY
string
default "__start" if MIPS
default "_start"
endmenu # General setup
menu "Boot images"

1
MAINTAINERS
View file

@ -447,6 +447,7 @@ M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal/
F: drivers/watchdog/xilinx_wwdt.c
N: (?<!uni)versal
ARM VERSATILE EXPRESS DRIVERS

27
Makefile
View file

@ -3,7 +3,7 @@
VERSION = 2020
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@ -485,6 +485,7 @@ endif
version_h := include/generated/version_autogenerated.h
timestamp_h := include/generated/timestamp_autogenerated.h
defaultenv_h := include/generated/defaultenv_autogenerated.h
dt_h := include/generated/dt.h
no-dot-config-targets := clean clobber mrproper distclean \
help %docs check% coccicheck \
@ -1654,18 +1655,17 @@ OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \
u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,pad_cat)
# Create a new ELF from a raw binary file.
ifndef PLATFORM_ELFENTRY
PLATFORM_ELFENTRY = "_start"
endif
quiet_cmd_u-boot-elf ?= LD $@
cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
--defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
-Ttext=$(CONFIG_SYS_TEXT_BASE)
u-boot.elf: u-boot.bin
u-boot.elf: u-boot.bin u-boot-elf.lds
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE
$(call if_changed_dep,cpp_lds)
# MediaTek's ARM-based u-boot needs a header to contains its load address
# which is parsed by the BootROM.
# If the SPL build is enabled, the header will be added to the spl binary,
@ -1775,7 +1775,7 @@ endif
# prepare2 creates a makefile if using a separate output directory
prepare2: prepare3 outputmakefile cfg
prepare1: prepare2 $(version_h) $(timestamp_h) \
prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) \
include/config/auto.conf
ifeq ($(wildcard $(LDSCRIPT)),)
@echo >&2 " Could not find linker script."
@ -1841,12 +1841,23 @@ define filechk_defaultenv.h
xxd -i ; echo ", 0x00" ; )
endef
define filechk_dt.h
(if test -n "$${DEVICE_TREE}"; then \
echo \#define DEVICE_TREE \"$(DEVICE_TREE)\"; \
else \
echo \#define DEVICE_TREE CONFIG_DEFAULT_DEVICE_TREE; \
fi)
endef
$(version_h): include/config/uboot.release FORCE
$(call filechk,version.h)
$(timestamp_h): $(srctree)/Makefile FORCE
$(call filechk,timestamp.h)
$(dt_h): $(srctree)/Makefile FORCE
$(call filechk,dt.h)
$(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE
$(call filechk,defaultenv.h)

90
arch/arc/include/asm/io.h
View file

@ -9,6 +9,12 @@
#include <linux/types.h>
#include <asm/byteorder.h>
/*
* Compiler barrier. It prevents compiler from reordering instructions before
* and after it. It doesn't prevent HW (CPU) from any reordering though.
*/
#define __comp_b() asm volatile("" : : : "memory")
#ifdef __ARCHS__
/*
@ -45,8 +51,8 @@
#define __iormb() rmb()
#define __iowmb() wmb()
#else
#define __iormb() asm volatile("" : : : "memory")
#define __iowmb() asm volatile("" : : : "memory")
#define __iormb() __comp_b()
#define __iowmb() __comp_b()
#endif
static inline void sync(void)
@ -54,31 +60,47 @@ static inline void sync(void)
/* Not yet implemented */
}
#define __arch_getb(a) (*(unsigned char *)(a))
#define __arch_getw(a) (*(unsigned short *)(a))
#define __arch_getl(a) (*(unsigned int *)(a))
#define __arch_getq(a) (*(unsigned long long *)(a))
/*
* We must use 'volatile' in C-version read/write IO accessors implementation
* to avoid merging several reads (writes) into one read (write), or optimizing
* them out by compiler.
* We must use compiler barriers before and after operation (read or write) so
* it won't be reordered by compiler.
*/
#define __arch_getb(a) ({ u8 __v; __comp_b(); __v = *(volatile u8 *)(a); __comp_b(); __v; })
#define __arch_getw(a) ({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; })
#define __arch_getl(a) ({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; })
#define __arch_getq(a) ({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; })
#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
#define __arch_putb(v, a) ({ __comp_b(); *(volatile u8 *)(a) = (v); __comp_b(); })
#define __arch_putw(v, a) ({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); })
#define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
#define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
#define __raw_writel(v, a) __arch_putl(v, a)
#define __raw_writeq(v, a) __arch_putq(v, a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
#define __raw_readq(a) __arch_getq(a)
/*
* We add memory barriers for __raw_readX / __raw_writeX accessors same way as
* it is done for readX and writeX accessors as lots of U-boot driver uses
* __raw_readX / __raw_writeX instead of proper accessor with barrier.
*/
#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); })
#define __raw_writew(v, c) ({ __iowmb(); __arch_putw(v, c); })
#define __raw_writel(v, c) ({ __iowmb(); __arch_putl(v, c); })
#define __raw_writeq(v, c) ({ __iowmb(); __arch_putq(v, c); })
#define __raw_readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
#define __raw_readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
#define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
#define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
static inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
{
u8 *buf = (uint8_t *)data;
__iowmb();
while (bytelen--)
__arch_putb(*buf++, addr);
}
@ -88,6 +110,8 @@ static inline void __raw_writesw(unsigned long addr, const void *data,
{
u16 *buf = (uint16_t *)data;
__iowmb();
while (wordlen--)
__arch_putw(*buf++, addr);
}
@ -97,6 +121,8 @@ static inline void __raw_writesl(unsigned long addr, const void *data,
{
u32 *buf = (uint32_t *)data;
__iowmb();
while (longlen--)
__arch_putl(*buf++, addr);
}
@ -107,6 +133,8 @@ static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
while (bytelen--)
*buf++ = __arch_getb(addr);
__iormb();
}
static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
@ -115,6 +143,8 @@ static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
while (wordlen--)
*buf++ = __arch_getw(addr);
__iormb();
}
static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
@ -123,6 +153,8 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
while (longlen--)
*buf++ = __arch_getl(addr);
__iormb();
}
/*
@ -130,21 +162,15 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
* ordering rules but do not guarantee any ordering relative to Normal memory
* accesses.
*/
#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
__raw_readw(c)); __r; })
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
__raw_readl(c)); __r; })
#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
__raw_readq(c)); __r; })
#define readb_relaxed(c) ({ u8 __r = __arch_getb(c); __r; })
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; })
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; })
#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; })
#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
cpu_to_le16(v), (c)))
#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \
cpu_to_le32(v), (c)))
#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \
cpu_to_le64(v), (c)))
#define writeb_relaxed(v, c) ((void)__arch_putb((v), (c)))
#define writew_relaxed(v, c) ((void)__arch_putw((__force u16)cpu_to_le16(v), (c)))
#define writel_relaxed(v, c) ((void)__arch_putl((__force u32)cpu_to_le32(v), (c)))
#define writeq_relaxed(v, c) ((void)__arch_putq((__force u64)cpu_to_le64(v), (c)))
/*
* MMIO can also get buffered/optimized in micro-arch, so barriers needed

3
arch/arm/Kconfig
View file

@ -989,6 +989,8 @@ config ARCH_SUNXI
select USB_KEYBOARD if DISTRO_DEFAULTS
select USB_STORAGE if DISTRO_DEFAULTS
select SPL_USE_TINY_PRINTF
select USE_PREBOOT
select SYS_RELOC_GD_ENV_ADDR
imply CMD_DM
imply CMD_GPT
imply CMD_UBI if MTD_RAW_NAND
@ -1366,6 +1368,7 @@ config TARGET_LS1028ARDB
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
help
Support for Freescale LS1028ARDB platform
The LS1028A Development System (RDB) is a high-performance

5
arch/arm/cpu/armv8/cpu.c
View file

@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
"b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
}
void __weak board_cleanup_before_linux(void){}
int cleanup_before_linux(void)
{
/*
@ -40,6 +42,9 @@ int cleanup_before_linux(void)
*
* disable interrupt and turn off caches etc ...
*/
board_cleanup_before_linux();
disable_interrupts();
/*

20
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -74,11 +74,11 @@ config ARCH_LS1043A
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
select SYS_I2C_MXC if !DM_I2C
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
imply CMD_PCI
config ARCH_LS1046A
@ -107,11 +107,11 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
select SYS_I2C_MXC if !DM_I2C
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
imply SCSI
imply SCSI_AHCI

4
arch/arm/dts/Makefile
View file

@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-0000.dtb \
tegra210-p2371-2180.dtb \
tegra210-p2571.dtb
tegra210-p2571.dtb \
tegra210-p3450-0000.dtb
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
@ -276,6 +277,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
zynqmp-zcu102-rev1.0.dtb \
zynqmp-zcu102-rev1.1.dtb \
zynqmp-zcu104-revA.dtb \
zynqmp-zcu104-revC.dtb \
zynqmp-zcu106-revA.dtb \

2
arch/arm/dts/avnet-ultra96-rev1.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Avnet Ultra96 rev1
*
* (C) Copyright 2018, Xilinx, Inc.
* (C) Copyright 2018 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/

2
arch/arm/dts/fsl-ls1028a-qds.dts
View file

@ -49,6 +49,8 @@
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
};

2
arch/arm/dts/fsl-ls1028a-rdb.dts
View file

@ -48,6 +48,8 @@
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
};

3
arch/arm/dts/fsl-ls1046a-frwy.dts
View file

@ -32,3 +32,6 @@
};
&i2c0 {
status = "okay";
};

4
arch/arm/dts/fsl-ls1046a-qds.dtsi
View file

@ -80,3 +80,7 @@
&sata {
status = "okay";
};
&i2c0 {
status = "okay";
};

8
arch/arm/dts/fsl-ls1046a-rdb.dts
View file

@ -43,3 +43,11 @@
&sata {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c3 {
status = "okay";
};

17
arch/arm/dts/fsl-lx2160a-qds.dts
View file

@ -13,6 +13,9 @@
/ {
model = "NXP Layerscape LX2160AQDS Board";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
aliases {
spi0 = &fspi;
};
};
&esdhc0 {
@ -46,6 +49,20 @@
};
};
&fspi {
status = "okay";
mt35xu512aba0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
};
&sata0 {
status = "okay";
};

4
arch/arm/dts/fsl-lx2160a-rdb.dts
View file

@ -39,6 +39,8 @@
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
mt35xu512aba1: flash@1 {
@ -47,6 +49,8 @@
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <1>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
};

4
arch/arm/dts/r8a7792-blanche-u-boot.dts
View file

@ -8,6 +8,10 @@
#include "r8a7792-blanche.dts"
#include "r8a7792-u-boot.dtsi"
&iic3 {
status = "okay";
};
&scif0 {
u-boot,dm-pre-reloc;
};

17
arch/arm/dts/r8a7792.dtsi
View file

@ -444,6 +444,23 @@
status = "disabled";
};
iic3: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7792",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>,
<&dmac1 0x77>, <&dmac1 0x78>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 926>;
status = "disabled";
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";

3
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
View file

@ -37,3 +37,6 @@
u-boot,dm-pre-reloc;
};
&qspi {
status = "okay";
};

1153
arch/arm/dts/stm32mp157-pinctrl.dtsi Normal file
View file

File diff suppressed because it is too large Load diff

9
arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
View file

@ -153,9 +153,12 @@
};
};
&sdmmc1_dir_pins_a {
&sdmmc1_dir_pins_b {
u-boot,dm-spl;
pins {
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
@ -174,7 +177,7 @@
};
};
&sdmmc2_d47_pins_a {
&sdmmc2_d47_pins_b {
u-boot,dm-spl;
pins {
u-boot,dm-spl;

80
arch/arm/dts/stm32mp157a-avenger96.dts
View file

@ -8,6 +8,7 @@
#include "stm32mp157.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp157-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@ -17,10 +18,12 @@
compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
aliases {
eeprom0 = &eeprom0;
ethernet0 = &ethernet0;
mmc0 = &sdmmc1;
serial0 = &uart4;
serial1 = &uart7;
spi0 = &qspi;
};
chosen {
@ -77,16 +80,42 @@
default-state = "off";
};
};
sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";
regulator-name = "sd_switch";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-type = "voltage";
regulator-always-on;
gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1>,
<2900000 0x0>;
};
/* Enpirion EP3A8LQI U2 on the DHCOR */
vdd_io: regulator-buck-io {
compatible = "regulator-fixed";
regulator-name = "buck-io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd>;
};
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
pinctrl-0 = <&ethernet0_rgmii_pins_b>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_b>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii";
max-speed = <1000>;
phy-handle = <&phy0>;
phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
@ -152,7 +181,7 @@
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
@ -170,8 +199,8 @@
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-always-on;
st,mask_reset;
regulator-initial-mode = <0>;
@ -253,6 +282,7 @@
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
interrupt-parent = <&pmic>;
regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
@ -275,6 +305,12 @@
status = "disabled";
};
};
eeprom0: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&iwdg2 {
@ -283,10 +319,29 @@
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd-supply = <&vdd_io>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&rng1 {
status = "okay";
};
@ -297,21 +352,24 @@
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
broken-cd;
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
disable-wp;
st,sig-dir;
st,neg-edge;
st,use-ckin;
sd-uhs-sdr104;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
non-removable;
no-sd;
no-sdio;

6
arch/arm/dts/stm32mp15xx-dhcom.dtsi
View file

@ -12,6 +12,10 @@
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
aliases {
eeprom0 = &eeprom0;
};
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x40000000>;
@ -189,7 +193,7 @@
};
};
eeprom@50 {
eeprom0: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;

12
arch/arm/dts/tegra210-p2371-2180.dts
View file

@ -12,6 +12,8 @@
aliases {
i2c0 = "/i2c@7000d000";
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0000";
usb0 = "/usb@7d000000";
@ -85,6 +87,16 @@
non-removable;
};
i2c@7000c400 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;

147
arch/arm/dts/tegra210-p3450-0000.dts Normal file
View file

@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019-2020 NVIDIA Corporation <www.nvidia.com>
*/
/dts-v1/;
#include "tegra210.dtsi"
/ {
model = "NVIDIA Jetson Nano Developer Kit";
compatible = "nvidia,p3450-0000", "nvidia,tegra210";
chosen {
stdout-path = &uarta;
};
aliases {
ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
i2c0 = "/i2c@7000d000";
i2c2 = "/i2c@7000c400";
i2c3 = "/i2c@7000c500";
i2c4 = "/i2c@7000c700";
mmc0 = "/sdhci@700b0600";
mmc1 = "/sdhci@700b0000";
spi0 = "/spi@70410000";
usb0 = "/usb@7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
pcie@1003000 {
status = "okay";
pci@1,0 {
status = "okay";
};
pci@2,0 {
status = "okay";
ethernet@0,0 {
reg = <0x000000 0 0 0 0>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
serial@70006000 {
status = "okay";
};
padctl@7009f000 {
pinctrl-0 = <&padctl_default>;
pinctrl-names = "default";
padctl_default: pinmux {
xusb {
nvidia,lanes = "otg-1", "otg-2";
nvidia,function = "xusb";
nvidia,iddq = <0>;
};
usb3 {
nvidia,lanes = "pcie-5", "pcie-6";
nvidia,function = "usb3";
nvidia,iddq = <0>;
};
pcie-x1 {
nvidia,lanes = "pcie-0";
nvidia,function = "pcie-x1";
nvidia,iddq = <0>;
};
pcie-x4 {
nvidia,lanes = "pcie-1", "pcie-2",
"pcie-3", "pcie-4";
nvidia,function = "pcie-x4";
nvidia,iddq = <0>;
};
sata {
nvidia,lanes = "sata-0";
nvidia,function = "sata";
nvidia,iddq = <0>;
};
};
};
sdhci@700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
};
i2c@7000c400 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000c700 {
status = "okay";
clock-frequency = <400000>;
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
};
spi@70410000 {
status = "okay";
spi-max-frequency = <80000000>;
};
usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};

27
arch/arm/dts/zynq-cse-nor.dts
View file

@ -5,7 +5,6 @@
* Copyright (C) 2018 Xilinx, Inc.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
#address-cells = <1>;
@ -33,27 +32,21 @@
};
amba: amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
intc: interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xF8F01000 0x1000>,
<0xF8F00100 0x100>;
};
slcr: slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
clock-output-names = "armpll", "ddrpll",
@ -78,6 +71,20 @@
reg = <0x100 0x100>;
};
};
/*
* This is partially hack because it is normally subnode of smcc
* but for mini U-Boot there is no reason to enable SMCC driver
* which does almost nothing in NOR flash configuration that's
* why place cfi-flash directly here.
*/
flash@e2000000 {
u-boot,dm-pre-reloc;
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
};

10
arch/arm/dts/zynq-cse-qspi.dtsi
View file

@ -67,23 +67,23 @@
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@qspi-fsbl-uboot {
partition@0 {
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux {
partition@100000 {
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree {
partition@600000 {
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs {
partition@620000 {
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
partition@qspi-bitstream {
partition@c00000 {
label = "qspi-bitstream";
reg = <0xC00000 0x400000>;
};

10
arch/arm/dts/zynq-topic-miami.dts
View file

@ -44,23 +44,23 @@
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@qspi-u-boot-spl {
partition@0 {
label = "qspi-u-boot-spl";
reg = <0x00000 0x10000>;
};
partition@qspi-u-boot-img {
partition@10000 {
label = "qspi-u-boot-img";
reg = <0x10000 0x60000>;
};
partition@qspi-device-tree {
partition@70000 {
label = "qspi-device-tree";
reg = <0x70000 0x10000>;
};
partition@qspi-linux {
partition@80000 {
label = "qspi-linux";
reg = <0x80000 0x400000>;
};
partition@qspi-rootfs {
partition@480000 {
label = "qspi-rootfs";
reg = <0x480000 0x1b80000>;
};

12
arch/arm/dts/zynq-zc702.dts
View file

@ -181,17 +181,17 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
hwmon@52 {
hwmon@34 {
compatible = "ti,ucd9248";
reg = <52>;
reg = <0x34>;
};
hwmon@53 {
hwmon@35 {
compatible = "ti,ucd9248";
reg = <53>;
reg = <0x35>;
};
hwmon@54 {
hwmon@36 {
compatible = "ti,ucd9248";
reg = <54>;
reg = <0x36>;
};
};
};

2
arch/arm/dts/zynq-zc770-xm010.dts
View file

@ -72,7 +72,7 @@
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
flash@1 {
compatible = "sst25wf080", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <1000000>;

1
arch/arm/dts/zynq-zc770-xm011-x16.dts
View file

@ -1 +0,0 @@
zynq-zc770-xm011.dts

11
arch/arm/dts/zynq-zc770-xm011-x16.dts Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZC770 XM011 board DTS with NAND x16
*
* Copyright (C) 2013-2018 Xilinx, Inc.
*/
#include "zynq-zc770-xm011.dts"
/ {
model = "Xilinx ZC770 XM011 board (NAND x16)";
};

2
arch/arm/dts/zynq-zc770-xm011.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZC770 XM013 board DTS
* Xilinx ZC770 XM011 board DTS
*
* Copyright (C) 2013-2018 Xilinx, Inc.
*/

2
arch/arm/dts/zynq-zc770-xm013.dts
View file

@ -67,7 +67,7 @@
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
eeprom: eeprom@0 {
eeprom: eeprom@2 {
at25,byte-len = <8192>;
at25,addr-mode = <2>;
at25,page-size = <32>;

2
arch/arm/dts/zynq-zturn.dts
View file

@ -54,7 +54,7 @@
label = "K1";
gpios = <&gpio0 0x32 0x1>;
linux,code = <0x66>;
gpio-key,wakeup;
wakeup-source;
autorepeat;
};
};

12
arch/arm/dts/zynqmp-clk-ccf.dtsi
View file

@ -2,7 +2,7 @@
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2019, Xilinx, Inc.
* (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -284,10 +284,18 @@
clocks = <&zynqmp_clk AMS_REF>;
};
&zynqmp_dpsub {
clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;
};
&xlnx_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
&xlnx_dp_snd_codec0 {
&zynqmp_dp_snd_codec0 {
clocks = <&zynqmp_clk DP_AUDIO_REF>;
};
&zynqmp_pcap {
clocks = <&zynqmp_clk PCAP>;
};

244
arch/arm/dts/zynqmp-clk.dtsi
View file

@ -1,244 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
/ {
clk100: clk100 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
u-boot,dm-pre-reloc;
};
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
u-boot,dm-pre-reloc;
};
clk250: clk250 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
clk300: clk300 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
u-boot,dm-pre-reloc;
};
clk600: clk600 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
dp_aclk: clock0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-accuracy = <100>;
};
dp_aud_clk: clock1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
clock-accuracy = <100>;
};
dpdma_clk: dpdma-clk {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <533000000>;
};
drm_clock: drm-clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <262750000>;
clock-accuracy = <0x64>;
};
};
&can0 {
clocks = <&clk100 &clk100>;
};
&can1 {
clocks = <&clk100 &clk100>;
};
&fpd_dma_chan1 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan2 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan3 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan4 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan5 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan6 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan7 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan8 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan1 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan2 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan3 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan4 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan5 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan6 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan7 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan8 {
clocks = <&clk600>, <&clk100>;
};
&nand0 {
clocks = <&clk100 &clk100>;
};
&gem0 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem1 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem2 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem3 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gpio {
clocks = <&clk100>;
};
&i2c0 {
clocks = <&clk100>;
};
&i2c1 {
clocks = <&clk100>;
};
&qspi {
clocks = <&clk300 &clk300>;
};
&sata {
clocks = <&clk250>;
};
&sdhci0 {
clocks = <&clk200 &clk200>;
};
&sdhci1 {
clocks = <&clk200 &clk200>;
};
&spi0 {
clocks = <&clk200 &clk200>;
};
&spi1 {
clocks = <&clk200 &clk200>;
};
&uart0 {
clocks = <&clk100 &clk100>;
};
&uart1 {
clocks = <&clk100 &clk100>;
};
&usb0 {
clocks = <&clk250>, <&clk250>;
};
&usb1 {
clocks = <&clk250>, <&clk250>;
};
&watchdog0 {
clocks = <&clk100>;
};
&lpd_watchdog {
clocks = <&clk250>;
};
&xilinx_drm {
clocks = <&drm_clock>;
};
&xlnx_dp {
clocks = <&dp_aclk>, <&dp_aud_clk>;
};
&xlnx_dpdma {
clocks = <&dpdma_clk>;
};
&xlnx_dp_snd_codec0 {
clocks = <&dp_aud_clk>;
};

2
arch/arm/dts/zynqmp-mini-qspi.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP Mini Configuration
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>

10
arch/arm/dts/zynqmp-zc1232-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1232
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -48,19 +48,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};

10
arch/arm/dts/zynqmp-zc1254-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1254
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -48,19 +48,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};

34
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -108,19 +108,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
@ -154,7 +154,10 @@
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
/*
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio_bank = <1>;
};
@ -172,32 +175,23 @@
dr_mode = "host";
};
&xilinx_drm {
&zynqmp_dpsub {
status = "okay";
};
&xlnx_dp {
&zynqmp_dp_snd_pcm0 {
status = "okay";
};
&xlnx_dp_sub {
status = "okay";
xlnx,vid-clk-pl;
};
&xlnx_dp_snd_pcm0 {
&zynqmp_dp_snd_pcm1 {
status = "okay";
};
&xlnx_dp_snd_pcm1 {
&zynqmp_dp_snd_card0 {
status = "okay";
};
&xlnx_dp_snd_card {
status = "okay";
};
&xlnx_dp_snd_codec0 {
&zynqmp_dp_snd_codec0 {
status = "okay";
};

6
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -197,7 +197,7 @@
reg = <0>;
partition@0 {
label = "data";
label = "spi0-data";
reg = <0x0 0x100000>;
};
};
@ -214,7 +214,7 @@
reg = <0>;
partition@0 {
label = "data";
label = "spi1-data";
reg = <0x0 0x84000>;
};
};

2
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/

12
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -115,7 +115,7 @@
status = "okay";
};
&xlnx_dp {
&zynqmp_dpsub {
status = "okay";
};
@ -187,19 +187,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};

2
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>

2
arch/arm/dts/zynqmp-zcu100-revC.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Nathalie Chan King Choy

6
arch/arm/dts/zynqmp-zcu102-rev1.0.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.0
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -34,7 +34,3 @@
reg = <0xe0 0x3>;
};
};
&sdhci1 {
/delete-property/ no-1-8-v;
};

15
arch/arm/dts/zynqmp-zcu102-rev1.1.dts Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZCU102 Rev1.1
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include "zynqmp-zcu102-rev1.0.dts"
/ {
model = "ZynqMP ZCU102 Rev1.1";
compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};

36
arch/arm/dts/zynqmp-zcu102-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -614,19 +614,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
@ -655,7 +655,11 @@
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
no-1-8-v; /* for 1.0 silicon */
/*
* 1.0 revision has level shifter and this property should be
* removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio_bank = <1>;
};
@ -701,33 +705,23 @@
status = "okay";
};
&xilinx_drm {
status = "okay";
clocks = <&si570_1>;
};
&xlnx_dp {
&zynqmp_dpsub {
status = "okay";
};
&xlnx_dp_sub {
status = "okay";
xlnx,vid-clk-pl;
};
&xlnx_dp_snd_pcm0 {
&zynqmp_dp_snd_codec0 {
status = "okay";
};
&xlnx_dp_snd_pcm1 {
&zynqmp_dp_snd_pcm0 {
status = "okay";
};
&xlnx_dp_snd_card {
&zynqmp_dp_snd_pcm1 {
status = "okay";
};
&xlnx_dp_snd_codec0 {
&zynqmp_dp_snd_card0 {
status = "okay";
};

2
arch/arm/dts/zynqmp-zcu102-revB.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevB
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/

10
arch/arm/dts/zynqmp-zcu104-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -209,19 +209,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};

10
arch/arm/dts/zynqmp-zcu104-revC.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -222,19 +222,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};

14
arch/arm/dts/zynqmp-zcu106-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU106
*
* (C) Copyright 2016, Xilinx, Inc.
* (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -612,19 +612,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
@ -653,6 +653,10 @@
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
/*
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio_bank = <1>;
};

14
arch/arm/dts/zynqmp-zcu111-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -525,19 +525,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
@ -567,6 +567,10 @@
&sdhci1 {
status = "okay";
disable-wp;
/*
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio_bank = <1>;
};

10
arch/arm/dts/zynqmp-zcu1275-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -49,19 +49,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};

10
arch/arm/dts/zynqmp-zcu1275-revB.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU1275 RevB
*
* (C) Copyright 2018, Xilinx, Inc.
* (C) Copyright 2018 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -50,19 +50,19 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
partition@qspi-fsbl-uboot { /* for testing purpose */
partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};

6
arch/arm/dts/zynqmp-zcu1285-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU1285 RevA
*
* (C) Copyright 2018 - 2019, Xilinx, Inc.
* (C) Copyright 2018 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -241,5 +241,9 @@
&sdhci1 {
status = "okay";
/*
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio_bank = <1>;
};

8
arch/arm/dts/zynqmp-zcu208-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU208
*
* (C) Copyright 2017 - 2019, Xilinx, Inc.
* (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -50,7 +50,7 @@
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
gpio-key,wakeup;
wakeup-source;
autorepeat;
};
};
@ -563,6 +563,10 @@
&sdhci1 {
status = "okay";
disable-wp;
/*
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio_bank = <1>;
};

8
arch/arm/dts/zynqmp-zcu216-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU216
*
* (C) Copyright 2017 - 2019, Xilinx, Inc.
* (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -50,7 +50,7 @@
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
gpio-key,wakeup;
wakeup-source;
autorepeat;
};
};
@ -567,6 +567,10 @@
&sdhci1 {
status = "okay";
disable-wp;
/*
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
xlnx,mio_bank = <1>;
};

172
arch/arm/dts/zynqmp.dtsi
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP
*
* (C) Copyright 2014 - 2015, Xilinx, Inc.
* (C) Copyright 2014 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
@ -149,6 +149,11 @@
#power-domain-cells = <0x1>;
u-boot,dm-pre-reloc;
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
clock-names = "ref_clk";
};
zynqmp_power: zynqmp-power {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-power";
@ -162,6 +167,11 @@
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
pinctrl0: pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
status = "disabled";
};
};
};
@ -180,9 +190,10 @@
fpga_full: fpga-full {
compatible = "fpga-region";
fpga-mgr = <&pcap>;
fpga-mgr = <&zynqmp_pcap>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
nvmem_firmware {
@ -195,63 +206,6 @@
};
};
pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
rst: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
xlnx_dp_snd_card: dp_snd_card {
compatible = "xlnx,dp-snd-card";
status = "disabled";
xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
};
xlnx_dp_snd_codec0: dp_snd_codec0 {
compatible = "xlnx,dp-snd-codec";
status = "disabled";
clock-names = "aud_clk";
};
xlnx_dp_snd_pcm0: dp_snd_pcm0 {
compatible = "xlnx,dp-snd-pcm";
status = "disabled";
dmas = <&xlnx_dpdma 4>;
dma-names = "tx";
};
xlnx_dp_snd_pcm1: dp_snd_pcm1 {
compatible = "xlnx,dp-snd-pcm";
status = "disabled";
dmas = <&xlnx_dpdma 5>;
dma-names = "tx";
};
xilinx_drm: xilinx_drm {
compatible = "xlnx,drm";
status = "disabled";
xlnx,encoder-slave = <&xlnx_dp>;
xlnx,connector-type = "DisplayPort";
xlnx,dp-sub = <&xlnx_dp_sub>;
planes {
xlnx,pixel-format = "rgb565";
plane0 {
dmas = <&xlnx_dpdma 3>;
dma-names = "dma0";
};
plane1 {
dmas = <&xlnx_dpdma 0>,
<&xlnx_dpdma 1>,
<&xlnx_dpdma 2>;
dma-names = "dma0", "dma1", "dma2";
};
};
};
amba_apu: amba-apu@0 {
compatible = "simple-bus";
#address-cells = <2>;
@ -259,7 +213,7 @@
ranges = <0 0 0 0 0xffffffff>;
gic: interrupt-controller@f9010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
compatible = "arm,gic-400";
#interrupt-cells = <3>;
reg = <0x0 0xf9010000 0x10000>,
<0x0 0xf9020000 0x20000>,
@ -794,6 +748,8 @@
power-domains = <&zynqmp_firmware PD_SD_0>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
};
sdhci1: mmc@ff170000 {
@ -810,12 +766,8 @@
power-domains = <&zynqmp_firmware PD_SD_1>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
};
pinctrl0: pinctrl@ff180000 {
compatible = "xlnx,pinctrl-zynqmp";
status = "disabled";
reg = <0x0 0xff180000 0x0 0x1000>;
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
};
smmu: smmu@fd800000 {
@ -1015,37 +967,6 @@
};
};
xlnx_dp: dp@fd4a0000 {
compatible = "xlnx,v-dp";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>;
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "aclk", "aud_clk";
xlnx,dp-version = "v1.2";
xlnx,max-lanes = <2>;
xlnx,max-link-rate = <540000>;
xlnx,max-bpc = <16>;
xlnx,enable-ycrcb;
xlnx,colormetry = "rgb";
xlnx,bpc = <8>;
xlnx,audio-chan = <2>;
xlnx,dp-sub = <&xlnx_dp_sub>;
xlnx,max-pclock-frequency = <300000>;
};
xlnx_dp_sub: dp_sub@fd4aa000 {
compatible = "xlnx,dp-sub";
status = "disabled";
reg = <0x0 0xfd4aa000 0x0 0x1000>,
<0x0 0xfd4ab000 0x0 0x1000>,
<0x0 0xfd4ac000 0x0 0x1000>;
reg-names = "blend", "av_buf", "aud";
xlnx,output-fmt = "rgb";
xlnx,vid-fmt = "yuyv";
xlnx,gfx-fmt = "rgb565";
};
xlnx_dpdma: dma@fd4c0000 {
compatible = "xlnx,dpdma";
status = "disabled";
@ -1075,5 +996,62 @@
compatible = "xlnx,audio1";
};
};
zynqmp_dpsub: zynqmp-display@fd4a0000 {
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>,
<0x0 0xfd4aa000 0x0 0x1000>,
<0x0 0xfd4ab000 0x0 0x1000>,
<0x0 0xfd4ac000 0x0 0x1000>;
reg-names = "dp", "blend", "av_buf", "aud";
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
vid-layer {
dma-names = "vid0", "vid1", "vid2";
dmas = <&xlnx_dpdma 0>,
<&xlnx_dpdma 1>,
<&xlnx_dpdma 2>;
};
gfx-layer {
dma-names = "gfx0";
dmas = <&xlnx_dpdma 3>;
};
/* dummy node to indicate there's no child i2c device */
i2c-bus {
};
zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
compatible = "xlnx,dp-snd-codec";
clock-names = "aud_clk";
};
zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
compatible = "xlnx,dp-snd-pcm";
dmas = <&xlnx_dpdma 4>;
dma-names = "tx";
};
zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
compatible = "xlnx,dp-snd-pcm";
dmas = <&xlnx_dpdma 5>;
dma-names = "tx";
};
zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
compatible = "xlnx,dp-snd-card";
xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
<&zynqmp_dp_snd_pcm1>;
xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
};
};
};
};

11
arch/arm/include/asm/arch-rockchip/vop_rk3288.h
View file

@ -85,6 +85,16 @@ enum {
LB_RGB_1280X8 = 0x5
};
#if defined(CONFIG_ROCKCHIP_RK3399)
enum vop_modes {
VOP_MODE_EDP = 0,
VOP_MODE_MIPI,
VOP_MODE_HDMI,
VOP_MODE_MIPI1,
VOP_MODE_DP,
VOP_MODE_NONE,
};
#else
enum vop_modes {
VOP_MODE_EDP = 0,
VOP_MODE_HDMI,
@ -94,6 +104,7 @@ enum vop_modes {
VOP_MODE_AUTO_DETECT,
VOP_MODE_UNKNOWN,
};
#endif
/* VOP_VERSION_INFO */
#define M_FPGA_VERSION (0xffff << 16)

20
arch/arm/include/asm/arch-tegra/tegra_mmc.h
View file

@ -2,7 +2,7 @@
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Portions Copyright (C) 2011-2012 NVIDIA Corporation
* Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
*/
#ifndef __TEGRA_MMC_H_
@ -52,7 +52,7 @@ struct tegra_mmc {
unsigned char admaerr; /* offset 54h */
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
unsigned long admaaddr; /* offset 58h-5Fh */
unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
unsigned short slotintstatus; /* offset FCh */
unsigned short hcver; /* HOST Version */
unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
@ -127,11 +127,23 @@ struct tegra_mmc {
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
/* SDMMC1/3 settings from section 24.6 of T30 TRM */
/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
#define MEMCOMP_PADCTRL_VREF 7
#define AUTO_CAL_ENABLED (1 << 29)
#define AUTO_CAL_ENABLE (1 << 29)
#define AUTO_CAL_ACTIVE (1 << 31)
#define AUTO_CAL_START (1 << 31)
#if defined(CONFIG_TEGRA210)
#define AUTO_CAL_PD_OFFSET (0x7D << 8)
#define AUTO_CAL_PU_OFFSET (0 << 0)
#define IO_TRIM_BYPASS_MASK (1 << 2)
#define TRIM_VAL_SHIFT 24
#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
#define TAP_VAL_SHIFT 16
#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
#else
#define AUTO_CAL_PD_OFFSET (0x70 << 8)
#define AUTO_CAL_PU_OFFSET (0x62 << 0)
#endif
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA_MMC_H_ */

1
arch/arm/include/asm/arch-tegra/xusb-padctl.h
View file

@ -16,6 +16,7 @@ struct tegra_xusb_phy;
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
void tegra_xusb_padctl_init(void);
void tegra_xusb_padctl_exit(void);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);

3
arch/arm/include/asm/gpio.h
View file

@ -4,7 +4,8 @@
!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
!defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
!defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
!defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_U8500) && \
!defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
!defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \
!defined(CONFIG_CORTINA_PLATFORM)
#include <asm/arch/gpio.h>
#endif

1
arch/arm/mach-rockchip/Kconfig
View file

@ -229,6 +229,7 @@ config ROCKCHIP_RK3399
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ROCKCHIP_COMMON_BOARD

2
arch/arm/mach-snapdragon/misc.c
View file

@ -41,7 +41,7 @@ void msm_generate_mac_addr(u8 *mac)
int i;
char sn[9];
snprintf(sn, 8, "%08x", msm_board_serial());
snprintf(sn, 9, "%08x", msm_board_serial());
/* fill in the mac with serialno, use locally adminstrated pool */
mac[0] = 0x02;

2
arch/arm/mach-socfpga/include/mach/base_addr_a10.h
View file

@ -47,4 +47,6 @@
#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400
#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500
#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000
#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */

2
arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
View file

@ -59,4 +59,6 @@
#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000
#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000
#define SOCFPGA_PHYS_OCRAM_SIZE 0x10000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */

32
arch/arm/mach-socfpga/spl_a10.c
View file

@ -33,6 +33,38 @@
DECLARE_GLOBAL_DATA_PTR;
#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
SOCFPGA_PHYS_OCRAM_SIZE - \
BOOTROM_SHARED_MEM_SIZE)
#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
static u32 rst_mgr_status __section(.data);
/*
* Bootrom will clear the status register in reset manager and stores the
* reset status value in shared memory. Bootrom stores shared data at last
* 2KB of onchip RAM.
* This function save reset status provided by BootROM to rst_mgr_status.
* More information about reset status register value can be found in reset
* manager register description.
* When running in debugger without Bootrom, r0 to r3 are random values.
* So, skip save the value when r0 is not BootROM shared data address.
*
* r0 - Contains the pointer to the shared memory block. The shared
* memory block is located in the top 2 KB of on-chip RAM.
* r1 - contains the length of the shared memory.
* r2 - unused and set to 0x0.
* r3 - points to the version block.
*/
void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
unsigned long r3)
{
if (r0 == BOOTROM_SHARED_MEM_ADDR)
rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
save_boot_params_ret();
}
u32 spl_boot_device(void)
{
const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);

2
arch/arm/mach-sunxi/Kconfig
View file

@ -994,7 +994,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does

153
arch/arm/mach-sunxi/spl_spi_sunxi.c
View file

@ -36,13 +36,13 @@
/* SUN4I variant of the SPI controller */
/*****************************************************************************/
#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C)
#define SUN4I_SPI0_CTL (0x01C05000 + 0x08)
#define SUN4I_SPI0_RX (0x01C05000 + 0x00)
#define SUN4I_SPI0_TX (0x01C05000 + 0x04)
#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28)
#define SUN4I_SPI0_BC (0x01C05000 + 0x20)
#define SUN4I_SPI0_TC (0x01C05000 + 0x24)
#define SUN4I_SPI0_CCTL 0x1C
#define SUN4I_SPI0_CTL 0x08
#define SUN4I_SPI0_RX 0x00
#define SUN4I_SPI0_TX 0x04
#define SUN4I_SPI0_FIFO_STA 0x28
#define SUN4I_SPI0_BC 0x20
#define SUN4I_SPI0_TC 0x24
#define SUN4I_CTL_ENABLE BIT(0)
#define SUN4I_CTL_MASTER BIT(1)
@ -54,15 +54,15 @@
/* SUN6I variant of the SPI controller */
/*****************************************************************************/
#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
#define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
#define SUN6I_SPI0_TCR (0x01C68000 + 0x08)
#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C)
#define SUN6I_SPI0_MBC (0x01C68000 + 0x30)
#define SUN6I_SPI0_MTC (0x01C68000 + 0x34)
#define SUN6I_SPI0_BCC (0x01C68000 + 0x38)
#define SUN6I_SPI0_TXD (0x01C68000 + 0x200)
#define SUN6I_SPI0_RXD (0x01C68000 + 0x300)
#define SUN6I_SPI0_CCTL 0x24
#define SUN6I_SPI0_GCR 0x04
#define SUN6I_SPI0_TCR 0x08
#define SUN6I_SPI0_FIFO_STA 0x1C
#define SUN6I_SPI0_MBC 0x30
#define SUN6I_SPI0_MTC 0x34
#define SUN6I_SPI0_BCC 0x38
#define SUN6I_SPI0_TXD 0x200
#define SUN6I_SPI0_RXD 0x300
#define SUN6I_CTL_ENABLE BIT(0)
#define SUN6I_CTL_MASTER BIT(1)
@ -72,7 +72,12 @@
/*****************************************************************************/
#define CCM_AHB_GATING0 (0x01C20000 + 0x60)
#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c)
#ifdef CONFIG_MACH_SUN50I_H6
#define CCM_SPI0_CLK (0x03001000 + 0x940)
#else
#define CCM_SPI0_CLK (0x01C20000 + 0xA0)
#endif
#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
#define AHB_RESET_SPI0_SHIFT 20
@ -86,74 +91,111 @@
/*
* Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
* from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
* The H6 uses PC0, PC2, PC3, PC5.
*/
static void spi0_pinmux_setup(unsigned int pin_function)
{
unsigned int pin;
/* All chips use PC0 and PC2. */
sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
sunxi_gpio_set_cfgpin(pin, pin_function);
/* All chips except H6 use PC1, and only H6 uses PC5. */
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
else
sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
/* Older generations use PC23 for CS, newer ones use PC3. */
if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
IS_ENABLED(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
else
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
}
static bool is_sun6i_gen_spi(void)
{
return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6);
}
static uintptr_t spi0_base_address(void)
{
if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
return 0x01C05000;
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
return 0x05010000;
if (!is_sun6i_gen_spi())
return 0x01C05000;
return 0x01C68000;
}
/*
* Setup 6 MHz from OSC24M (because the BROM is doing the same).
*/
static void spi0_enable_clock(void)
{
uintptr_t base = spi0_base_address();
/* Deassert SPI0 reset on SUN6I */
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
else if (is_sun6i_gen_spi())
setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
(1 << AHB_RESET_SPI0_SHIFT));
/* Open the SPI0 gate */
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Divide by 4 */
writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL);
writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
/* 24MHz from OSC24M */
writel((1 << 31), CCM_SPI0_CLK);
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
if (is_sun6i_gen_spi()) {
/* Enable SPI in the master mode and do a soft reset */
setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
SUN6I_CTL_ENABLE |
SUN6I_CTL_SRST);
setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
/* Wait for completion */
while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
;
} else {
/* Enable SPI in the master mode and reset FIFO */
setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
SUN4I_CTL_ENABLE |
SUN4I_CTL_TF_RST |
SUN4I_CTL_RF_RST);
setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
SUN4I_CTL_ENABLE |
SUN4I_CTL_TF_RST |
SUN4I_CTL_RF_RST);
}
}
static void spi0_disable_clock(void)
{
uintptr_t base = spi0_base_address();
/* Disable the SPI0 controller */
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
if (is_sun6i_gen_spi())
clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
SUN6I_CTL_ENABLE);
else
clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
SUN4I_CTL_ENABLE);
/* Disable the SPI0 clock */
writel(0, CCM_SPI0_CLK);
/* Close the SPI0 gate */
clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Assert SPI0 reset on SUN6I */
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
else if (is_sun6i_gen_spi())
clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
(1 << AHB_RESET_SPI0_SHIFT));
}
@ -162,7 +204,8 @@ static void spi0_init(void)
{
unsigned int pin_function = SUNXI_GPC_SPI0;
if (IS_ENABLED(CONFIG_MACH_SUN50I))
if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6))
pin_function = SUN50I_GPC_SPI0;
spi0_pinmux_setup(pin_function);
@ -173,7 +216,8 @@ static void spi0_deinit(void)
{
/* New SoCs can disable pins, older could only set them as input */
unsigned int pin_function = SUNXI_GPIO_INPUT;
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
if (is_sun6i_gen_spi())
pin_function = SUNXI_GPIO_DISABLE;
spi0_disable_clock();
@ -227,31 +271,32 @@ static void spi0_read_data(void *buf, u32 addr, u32 len)
{
u8 *buf8 = buf;
u32 chunk_len;
uintptr_t base = spi0_base_address();
while (len > 0) {
chunk_len = len;
if (chunk_len > SPI_READ_MAX_SIZE)
chunk_len = SPI_READ_MAX_SIZE;
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
if (is_sun6i_gen_spi()) {
sunxi_spi0_read_data(buf8, addr, chunk_len,
SUN6I_SPI0_TCR,
base + SUN6I_SPI0_TCR,
SUN6I_TCR_XCH,
SUN6I_SPI0_FIFO_STA,
SUN6I_SPI0_TXD,
SUN6I_SPI0_RXD,
SUN6I_SPI0_MBC,
SUN6I_SPI0_MTC,
SUN6I_SPI0_BCC);
base + SUN6I_SPI0_FIFO_STA,
base + SUN6I_SPI0_TXD,
base + SUN6I_SPI0_RXD,
base + SUN6I_SPI0_MBC,
base + SUN6I_SPI0_MTC,
base + SUN6I_SPI0_BCC);
} else {
sunxi_spi0_read_data(buf8, addr, chunk_len,
SUN4I_SPI0_CTL,
base + SUN4I_SPI0_CTL,
SUN4I_CTL_XCH,
SUN4I_SPI0_FIFO_STA,
SUN4I_SPI0_TX,
SUN4I_SPI0_RX,
SUN4I_SPI0_BC,
SUN4I_SPI0_TC,
base + SUN4I_SPI0_FIFO_STA,
base + SUN4I_SPI0_TX,
base + SUN4I_SPI0_RX,
base + SUN4I_SPI0_BC,
base + SUN4I_SPI0_TC,
0);
}

31
arch/arm/mach-tegra/board2.c
View file

@ -181,6 +181,12 @@ int board_init(void)
return nvidia_board_init();
}
void board_cleanup_before_linux(void)
{
/* power down UPHY PLL */
tegra_xusb_padctl_exit();
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
static void __gpio_early_init(void)
{
@ -211,6 +217,31 @@ int board_early_init_f(void)
arch_timer_init();
#endif
#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
/*
* Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
* We do this because earlier bootloaders have enabled power to
* SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
* results in power being back-driven into the SD-card and SDMMC1
* HW, which is 'bad' as per the HW team.
*
* From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
* nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
* table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
* the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
* voltage turns off. Since the SDCard voltage is no longer there, the
* SDMMC CLK/DAT lines are backdriving into what essentially is a
* powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
*
* Note that this can probably be removed when we change over to storing
* all BL components on QSPI on Nano, and U-Boot then becomes the first
* one to turn on SDMMC1 power. Another fix would be to have CBoot
* disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
*/
reset_set_enable(PERIPH_ID_SDMMC1, 1);
clock_set_enable(PERIPH_ID_SDMMC1, 0);
#endif /* CONFIG_DISABLE_SDMMC1_EARLY */
pinmux_init();
board_init_uart_f();

7
arch/arm/mach-tegra/tegra210/Kconfig
View file

@ -35,6 +35,12 @@ config TARGET_P2571
help
P2571 is a P2530 married to a P1963 I/O board
config TARGET_P3450_0000
bool "NVIDIA Jetson Nano Developer Kit"
select BOARD_LATE_INIT
help
P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
endchoice
config SYS_SOC
@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig"
source "board/nvidia/p2371-0000/Kconfig"
source "board/nvidia/p2371-2180/Kconfig"
source "board/nvidia/p2571/Kconfig"
source "board/nvidia/p3450-0000/Kconfig"
endif

3
arch/arm/mach-tegra/tegra210/Makefile
View file

@ -1,5 +1,5 @@
#
# (C) Copyright 2013-2015
# (C) Copyright 2013-2020
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
@ -7,6 +7,5 @@
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o

27
arch/arm/mach-tegra/tegra210/clock.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013-2015
* (C) Copyright 2013-2020
* NVIDIA Corporation <www.nvidia.com>
*/
@ -333,7 +333,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE),
TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16),
TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
@ -739,7 +739,7 @@ int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
if (!clock_periph_id_isvalid(periph_id))
return -1;
internal_id = periph_id_to_internal_id[periph_id];
internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
if (!periphc_internal_id_isvalid(internal_id))
return -1;
@ -765,7 +765,7 @@ enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
internal_id = periph_id_to_internal_id[periph_id];
internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
@ -1235,25 +1235,6 @@ int tegra_plle_enable(void)
value &= ~PLLE_SS_CNTL_INTERP_RESET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
/* 7. Enable HW power sequencer for PLLE */
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
value &= ~PLLE_MISC_IDDQ_SWCTL;
writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
value &= ~PLLE_AUX_SS_SWCTL;
value &= ~PLLE_AUX_ENABLE_SWCTL;
value |= PLLE_AUX_SS_SEQ_INCLUDE;
value |= PLLE_AUX_USE_LOCKDET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
/* 8. Wait 1 us */
udelay(1);
value |= PLLE_AUX_SEQ_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
return 0;
}

194
arch/arm/mach-tegra/tegra210/pinmux.c
View file

@ -1,194 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
#define PIN(pin, f0, f1, f2, f3) \
{ \
.funcs = { \
PMUX_FUNC_##f0, \
PMUX_FUNC_##f1, \
PMUX_FUNC_##f2, \
PMUX_FUNC_##f3, \
}, \
}
#define PIN_RESERVED {}
static const struct pmux_pingrp_desc tegra210_pingroups[] = {
/* pin, f0, f1, f2, f3 */
/* Offset 0x3000 */
PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x301c */
PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x3038 */
PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
PIN_RESERVED,
/* Offset 0x30a4 */
PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;

68
arch/arm/mach-tegra/tegra210/xusb-padctl.c
View file

@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
return tegra_xusb_padctl_disable(phy->padctl);
}
#define XUSB_PADCTL_USB3_PAD_MUX 0x28
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
udelay(1);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
debug("< %s()\n", __func__);
return 0;
}
@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void)
ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
debug("%s: done, ret=%d\n", __func__, ret);
}
void tegra_xusb_padctl_exit(void)
{
u32 value;
debug("> %s\n", __func__);
value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
while (padctl.enable)
tegra_xusb_padctl_disable(&padctl);
debug("< %s()\n", __func__);
}

4
arch/arm/mach-tegra/xusb-padctl-dummy.c
View file

@ -36,3 +36,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
void __weak tegra_xusb_padctl_init(void)
{
}
void __weak tegra_xusb_padctl_exit(void)
{
}

6
arch/arm/mach-versal/Kconfig
View file

@ -56,4 +56,10 @@ config DEFINE_TCM_OCM_MMAP
This option if enabled defines the TCM and OCM memory and its
memory attributes in MMU table entry.
config VERSAL_NO_DDR
bool "Disable DDR MMU mapping"
help
This option configures MMU with no DDR to avoid speculative
access to DDR memory where DDR is not present.
endif

9
arch/arm/mach-versal/cpu.c
View file

@ -81,6 +81,15 @@ void mem_map_fill(void)
if (!gd->bd->bi_dram[i].size)
break;
#if defined(CONFIG_VERSAL_NO_DDR)
if (gd->bd->bi_dram[i].start < 0x80000000UL ||
gd->bd->bi_dram[i].start > 0x100000000UL) {
printf("Ignore caches over %llx/%llx\n",
gd->bd->bi_dram[i].start,
gd->bd->bi_dram[i].size);
continue;
}
#endif
versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
versal_mem_map[banks].size = gd->bd->bi_dram[i].size;

10
arch/arm/mach-zynq/spl.c
View file

@ -6,6 +6,7 @@
#include <debug_uart.h>
#include <hang.h>
#include <spl.h>
#include <generated/dt.h>
#include <asm/io.h>
#include <asm/spl.h>
@ -44,7 +45,6 @@ u32 spl_boot_device(void)
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
#ifdef CONFIG_SPL_SPI_SUPPORT
case ZYNQ_BM_QSPI:
puts("qspi boot\n");
mode = BOOT_DEVICE_SPI;
break;
#endif
@ -56,7 +56,6 @@ u32 spl_boot_device(void)
break;
#ifdef CONFIG_SPL_MMC_SUPPORT
case ZYNQ_BM_SD:
puts("mmc boot\n");
mode = BOOT_DEVICE_MMC1;
break;
#endif
@ -89,8 +88,11 @@ void spl_board_prepare_for_boot(void)
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE);
return 0;
if (!strcmp(name, DEVICE_TREE))
return 0;
return -1;
}
#endif

4
arch/arm/mach-zynqmp/include/mach/hardware.h
View file

@ -128,7 +128,9 @@ struct apu_regs {
#define ZYNQMP_SILICON_VER_SHIFT 12
struct csu_regs {
u32 reserved0[17];
u32 reserved0[4];
u32 multi_boot;
u32 reserved1[12];
u32 version;
};

23
arch/arm/mach-zynqmp/mkimage_fit_atf.sh
View file

@ -29,11 +29,8 @@ else
fi
if [ ! -f $BL31 ]; then
echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
echo "WARNING: BL31 file $BL31 NOT found, U-Boot will run in EL3" >&2
BL31=/dev/null
# But U-Boot proper could be loaded in EL3 by specifying
# firmware = "uboot";
# instead of "atf" in config node
fi
cat << __HEADER_EOF
@ -58,6 +55,10 @@ cat << __HEADER_EOF
algo = "md5";
};
};
__HEADER_EOF
if [ -f $BL31 ]; then
cat << __ATF
atf {
description = "ARM Trusted Firmware";
data = /incbin/("$BL31");
@ -71,7 +72,8 @@ cat << __HEADER_EOF
algo = "md5";
};
};
__HEADER_EOF
__ATF
fi
DEFAULT=1
cnt=1
@ -106,6 +108,15 @@ __CONF_HEADER_EOF
cnt=1
for dtname in $DT
do
if [ ! -f $BL31 ]; then
cat << __CONF_SECTION1_EOF
config_$cnt {
description = "$(basename $dtname .dtb)";
firmware = "uboot";
fdt = "fdt_$cnt";
};
__CONF_SECTION1_EOF
else
cat << __CONF_SECTION1_EOF
config_$cnt {
description = "$(basename $dtname .dtb)";
@ -114,6 +125,8 @@ cat << __CONF_SECTION1_EOF
fdt = "fdt_$cnt";
};
__CONF_SECTION1_EOF
fi
cnt=$((cnt+1))
done

11
arch/arm/mach-zynqmp/spl.c
View file

@ -6,7 +6,6 @@
*/
#include <common.h>
#include <debug_uart.h>
#include <init.h>
#include <spl.h>
@ -20,14 +19,6 @@ void board_init_f(ulong dummy)
{
board_early_init_f();
board_early_init_r();
#ifdef CONFIG_DEBUG_UART
/* Uart debug for sure */
debug_uart_init();
puts("Debug uart enabled\n"); /* or printch() */
#endif
/* Delay is required for clocks to be propagated */
udelay(1000000);
}
static void ps_mode_reset(ulong mode)
@ -66,6 +57,8 @@ void board_boot_order(u32 *spl_boot_list)
spl_boot_list[1] = BOOT_DEVICE_MMC2;
if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
spl_boot_list[1] = BOOT_DEVICE_MMC1;
spl_boot_list[2] = BOOT_DEVICE_RAM;
}
u32 spl_boot_device(void)

1
arch/mips/config.mk
View file

@ -36,7 +36,6 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000
endif
PLATFORM_CPPFLAGS += -D__MIPS__
PLATFORM_ELFENTRY = "__start"
PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS)
#

7
arch/powerpc/dts/gdsys/mpc8308.dtsi
View file

@ -17,6 +17,7 @@
/dts-v1/;
#include <dt-bindings/memory/mpc83xx-sdram.h>
#include <dt-bindings/clk/mpc83xx-clk.h>
/ {
compatible = "fsl,mpc8308rdb";
@ -50,6 +51,11 @@
};
};
socclocks: clocks {
compatible = "fsl,mpc8308-clk";
#clock-cells = <1>;
};
board_lbc: localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
@ -173,6 +179,7 @@
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
clocks = <&socclocks MPC83XX_CLK_CSB>;
mode = "cpu";
};

9
arch/u-boot-elf.lds Normal file
View file

@ -0,0 +1,9 @@
ENTRY(CONFIG_PLATFORM_ELFENTRY)
SECTIONS
{
. = CONFIG_PLATFORM_ELFENTRY;
.data : {
*(.data*)
}
}

77
arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
View file

@ -240,6 +240,21 @@ Device (PCI0)
Return (STA_VISIBLE)
}
Name (SSCN, Package ()
{
0x02F8, 0x037B, Zero,
})
Name (FMCN, Package ()
{
0x0087, 0x010A, Zero,
})
Name (HSCN, Package ()
{
0x0008, 0x0020, Zero,
})
Name (RBUF, ResourceTemplate()
{
FixedDMA(0x0009, 0x0000, Width32bit, )
@ -260,6 +275,21 @@ Device (PCI0)
{
Return (STA_VISIBLE)
}
Name (SSCN, Package ()
{
0x02F8, 0x037B, Zero,
})
Name (FMCN, Package ()
{
0x0087, 0x010A, Zero,
})
Name (HSCN, Package ()
{
0x0008, 0x0020, Zero,
})
}
Device (GPIO)
@ -291,6 +321,53 @@ Device (PCI0)
}
}
Device (DWC3)
{
Name (_ADR, 0x00110000)
Name (_DEP, Package ()
{
^IPC1.PMIC
})
Method (_STA, 0, NotSerialized)
{
Return (STA_VISIBLE)
}
Device (RHUB)
{
Name (_ADR, Zero)
/* GPLD: Generate Port Location Data (PLD) */
Method (GPLD, 1, Serialized) {
Name (PCKG, Package () {
Buffer (0x14) {}
})
/* REV: Revision 0x02 for ACPI 5.0 */
CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
Store (0x0002, REV)
/* VISI: Port visibility to user per port */
CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
Store (Arg0, VISI)
/* VOFF: Vertical offset is not supplied */
CreateField (DerefOf (Index (PCKG, Zero)), 0x80, 0x10, VOFF)
Store (0xFFFF, VOFF)
/* HOFF: Horizontal offset is not supplied */
CreateField (DerefOf (Index (PCKG, Zero)), 0x90, 0x10, HOFF)
Store (0xFFFF, HOFF)
Return (PCKG)
}
Device (HS01) { Name (_ADR, 1) }
Device (SS01) { Name (_ADR, 2) }
}
}
Device (PWM0)
{
Name (_ADR, 0x00170000)

33
arch/x86/lib/acpi_table.c
View file

@ -109,14 +109,11 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
{
int i, entries_num;
struct acpi_rsdt *rsdt;
struct acpi_xsdt *xsdt = NULL;
struct acpi_xsdt *xsdt;
/* The RSDT is mandatory while the XSDT is not */
rsdt = (struct acpi_rsdt *)rsdp->rsdt_address;
if (rsdp->xsdt_address)
xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address);
/* This should always be MAX_ACPI_TABLES */
entries_num = ARRAY_SIZE(rsdt->entry);
@ -135,30 +132,34 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
/* Fix RSDT length or the kernel will assume invalid entries */
rsdt->header.length = sizeof(struct acpi_table_header) +
(sizeof(u32) * (i + 1));
sizeof(u32) * (i + 1);
/* Re-calculate checksum */
rsdt->header.checksum = 0;
rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
rsdt->header.length);
/* The RSDT is mandatory while the XSDT is not */
if (!rsdp->xsdt_address)
return;
/*
* And now the same thing for the XSDT. We use the same index as for
* now we want the XSDT and RSDT to always be in sync in U-Boot
*/
if (xsdt) {
/* Add table to the XSDT */
xsdt->entry[i] = (u64)(u32)table;
xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address);
/* Fix XSDT length */
xsdt->header.length = sizeof(struct acpi_table_header) +
(sizeof(u64) * (i + 1));
/* Add table to the XSDT */
xsdt->entry[i] = (u64)(u32)table;
/* Re-calculate checksum */
xsdt->header.checksum = 0;
xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
xsdt->header.length);
}
/* Fix XSDT length */
xsdt->header.length = sizeof(struct acpi_table_header) +
sizeof(u64) * (i + 1);
/* Re-calculate checksum */
xsdt->header.checksum = 0;
xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
xsdt->header.length);
}
static void acpi_create_facs(struct acpi_facs *facs)

15
board/dhelectronics/dh_stm32mp1/board.c
View file

@ -78,22 +78,21 @@ DECLARE_GLOBAL_DATA_PTR;
int setup_mac_address(void)
{
struct udevice *dev;
ofnode eeprom;
unsigned char enetaddr[6];
int ret;
struct udevice *dev;
int off, ret;
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
if (ret) /* ethaddr is already set */
return 0;
eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50");
if (!ofnode_valid(eeprom)) {
printf("Invalid hardware path to EEPROM!\n");
return -ENODEV;
off = fdt_path_offset(gd->fdt_blob, "eeprom0");
if (off < 0) {
printf("%s: No eeprom0 path offset\n", __func__);
return off;
}
ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
if (ret) {
printf("Cannot find EEPROM!\n");
return ret;

2
board/freescale/ls1012ardb/Kconfig
View file

@ -35,7 +35,7 @@ config SYS_LS_PFE_FW_ADDR
config SYS_LS_PFE_ESBC_ADDR
hex "PFE Firmware HDR Addr"
default 0x40700000
default 0x40640000
config DDR_PFE_PHYS_BASEADDR
hex "PFE DDR physical base address"

98
board/freescale/ls1043aqds/ls1043aqds.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
#include <common.h>
@ -271,11 +272,24 @@ unsigned long get_board_ddr_clk(void)
return 66666666;
}
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -290,8 +304,10 @@ int dram_init(void)
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
*
* PCA9547 mount on I2C1 bus
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
@ -304,16 +320,83 @@ int dram_init(void)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
return select_i2c_ch_pca9547(channel);
return select_i2c_ch_pca9547(channel, 0);
}
void board_retimer_init(void)
{
u8 reg;
int bus_num = 0;
/* Retimer is connected to I2C1_CH7_CH5 */
select_i2c_ch_pca9547(I2C_MUX_CH7);
select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
reg = I2C_MUX_CH5;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return;
}
dm_i2c_write(dev, 0, &reg, 1);
/* Access to Control/Shared register */
ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return;
}
reg = 0x0;
dm_i2c_write(dev, 0xff, &reg, 1);
/* Read device revision and ID */
dm_i2c_read(dev, 1, &reg, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
dm_i2c_write(dev, 0xff, &reg, 1);
/* Reset Channel Registers */
dm_i2c_read(dev, 0, &reg, 1);
reg |= 0x4;
dm_i2c_write(dev, 0, &reg, 1);
/* Enable override divider select and Enable Override Output Mux */
dm_i2c_read(dev, 9, &reg, 1);
reg |= 0x24;
dm_i2c_write(dev, 9, &reg, 1);
/* Select VCO Divider to full rate (000) */
dm_i2c_read(dev, 0x18, &reg, 1);
reg &= 0x8f;
dm_i2c_write(dev, 0x18, &reg, 1);
/* Selects active PFD MUX Input as Re-timed Data (001) */
dm_i2c_read(dev, 0x1e, &reg, 1);
reg &= 0x3f;
reg |= 0x20;
dm_i2c_write(dev, 0x1e, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x0;
dm_i2c_write(dev, 0x60, &reg, 1);
reg = 0xb2;
dm_i2c_write(dev, 0x61, &reg, 1);
reg = 0x90;
dm_i2c_write(dev, 0x62, &reg, 1);
reg = 0xb3;
dm_i2c_write(dev, 0x63, &reg, 1);
reg = 0xcd;
dm_i2c_write(dev, 0x64, &reg, 1);
#else
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
/* Access to Control/Shared register */
@ -360,9 +443,10 @@ void board_retimer_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
#endif
/* Return the default channel */
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
}
int board_early_init_f(void)
@ -375,8 +459,10 @@ int board_early_init_f(void)
u8 uart;
#endif
#ifdef CONFIG_SYS_I2C
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
#endif
fsl_lsch2_early_init_f();
@ -457,7 +543,7 @@ int board_init(void)
erratum_a010315();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
#ifdef CONFIG_SYS_FSL_SERDES

17
board/freescale/ls1046afrwy/ls1046afrwy.c
View file

@ -36,11 +36,24 @@
DECLARE_GLOBAL_DATA_PTR;
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -149,7 +162,7 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
sec_init();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}

25
board/freescale/ls1046aqds/ls1046aqds.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
#include <common.h>
@ -269,11 +270,23 @@ u32 get_lpuart_clk(void)
}
#endif
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -288,8 +301,10 @@ int dram_init(void)
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
*
* PCA9547 mount on I2C1 bus
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
@ -302,7 +317,7 @@ int dram_init(void)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
return select_i2c_ch_pca9547(channel);
return select_i2c_ch_pca9547(channel, 0);
}
int board_early_init_f(void)
@ -315,8 +330,10 @@ int board_early_init_f(void)
u8 uart;
#endif
#ifdef CONFIG_SYS_I2C
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
#endif
fsl_lsch2_early_init_f();
@ -394,7 +411,7 @@ int misc_init_r(void)
int board_init(void)
{
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();

48
board/freescale/lx2160a/lx2160a.c
View file

@ -29,11 +29,14 @@
#include "../common/vid.h"
#include <fsl_immap.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <asm/gic-v3.h>
#include <cpu_func.h>
#ifdef CONFIG_EMC2305
#include "../common/emc2305.h"
#endif
#define GIC_LPI_SIZE 0x200000
#ifdef CONFIG_TARGET_LX2160AQDS
#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
@ -149,6 +152,7 @@ int board_fix_fdt(void *fdt)
reg_name = reg_names;
remaining_names_len = names_len - (reg_name - reg_names);
i = 0;
while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
old_name_len = strlen(reg_names_map[i].old_str);
new_name_len = strlen(reg_names_map[i].new_str);
@ -274,7 +278,14 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
int init_func_vid(void)
{
if (adjust_vdd(0) < 0)
int set_vid;
if (IS_SVR_REV(get_svr(), 1, 0))
set_vid = adjust_vdd(800);
else
set_vid = adjust_vdd(0);
if (set_vid < 0)
printf("core voltage not adjusted\n");
return 0;
@ -469,10 +480,16 @@ int config_board_mux(void)
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
QIXIS_WRITE(brdcfg[11], reg11);
} else {
/* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
/*
* If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
* do not change it.
* Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
*/
reg11 = QIXIS_READ(brdcfg[11]);
reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
QIXIS_WRITE(brdcfg[11], reg11);
if ((reg11 & 0x30) != 0x30) {
reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
QIXIS_WRITE(brdcfg[11], reg11);
}
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
* {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
@ -627,8 +644,22 @@ void board_quiesce_devices(void)
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
#ifdef CONFIG_GIC_V3_ITS
void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
{
u32 phandle;
int err;
struct fdt_memory gic_lpi;
gic_lpi.start = gic_lpi_base;
gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
if (err < 0)
debug("failed to add reserved memory: %d\n", err);
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
@ -639,6 +670,7 @@ int ft_board_setup(void *blob, bd_t *bd)
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
u64 gic_lpi_base;
ft_cpu_setup(blob, bd);
@ -658,6 +690,12 @@ int ft_board_setup(void *blob, bd_t *bd)
size[i] = gd->bd->bi_dram[i].size;
}
#ifdef CONFIG_GIC_V3_ITS
gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
#endif
#ifdef CONFIG_RESV_RAM
/* reduce size if reserved memory is within this bank */
if (gd->arch.resv_ram >= base[0] &&

21
board/nvidia/e2220-1170/e2220-1170.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013-2015
* (C) Copyright 2013-2019
* NVIDIA Corporation <www.nvidia.com>
*/
@ -9,7 +9,6 @@
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include "../p2571/max77620_init.h"
#include "pinmux-config-e2220-1170.h"
void pin_mux_mmc(void)
{
@ -30,21 +29,3 @@ void pin_mux_mmc(void)
if (ret)
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
}
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
*/
void pinmux_init(void)
{
pinmux_clear_tristate_input_clamping();
gpio_config_table(e2220_1170_gpio_inits,
ARRAY_SIZE(e2220_1170_gpio_inits));
pinmux_config_pingrp_table(e2220_1170_pingrps,
ARRAY_SIZE(e2220_1170_pingrps));
pinmux_config_drvgrp_table(e2220_1170_drvgrps,
ARRAY_SIZE(e2220_1170_drvgrps));
}

276
board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
View file

@ -1,276 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*/
/*
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
*
* To generate this file, use the tegra-pinmux-scripts tool available from
* https://github.com/NVIDIA/tegra-pinmux-scripts
* Run "board-to-uboot.py e2220-1170".
*/
#ifndef _PINMUX_CONFIG_E2220_1170_H_
#define _PINMUX_CONFIG_E2220_1170_H_
#define GPIO_INIT(_port, _gpio, _init) \
{ \
.gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
/* port, pin, init_val */
GPIO_INIT(A, 5, IN),
GPIO_INIT(A, 6, IN),
GPIO_INIT(B, 4, IN),
GPIO_INIT(E, 6, IN),
GPIO_INIT(G, 2, OUT0),
GPIO_INIT(G, 3, OUT0),
GPIO_INIT(H, 0, OUT0),
GPIO_INIT(H, 1, OUT0),
GPIO_INIT(H, 2, IN),
GPIO_INIT(H, 3, OUT0),
GPIO_INIT(H, 4, OUT0),
GPIO_INIT(H, 5, IN),
GPIO_INIT(H, 6, OUT0),
GPIO_INIT(H, 7, OUT0),
GPIO_INIT(I, 0, OUT0),
GPIO_INIT(I, 1, IN),
GPIO_INIT(I, 2, OUT0),
GPIO_INIT(I, 3, OUT0),
GPIO_INIT(K, 0, IN),
GPIO_INIT(K, 1, OUT0),
GPIO_INIT(K, 2, OUT0),
GPIO_INIT(K, 3, OUT0),
GPIO_INIT(K, 4, IN),
GPIO_INIT(K, 5, OUT0),
GPIO_INIT(K, 6, IN),
GPIO_INIT(K, 7, OUT0),
GPIO_INIT(L, 0, OUT0),
GPIO_INIT(S, 4, OUT0),
GPIO_INIT(S, 5, OUT0),
GPIO_INIT(S, 6, OUT0),
GPIO_INIT(S, 7, OUT0),
GPIO_INIT(T, 0, OUT0),
GPIO_INIT(T, 1, OUT0),
GPIO_INIT(V, 1, OUT0),
GPIO_INIT(V, 2, OUT0),
GPIO_INIT(V, 3, IN),
GPIO_INIT(V, 5, OUT0),
GPIO_INIT(V, 6, OUT0),
GPIO_INIT(X, 0, IN),
GPIO_INIT(X, 1, IN),
GPIO_INIT(X, 2, IN),
GPIO_INIT(X, 3, IN),
GPIO_INIT(X, 4, IN),
GPIO_INIT(X, 5, IN),
GPIO_INIT(X, 6, IN),
GPIO_INIT(X, 7, IN),
GPIO_INIT(Y, 0, IN),
GPIO_INIT(Y, 1, IN),
GPIO_INIT(Z, 0, IN),
GPIO_INIT(Z, 4, OUT0),
GPIO_INIT(BB, 2, OUT0),
GPIO_INIT(BB, 3, OUT0),
GPIO_INIT(BB, 4, IN),
GPIO_INIT(CC, 1, IN),
GPIO_INIT(CC, 5, OUT0),
GPIO_INIT(CC, 6, IN),
GPIO_INIT(CC, 7, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.od = PMUX_PIN_OD_##_od, \
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
.lock = PMUX_PIN_LOCK_DEFAULT, \
}
static const struct pmux_pingrp_config e2220_1170_pingrps[] = {
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
};
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
.lpmd = PMUX_LPMD_##_lpmd, \
.schmt = PMUX_SCHMT_##_schmt, \
.hsm = PMUX_HSM_##_hsm, \
}
static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = {
};
#endif /* PINMUX_CONFIG_E2220_1170_H */

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