Commit graph

4353 commits

Author SHA1 Message Date
Stefano Babic
707acd01de Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-26 12:11:54 +01:00
Dan Murphy
8cffe5bd0d spl: common: Support for USB MSD FAT image loading
Add SPL support to be able to detect a USB Mass Storage device
connected to a USB host.  Once a USB Mass storage device is detected
the SPL will load the u-boot.img from a FAT partition to target address.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2014-01-24 16:59:22 -05:00
Masahiro Yamada
b2a6dfe4f8 powerpc: mpc5xxx: remove redundant CONFIG_MPC5xxx definition
We do not have to define CONFIG_MPC5xxx in board config headers
(and start.S) because it is defined in arch/powerpc/cpu/mpc5xxx/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:21 -05:00
Masahiro Yamada
347d06dec4 sandbox: fix the return type of os_free() function
The function os_free() returns nothing.
Its return type should be "void" rather than "void *".

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
bf1af3d872 ARM: merge commonly-defined PLATFORM_RELFLAGS
Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8
had the same option:
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

This commit moves it into arch/arm/config.mk.

If the compiler does not support the option,
it is ignored by $(call cc-option,...).
So this commit gives no harm to ARMv8.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
84acd1e179 powerpc: mpc86xx: move CONFIG_MPC86xx definition to CPU config.mk
Define CONFIG_MPC86xx in arch/powerpc/cpu/mpc86xx/config.mk
because all target boards with mpc86xx cpu define it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
d40ddae4b3 powerpc: mpc85xx: move CONFIG_MPC85xx definition to CPU config.mk
Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk
because all target boards with mpc85xx cpu define it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
4b0065c644 powerpc: mpc5xx: remove redundant CONFIG_5xx definition
We do not have to define CONFIG_5xx in a source file
because it is defined in arch/powerpc/cpu/mpc5xx/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
07344edde2 powerpc: mpc8xx: remove redundant CONFIG_8xx definition
We do not have to define CONFIG_8xx in source files
because it is defined in arch/powerpc/cpu/mpc8xx/config.mk

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:08 -05:00
Masahiro Yamada
df05ff7789 x86: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-01-24 16:59:07 -05:00
Masahiro Yamada
36aa822880 powerpc: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:07 -05:00
Masahiro Yamada
2bf9557744 blackfin: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:07 -05:00
Masahiro Yamada
4d54b43a59 avr32: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:07 -05:00
Masahiro Yamada
5378d5eabe avr32: move CONFIG_AVR32 definition to arch/avr32/config.mk
Like other architectures, CONFIG_AVR32 can be defined
in arch/avr32/config.mk rather than board header files.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-01-24 16:59:07 -05:00
Masahiro Yamada
d937326ffc Remove obsolete _LINUX_CONFIG_H macro
Commit 643aae1406
deleted include/linux/config.h but missed to
delete _LINUX_CONFIG_H macro.
It is no longer used at all.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-01-24 16:59:07 -05:00
Darwin Rambo
de351d6be6 lib: time: add weak timer_init() function
If timer_init() is made a weak stub function, then it allows us to
remove several empty timer_init functions for those boards that
already have a timer initialized when u-boot starts. Architectures
that use the timer framework may also remove the need for timer.c.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
2014-01-24 16:59:06 -05:00
Nishanth Menon
194dd74ad9 DRA7: add ABB setup for MPU voltage domain
Patch adds modification to shared omap5 abb_setup() function, and
proper registers definitions needed for ABB setup sequence. ABB is
initialized for MPU voltage domain at OPP_NOM.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-01-24 11:41:17 -05:00
Nishanth Menon
3ac8c0bf65 DRA7: Add support for ES1.1 silicon ID code
ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support
for ES1.1 IDCODE change.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-01-24 11:41:17 -05:00
Satyanarayana, Sandhya
e9b13ce0b6 ARM: AM335x: Enable DDR dynamic IO power down
This patch enables dynamically powering down the
IO receiver when not performing a read on boards using DDR3.
This optimizes both active and standby power consumption.
This bit is not set on EVM SK and EVM 1.5 and later boards.
Setting the same.

This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
2014-01-24 11:38:39 -05:00
Enric Balletbò i Serra
ac02aa9763 ARM: OMAP3: Rename OMAP3_PUBLIC_SRAM_* to NON_SECURE_SRAM_*
Other TI processors like am33xx, omap4 and omap5 have called these variables
as NON_SECURE_SRAM_*, shouldn't be a big problem rename these variables to
be coherent.

One reason more to rename these variables is to have the possibility of any
OMAP3 board to use the ti_armv7_common.h include as the NON_SECURE_SRAM_END
is used to define the CONFIG_SYS_INIT_SP_ADDR variable.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
2014-01-24 11:38:39 -05:00
Jassi Brar
e81f63f0d2 ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL
The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-01-24 09:38:39 -05:00
Jassi Brar
02c41535b6 ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL
The commit
 f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-01-24 09:34:22 -05:00
Haijun.Zhang
f28bea0003 eSDHC: Calculate envaddr accroding to the address format
On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.

If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.

Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-22 08:56:44 -08:00
Po Liu
6609916efb powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.

	- For ifc, elbc, esdhc, espi, all need the SPL without
	section .resetvec.
	- Use a clear function name for nand spl boot.
	- Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c
	in spl/Makefile;

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:42:01 -08:00
York Sun
b518816423 powerpc/mpc85xx: Fix a typo in workaround message for DDR erratum A003474
Unfortunately a typo presents "DDR-A003473" instead of "DDR-A003474".

Signed-off-by: York Sun <yorksun@freescale.com>
2014-01-21 13:40:18 -08:00
Shengzhou Liu
842eaa1361 powerpc/85xx: update erratum a006379
Enable Erratum A006379 for T2080, T2081, T4160, B4420.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:39:19 -08:00
Ramneek Mehresh
3f283f4bdc powerpc/83xx: Add support for get_svr() for 83xx devices
Defines get_svr() for 83xx devices

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:35:43 -08:00
Stephen Warren
004c10598b ARM: bcm2835: fix mailbox timeout
My original intention was to have a 100ms timeout. However, the timer
operations used return values in ms not us, so we ended up with a 100s
timeout instead. Fixing this exposes that some operations need longer
to operate than 100ms, so bump the timeout up to a whole second.

Reported-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Andre Heider <a.heider@gmail.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-01-20 17:11:39 -05:00
Stephen Warren
f66f2aa265 ARM: rpi_b: power on SDHCI and USB HW modules
Send RPC commands to the VideoCore to turn on the SDHCI and USB modules.
For SDHCI this isn't needed in practice, since the firmware already
turned on the power in order to load U-Boot. However, it's best to be
explicit. For USB, this is necessary, since the module isn't powered
otherwise. This will allow the kernel USB driver to work.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-01-20 17:11:39 -05:00
Tom Rini
4641c211f6 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-01-20 07:33:42 -05:00
Fabio Estevam
be2a3bb39a mx6: Revert "mx6: soc: Disable VDDPU regulator"
Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang
for people using FSL kernel 3.0.35 and 3.10, so revert it for now.

Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Reported-by: Pierre Aubert <p.aubert@staubli.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-17 10:16:48 +01:00
Tom Rini
4913fc23f0 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-16 13:50:16 -05:00
Nobuhiro Iwamatsu
82852762ce arm: rmobile: Add SH QSPI base register address
This adds base register address of SH QSPI.
Currently, SH QSPI is used only from R8A7790 and R8A7791.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-01-16 08:07:20 +09:00
Albert ARIBAUD
bf46e7d8d1 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-01-15 15:18:04 +01:00
Fabio Estevam
3a21773129 mx6: Add initial support for the Hummingboard solo
SolidRun has designed the Hummingboard board based on mx6q/dl/solo.

Add the initial support for the mx6 solo variant.

More information about this hardware can be found at:
http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware

(Carrier-One was the previous name of Hummingboard).

Based on the work from Jon Nettleton <jon.nettleton@gmail.com>.

Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-15 10:33:25 +01:00
Fabio Estevam
5f98d0b5d3 mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency
that will be generated.

No changes are made to mx6slevk, which uses the default 50MHz fec clock.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-15 10:33:25 +01:00
Tom Rini
b5c068f3f8 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-14 14:48:42 -05:00
Andreas Bießmann
6ba2bc8fa9 arm: use canonical sub mnemonic
Building some arm boards with older binutils may produce errors like this:

---8<---
crt0.S: Assembler messages:
crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)'
--->8---

Use canonical version of the subtract mnemonic to avoid those issues.

Reported-by: Alexey Smishlayev <alexey@xtech2.lv>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-01-14 12:38:47 +01:00
Albert ARIBAUD
e6fe4bd989 Merge 'u-boot-imx/master' into 'u-boot-arm/master' 2014-01-14 11:50:54 +01:00
Albert ARIBAUD
b02bfc4dfc arm: put .hash, .got.plt and .machine_param back in binaries
Some targets will build fine but not boot if sections .hash and
.got.plt are not present in the binary. Add them back.

Also, Exynos machines require .machine_param section in SPL.
Add it.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
2014-01-14 11:43:10 +01:00
Tom Rini
0effc5e567 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-13 13:50:25 -05:00
Marek Vasut
67decc71ed ARM: pxa: Fix OneNAND SPL builds
The OneNAND SPL used on PXA is slightly obscure. Due to the OneNAND limitation,
where we have only the first 1KiB of the OneNAND available upon power-up as a
memory-mapped area, from which the CPU starts executing, we place only the most
essential code into this first 1KiB . This code copies the rest of the SPL into
SRAM and jumps to it. This code is stored in section .text.0 .

The rest of the SPL is stored in section .text.1 . When running the OBJCOPY on
the SPL, it will preserve only .text section, but the .text.0 and .text.1 are
stripped away from the result, thus making the SPL binary empty. The patch adds
additional -j parameters to the OBJCOPY for PXA during the SPL build, which will
preserve the .text.0 and .text.1 sections.

Moreover, this patch also adds missing functions into the .text.0 section, since
otherwise the PXA270 with 1KiB-window OneNAND won't be able to boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
2014-01-13 12:39:10 +01:00
Inderpal Singh
16f9480dfc usb: ehci: exynos: set/reset hsic phys
The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2
are for HSIC phys. The usb 2.0 phy is already being setup. This patch
sets up the hsic phys.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
2014-01-13 12:23:28 +01:00
Christian Gmeiner
5a66016987 imx6: make use of lldiv(..)
Commit 762a88ccf8 introduces
a 64-bit division without using the lldiv() function,
which pulls in previously unused libgcc stuff.

Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-13 11:52:28 +01:00
Tom Rini
7f673c99c2 Merge branch 'master' of git://git.denx.de/u-boot-arm
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
2014-01-10 10:56:00 -05:00
Jagannadha Sutradharudu Teki
84515165da gpio: zynq: Add dummy gpio routines
GPIO dummy routines are required for fdt build, may be removed
these dependencies once the u-boot fdt is fully optimized.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-10 15:18:33 +01:00
Jagannadha Sutradharudu Teki
f8f36c5dda dts: zynq: Add basic fdt support
This patch provides a basic fdt support for zynq u-boot.

zynq-7000.dtsi-> initial arch dts file
zynq-zed.dts -> initial zed board dts file
more devices should be added in subsequent patches.

u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zed

Enabled CONFIG_OF_SEPARATE for building dtb separately.
There is a new binary called u-boot-dtb.bin which is a u-boot
with devicetree supported.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-10 15:18:33 +01:00
Jagannadha Sutradharudu Teki
b3de92495f zynq: Add support to find bootmode
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.

Added this functionality on board_late_init as it's not
needed for normal initializtion part.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-10 15:18:33 +01:00
Tom Rini
795611e6ff armv8: Use __aarch64__ rather than CONFIG_ARM64 in some cases
The toolchain sets __aarch64__ for both LE and BE.  In the case of
posix_types.h we cannot reliably use config.h as that will lead to
problems.  In the case of byteorder.h it's clearer to check the EB flag
being set in either case instead.

Cc: David Feng <fenghua@phytium.com.cn>
Signed-off-by: Tom Rini <trini@ti.com>

Amended by Albert ARIBAUD <albert.u.boot@aribaud.net> to
actually remove the config.h include from the posix_types.h
files, with permission from Tom Rini.
2014-01-10 10:10:23 +01:00
Tom Rini
8401bfa91e Merge branch 'master' of git://git.denx.de/u-boot-mmc 2014-01-09 11:05:32 -05:00
Tom Rini
33d413fc91 Merge branch 'master' of git://git.denx.de/u-boot-sh 2014-01-09 11:04:53 -05:00
David Feng
0ae7653128 arm64: core support
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: David Feng <fenghua@phytium.com.cn>
2014-01-09 16:08:44 +01:00
Chin Liang See
c5c1af2176 socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA
To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-01-09 11:53:55 +02:00
Nobuhiro Iwamatsu
5fe3aefd3d sh: sh2: Remove CONFIG_SH2A definition from asm/processor.h
SH2 and SH2A use a common header. Both checks are not necessary.
This removes CONFIG_SH2A definition from asm/processor.h.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-01-09 13:22:22 +09:00
Nobuhiro Iwamatsu
6b87abe3ac sh: sh4: Remove CONFIG_SH4A definition from source code
SH4 and SH4A are compatible. But some instructions are different from these.
In Linux kernel, It is treated as a separate CPU, but for now, I think that
there is no need to divide especially in the U-Boot.

This removes CONFIG_SH4A definition from source code, SH4A is treated as SH4.
And this fix white space.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-01-09 12:47:15 +09:00
Simon Glass
b88eb329ce sandbox: Add a prototype for cleanup_before_linux()
This function is defined but has no prototype declaration. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-01-08 17:26:01 -07:00
Simon Glass
1209e2727c sandbox: Add facility to save/restore sandbox state
It is often useful to be able to save out the state from a sandbox test
run, for analysis or to restore it later to continue a test. Add generic
infrastructure for doing this using a device tree binary file. This is
a flexible tagged file format which is already supported by U-Boot, and
it supports hierarchy if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
2014-01-08 17:25:08 -07:00
Simon Glass
5c2859cdc3 sandbox: Allow reading/writing of RAM buffer
It is useful to be able to save and restore the RAM contents of sandbox
U-Boot either for setting up tests, for later analysys, or for chaining
together multiple tests which need to keep the same memory contents.

Add a function to provide a memory file for U-Boot. This is read on
start-up and written when shutting down. If the file does not exist
on start-up, it will be created when shutting down.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-01-08 17:25:03 -07:00
Simon Glass
c5a62d4a7b sandbox: Add -i option to enter interactive mode
Normally when U-Boot starts with a command (-c option) it quits when the
command completes. Normally this is what is requires, since the test is
likely complete.

Provide an option to jump into the console instead, so that debugging or
other tasks may be performed before quitting.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-01-08 17:24:53 -07:00
Simon Glass
91b136c798 sandbox: Allow the console to work earlier
With sandbox, errors and problems may be reported before console_init_f()
is executed. For example, an argument may not parse correctly or U-Boot may
panic(). At present this output is swallowed so there is no indication what
is going wrong.

Adjust the console to deal with a very early sandbox setup, by detecting that
there is no global_data yet, and calling os functions in that case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-01-08 17:24:50 -07:00
Simon Glass
88bd0e9d15 sandbox: Implement the bootm command for sandbox
When sandbox does a 'bootm' to run a kernel we cannot actually execute it.
So just exit sandbox, which is essentially what U-Boot does on other archs.
Also, allow sandbox to use bootm on any kernel, so that it can be used
to test booting of kernels from any architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-01-08 17:24:42 -07:00
Simon Glass
808434cdbd sandbox: Allow return from board_init_f()
The execution flow becomes easier if we can return from board_init_f()
as ARM does. We can control things from start.c instead of having to
call back into that file from other places.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-01-08 17:24:38 -07:00
Simon Glass
6ebcab8de7 sandbox: Correct help message <arg> garbling
The <arg> is displayed for options with no argument, and omitted for those
with an argument. Swap this around.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-01-08 17:24:23 -07:00
Simon Glass
77595c6d9e sandbox: Improve/augment memory allocation functions
Implement realloc() and free() for sandbox, by adding a header to each
block which contains the block size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
2014-01-08 17:24:19 -07:00
Nobuhiro Iwamatsu
8f0960e837 sh: sh2: Change CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQ
CONFIG_SYS_HZ of SH2 is not used as frequency of base timer. This is the
correct clock of CMT.
This changes from CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQ, in order to use
CONFIG_SYS_HZ as clock of CMT.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-01-08 14:59:53 +09:00
Nobuhiro Iwamatsu
b1165adfd5 sh: sh4: Add CONFIG_SH4 definition to config.mk of SH4
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-01-08 14:47:40 +09:00
Nobuhiro Iwamatsu
22e7d66181 sh: sh3: Add CONFIG_SH3 definition to config.mk of SH3
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-01-08 14:47:36 +09:00
Nobuhiro Iwamatsu
14eeb926bb sh: sh2: Add CONFIG_SH2 definition to config.mk of SH2
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-01-08 14:13:55 +09:00
Albert ARIBAUD
4b0561d841 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-01-06 09:32:42 +01:00
Albert ARIBAUD
a891601ce5 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
2014-01-06 08:49:58 +01:00
Sergey Alyoshin
4611d5bab2 arm: mx5: Add fuse supply enable in fsl_iim
Enable fuse supply before fuse programming and disable after.

Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2014-01-03 15:44:06 +01:00
Otavio Salvador
c655b816e5 ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6
The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-03 15:44:05 +01:00
Otavio Salvador
7773fd1969 imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro
The macro allows easy setting in per-pin, as for example:

,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----

The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.

The following quote from the datasheet:

,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----

This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.

Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio
Estevam <fabio.estevam@freescale.com> and Eric Bénard
<eric@eukrea.com> for helping to properly trace this down.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-03 15:44:05 +01:00
Shengzhou Liu
2ffa96d815 powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS
CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-01-02 14:10:13 -08:00
Priyanka Jain
b135991a3c powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.

So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock

DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
 normal clocking mode by DDR_Reference clock

-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
 single source clocking mode by DIFF_SYSCLK

Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2014-01-02 14:10:13 -08:00
Fabio Estevam
0222982780 mx6: soc: Disable VDDPU regulator
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
39f0ac9347 mx6: soc: Add the required LDO ramp up delay
When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
3d622b78bd mx6: soc: Introduce set_ldo_voltage()
Introduce set_ldo_voltage() so that all three LDO regulators can be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:51 +01:00
Fabio Estevam
7e5e8c94a9 mx6: soc: Set the VDDSOC at 1.175 V
mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.

This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Fabio Estevam
e113fd1972 mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages
Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Fabio Estevam
fc740648bd mx6: soc: Staticize set_vddsoc()
set_vddsoc() is not used anywhere else, so make it static.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02 17:16:50 +01:00
Rajeshwari Birje
e2be3369c8 DTS: Add dts support for SMDK5420
This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:35 +09:00
Rajeshwari Birje
5af4a4f74a Exynos5420: Add support for 5420 in pinmux and gpio
Adds code in pinmux and gpio framework to support Exynos5420.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
f3d7c2fe9d Exynos5420: Add DDR3 initialization for 5420
This patch intends to add DDR3 initialization code for Exynos5420.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
060c227a28 Exynos5420: Add clock initialization for 5420
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
e89278c933 EXYNOS5420: Add dmc and phy_control register structure
Add dmc and phy_control register structure for 5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
3e97635764 EXYNOS5420: Add power register structure.
Add structure for power register for Exynos5420

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
e69847ab8d Exynos5420: Add base addresses for 5420
Adds base addresses of various IPs and controllers required for
Exynos5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Rajeshwari Birje
71ebb33559 EXYNOS5: Create a common board file
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.

exynos_init function is provided for platform specific code.

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30 16:50:34 +09:00
Stefano Babic
f5514e47c4 MX6: fix sata compilation for i.MX6
Commit 164d984661 breaks
board with SATA support, because sata is not compiled.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-12-19 11:04:33 +01:00
Lokesh Vutla
b5e01eecc8 ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:45 -05:00
Lokesh Vutla
d3daba10f1 ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:44 -05:00
Lokesh Vutla
965de8b91b ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-18 21:14:18 -05:00
Lokesh Vutla
cf04d0326b ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50	300MHz
OPP100	600MHz
OPP120	720MHz
OPPTB	800MHz
OPPNT	1000MHz
According to the latest DM following is the OPP table dependencies:
	VDD_CORE 	VDD_MPU
	OPP50		OPP50
	OPP50 		OPP100
	OPP100		OPP50
	OPP100		OPP100
	OPP100		OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
4892495e36 ARM: AM43xx: mux: Update mux data
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
1fb68b842e ARM: AM43xx: Update Current Booting devices list
Current Booting devices list is different from that of AM33xx.
Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Lokesh Vutla
0d54cb924e ARM: AM43xx: Select clk source for Timer2
Selecting the Master osc clk as Timer2 clock source.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:01 -05:00
Sekhar Nori
9f1a8cd33f ARM: AM43XX: board: add support for reading onboard EEPROM
Add support for reading onboard EEPROM to enable
board detection.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
369cbe1e1e ARM: AM43xx: Adapt to ti_armv7_common.h config file
Use ti_armv7_common.h config file to inclde the common
configs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:14:00 -05:00
Lokesh Vutla
7ca1b2a210 ARM: AM43xx: Update the base addresses of modules
PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18 21:13:59 -05:00
Albert ARIBAUD
d627eefcd5 Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master' 2013-12-18 22:19:02 +01:00
Alban Bedel
766afc3dff arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swrren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:49 -07:00
Alban Bedel
3346cbb8e8 ARM: tegra: support SKU b1 of Tegra30
Add the Tegra30 SKU b1 and treat it like other Tegra30 chips.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Thierry Reding
4475c7752d Tegra114: Do not program CPCON field for PLLX
PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Jimmy Zhang
44de8e22ec Tegra114: Fix PLLX M, N, P init settings
The M, N and P width have been changed from Tegra30. The maximum value
for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
be set accordingly.

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-12-18 10:19:48 -07:00
Sergei Ianovich
23f00caf6e ARM: pxa: prevent PXA270 occasional reboot freezes
Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains that watchdog reset time is just
8us insead of 10ms in EMTS.

If SDRAM is not reset, it causes memory bus congestion and
the device hangs.

We put SDRAM in selfresh mode before watchdog reset, removing
potential freezes.

Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
CC: Marek Vasut <marex@denx.de>
2013-12-18 16:00:37 +01:00
Yoshihiro Shimoda
320cf35080 sh: add support for sh7753evb board
The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.

This patch support the following functions:
 - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-12-18 16:49:08 +09:00
Frank Li
ebaf6b26bc imx6: fix random hang when download by usb
ROM did not invalidate L1 cache when download by usb
Need invalidate L1 cache before enable cache

Signed-off-by: Huang yongcai <b20788@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
2013-12-17 18:48:45 +01:00
Fabio Estevam
89cfd0f575 mx6: clock: Fix the calculation of PLL_ENET frequency
According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-12-17 18:38:42 +01:00
Giuseppe Pagano
164d984661 nitrogen6x: Move setup_sata to common part
Move setup_sata function definition from platform file nitrogen6x.c
to arch/arm/imx-common/sata.c to avoid code duplication.

Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Eric Nelson <eric.nelson@boundarydevices.com>
2013-12-17 18:12:14 +01:00
Eric Nelson
b47abc36aa i.MX6 (DQ/DLS): use macros for mux and pad declarations
This allows the use of either or both declarations from
the files mx6q_pins.h and mx6dl_pins.h.

All board files should include <asm/arch/mx6-pins.h>
with one of the following defined in boards.cfg
    MX6Q   - for boards targeting i.MX6Q or i.MX6D
    MX6DL  - for boards targeting i.MX6DL
    MX6S   - for boards targeting i.MX6S
    MX6QDL - for boards that support any of the above with
             run-time detection

Pad declarations will be MX6_PAD_x for single-variant boards
and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both
processor classes.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-12-17 17:12:34 +01:00
Tom Rini
93b7b7fdad Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2013-12-16 09:13:25 -05:00
Masahiro Yamada
e8a8b8246a Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)
Convert like follows:

 CPU mpc83xx  -> CONFIG_MPC83xx
 CPU mpc85xx  -> CONFIG_MPC85xx
 CPU mpc86xx  -> CONFIG_MPC86xx
 CPU mpc5xxx  -> CONFIG_MPC5xxx
 CPU mpc8xx   -> CONFIG_8xx
 CPU mpc8260  -> CONFIG_8260
 CPU ppc4xx   -> CONFIG_4xx
 CPU x86      -> CONFIG_X86
 ARCH x86     -> CONFIG_X86
 ARCH powerpc -> CONFIG_PPC

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-16 08:59:42 -05:00
Miao Yan
871a57bb81 common/cmd_bootm: extend do_bootm_vxworks to support the new VxWorks boot interface.
The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware
description mechanism. For PowerPC, the boot interface conforms to
the ePAPR standard, which is:

   void (*kernel_entry)(ulong fdt_addr,
          ulong r4 /* 0 */,
          ulong r5 /* 0 */,
          ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */,
          ulong r8 /* 0 */, ulong r9 /* 0 */)

For ARM, the boot interface is:

   void (*kernel_entry)(void *fdt_addr)

Signed-off-by: Miao Yan <miao.yan@windriver.com>
[trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC,
missing extern ft_fixup_num_cores]
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-16 08:59:05 -05:00
Sonic Zhang
ecf9ce2149 blackfin: remove build warning
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-16 11:38:33 +08:00
Sonic Zhang
31d5d4e056 blackfin: fixing warning by including proper headers
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-16 11:38:33 +08:00
Masahiro Yamada
de04d64eda PowerPC: merge commonly-defined flags
PLATFORM_RELFLAGS += -meabi
PLATFORM_CPPFLAGS += -ffixed-r2
were defined in all arch/powerpc/${CPU}/config.mk.

This commit moves them to arch/powerpc/config.mk.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-13 09:17:32 -05:00
Tom Rini
49a90e2975 ARM:PXA: Correct tick_to_time / us_to_tick to use lldiv
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-12-13 09:16:20 -05:00
Tom Rini
e83bab8403 ARM:zynq: Correct __udelay to use lldiv
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Tom Rini <trini@ti.com>
2013-12-13 09:16:20 -05:00
Masahiro Yamada
a8c075414a Makefile: use two double-quotations as a pair
Some editors such as Emacs can highlight source files.
But their parser algorithm is not perfect.

If you use one double-quotation alone, some editor cannot
handle it nicely and mark source lines as a string by mistake.

It is preferable to use two double-quotations as a pair.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-13 09:15:33 -05:00
Lokesh Vutla
d2c7074b95 ARM: OMAP5: clocks: Update MPU settings for OPP_NOM
As per the latest 0.6 version of DM for OMAP5430 ES2.0,
MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU
should be locked at 2000MHz. Fixing the same and cleaning the
previously used dpll values.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-12 17:43:39 -05:00
Lokesh Vutla
5298f21ab3 ARM: DRA7xx: Change clk divider setting
Commit "armv7: hw_data: change clock divider setting"
updates the setting for m6 divider for 20MHz sys_clk frequency.
But missed to update for other sys_clk frequencies. Doing the same.

Reported-by: Rajendran, Vinothkumar <vinothr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-12 17:43:39 -05:00
Nikita Kiryanov
47b4bcf785 arm: omap: abb: add missing include
ABB code uses LDELAY but does not include the header that provides its
definition.

Include the header.

Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Nishanth Menon <nm@ti.com>
2013-12-12 14:54:22 -05:00
Dan Murphy
052fb19603 arm: am437: Fix offset for USB registers
Fix the offset for the USB clock registers

Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-12-12 14:54:22 -05:00
Lokesh Vutla
dcc2357638 ARM: OMAP4: Move TEXT_BASE down to non-HS limit
With the current scenario SPL size is being overlapped with the public
stack and not allowing any OMAP4 device to boot. So the suggestion came
up was to move the TEXT_BASE down to non-HS limit. Fixing the same and
also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image
downloadable area.
Discussion on this can be seen here:
https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html

Tested on OMAP4460 PANDA.

Reported-by: Chao Xu <caesarxuchao@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-12 14:54:20 -05:00
Tom Rini
12115c6ad3 am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF
Test on Beaglebone white over cpsw, usb ether and SD card (read and
write), performance increased, crc32 of data matches.

Signed-off-by: Tom Rini <trini@ti.com>
2013-12-12 14:54:12 -05:00
Albert ARIBAUD
bd851c7a26 Revert "ARM: move interrupt_init to before relocation"
Revert commit 0f5141e9 which causes boards starting in
FLASH to try and write to a FLASH location.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-12-11 21:28:06 +01:00
Prabhakar Kushwaha
e03c76c303 powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040
The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16.

So, update its value as default.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:54 -08:00
Shaohui Xie
c1015c67f4 powerpc/t4240: Add a frequency setting case for fman1
A new valid setting case added for fman1, it uses platform frequency.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:04 -08:00
Tom Rini
4b210ad342 Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	board/samsung/trats2/trats2.c
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-12-10 17:15:18 -05:00
Albert ARIBAUD
f15ea6e1d6 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/armv7/rmobile/Makefile
	doc/README.scrapyard

Needed manual fix:
	arch/arm/cpu/armv7/omap-common/Makefile
	board/compulab/cm_t335/u-boot.lds
2013-12-10 22:23:59 +01:00
Tom Rini
65b7fe28a1 Merge branch 'spi' of git://git.denx.de/u-boot-x86 2013-12-10 09:36:23 -05:00
Mike Frysinger
6122813fa2 sandbox: spi: Add SPI emulation bus
This adds a SPI framework for people to hook up simulated SPI clients.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-12-09 12:22:18 -07:00
Simon Glass
7b3efc6699 sandbox: Rename sb_cmdline_option to sandbox_cmdline_option
The new name is longer but more clearly related to sandbox.

This is in a separate patch within the same series since some comments on the
SPI series rely on it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
2013-12-09 12:22:02 -07:00
Andreas Bießmann
bcf9fe37f5 at91: switch coloured LED to gpio API
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-09 13:21:47 +01:00
Andreas Bießmann
934e3b5240 at91: redefine legacy GPIO PIN_BASE
In order to get the very same value for legacy pin definitions and new gpio
definitions set the legacy PIN_BASE to 0.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-12-09 13:21:39 +01:00
Andreas Bießmann
9ecc922e75 at91: add new gpio pin definitions
This patch define new names for GPIO pins on at91 devices. Follow up patches
will convert the whole infrastructure to use these new definitions.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Bo Shen <voice.shen@atmel.com>
2013-12-09 13:21:26 +01:00
Albert ARIBAUD
47ed5dd031 arm: keep all sections in ELF file
Current LDS files /DISCARD/ a lot of sections when linking ELF
files, causing diagnostic tools such as readelf or objdump to
produce partial output. Keep all section at link stage, filter
only at objcopy time so that .bin remains minimal.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-12-07 06:53:58 +01:00
Masahiro Yamada
3064d599af ARM: align MVBAR on 32 byte boundary
The lower 5 bit of MVBAR is UNK/SBZP.
So, Monitor Vector Base Address must be 32-byte aligned.
On the other hand, the secure monitor handler does not need
32-byte alignment.

This commit moves ".algin 5" directive to the correct place.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andre Przywara <andre.przywara@linaro.org>
Acked-by: Andre Przywara <andre.przywara@linaro.org>
2013-12-06 21:03:35 +01:00
Albert ARIBAUD
375a4496ff Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-12-06 16:54:42 +01:00
Albert ARIBAUD
c35cf8dc9f Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2013-12-06 14:26:51 +01:00
Tom Rini
3f56795635 Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2013-12-06 07:19:09 -05:00
Michael Trimarchi
f33b9bd398 arm: omap3: Enable clocks for peripherals only if they are used
This patch change the per_clocks_enable() function used in OMAP3
code to enable peripherals clocks. Only required clock should be
activated. So if the board use the uart(x) as a console we need
to activate it. The Board's config should include define to enable
every subsystem that the board use. For a complete list
of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER
should be checked.
Right now the bootloader can enable and disable clocks for:
uart(x) using CONFIG_SYS_NS16550
gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 }
i2c bus using CONFIG_DRIVER_OMAP34XX_I2C.

Not required gptimer(x) and mcbsp(x) for booting are disabled by default and
are not supported by any define.
Their activation need to included in the per_clocks_enable if the
peripheral is included. Not booting board should enable the peripheral
clock connected to their driver

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2013-12-06 07:02:32 -05:00
Minkyu Kang
d8fa31a71f arm: exynos: adds ifdef for spi boot
This patch fix following errors and warnings

spl_boot.c: In function 'exynos_spi_copy':
spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function)
spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in
spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function)
spl_boot.c: In function 'copy_uboot_to_ram':
spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable]
spl_boot.c: At top level:
spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function]

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-12-06 19:07:47 +09:00
Albert ARIBAUD
7988bd4ed6 Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' 2013-12-06 10:41:49 +01:00
Masahiro Yamada
985e18d14e blackfin: Do not generate unused header bootrom-asm-offsets.h
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-06 16:06:51 +08:00
Sonic Zhang
76db0fde5b blackfin: If none ADI_GPIOX macro is defined, use ADI_GPIO1 as default
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2013-12-06 16:06:51 +08:00
Jaehoon Chung
01322004ec arm: exynos: remove the unused define.
These defines didn't use anywhere.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-05 10:42:04 +09:00
Jaehoon Chung
4bee78f502 arm: exynos/goni: fix the return type for s5p_mmc_init
The "int" type is right.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-05 10:42:04 +09:00
York Sun
1df99080cb powerpc/mpc8349: Use generic mpc85xx DDR driver
MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/ddr/fsl/, the link is replaced by referring driver
directly. We now can simply enable the macro and use the driver.
Other mpc83xx SoCs still use their own driver.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-12-04 14:55:05 -08:00