mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
mx6: Add initial support for the Hummingboard solo
SolidRun has designed the Hummingboard board based on mx6q/dl/solo. Add the initial support for the mx6 solo variant. More information about this hardware can be found at: http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware (Carrier-One was the previous name of Hummingboard). Based on the work from Jon Nettleton <jon.nettleton@gmail.com>. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
5f98d0b5d3
commit
3a21773129
10 changed files with 675 additions and 0 deletions
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@ -245,6 +245,10 @@ struct src {
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u32 gpr10;
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};
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/* GPR1 bitfields */
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#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
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#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
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/* GPR3 bitfields */
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#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
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#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
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9
board/solidrun/hummingboard/Makefile
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9
board/solidrun/hummingboard/Makefile
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@ -0,0 +1,9 @@
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#
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# (C) Copyright 2013 Freescale Semiconductor, Inc.
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# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
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# Copyright (C) 2013, Jon Nettleton <jon.nettleton@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := hummingboard.o
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40
board/solidrun/hummingboard/README
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40
board/solidrun/hummingboard/README
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@ -0,0 +1,40 @@
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U-Boot for SolidRun Hummingboard
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--------------------------------
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This file contains information for the port of U-Boot to the Hummingboard.
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For more details about Hummingboard, please refer to:
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http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
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(Carrier-One was the previous name of Hummingboard).
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Building U-boot for Hummingboard
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--------------------------------
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To build U-Boot for the Hummingboard Solo version:
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$ make hummingboard_solo_config
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$ make
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Flashing U-boot into the SD card
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--------------------------------
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- After the 'make' command completes, the generated 'u-boot.imx' binary must be
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flashed into the SD card:
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$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync
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(Note - the SD card node may vary, so adjust this as needed).
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Also, a more detailed explanation on how to format the SD card is available
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at doc/README.imximage.
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- Insert the micro SD card into the slot located in the bottom of the board
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- Connect a 3.3V USB to serial converter cable to the host PC. The MX6 UART
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signals are available in the 26 pin connector as shown at:
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http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
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(Check for "26 pin header layout").
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- Power up the board via USB cable (CON201) and U-boot messages will appear in
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the serial console.
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187
board/solidrun/hummingboard/hummingboard.c
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187
board/solidrun/hummingboard/hummingboard.c
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@ -0,0 +1,187 @@
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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* Copyright (C) 2013 SolidRun ltd.
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* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
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*
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* Authors: Fabio Estevam <fabio.estevam@freescale.com>
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Jon Nettleton <jon.nettleton@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/io.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
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PAD_CTL_HYS)
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#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
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int dram_init(void)
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{
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gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024);
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL),
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};
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#ifdef CONFIG_FSL_ESDHC
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static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{ USDHC2_BASE_ADDR },
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1; /* SD card is the boot medium, so always present */
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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#endif
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#ifdef CONFIG_FEC_MXC
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* AR8035 reset */
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MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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/* AR8035 interrupt */
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MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* GPIO16 -> AR8035 25MHz */
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MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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};
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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gpio_direction_output(ETH_PHY_RESET, 0);
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mdelay(2);
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gpio_set_value(ETH_PHY_RESET, 1);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct iomuxc_base_regs *const iomuxc_regs =
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(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
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int ret = enable_fec_anatop_clock(ENET_25MHz);
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if (ret)
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return ret;
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/* set gpr1[ENET_CLK_SEL] */
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setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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setup_iomux_enet();
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ret = cpu_eth_init(bis);
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if (ret)
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printf("FEC MXC: %s:failed\n", __func__);
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return ret;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Hummingboard\n");
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return 0;
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}
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25
board/solidrun/hummingboard/solo.cfg
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25
board/solidrun/hummingboard/solo.cfg
Normal file
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@ -0,0 +1,25 @@
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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#define __ASSEMBLY__
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#include <config.h>
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#include "asm/arch/mx6-ddr.h"
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#include "asm/arch/iomux.h"
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#include "asm/arch/crm_regs.h"
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#include "../mx6-microsom/ddr-800mhz-32bit-setup.cfg"
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#include "../mx6-microsom/800mhz_2x128mx16.cfg"
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#include "../mx6-microsom/clocks.cfg"
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74
board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
Normal file
74
board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
Normal file
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@ -0,0 +1,74 @@
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2013 SolidRun ltd.
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* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* ZQ Calibrations */
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
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/* write leveling */
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052
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/*
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* DQS gating, read delay, write delay calibration values
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* based on calibration compare of 0x00ffff00
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*/
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034
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/* read data bit delay */
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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/* Complete calibration by forced measurement */
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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/*
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* MMDC init:
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* in DDR3, 32-bit mode, only MMDC0 is initiated:
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*/
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
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DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
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/* CS0_END - 0x2fffffff, 512M */
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
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/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
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DATA 4, 0x021b0400, 0x11420000
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/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
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DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
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/*
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* Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C
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* MR2
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*/
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
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/* MR3 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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/* MR1 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
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/* MR0 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
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/* ZQ calibration */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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/* final DDR setup */
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DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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33
board/solidrun/mx6-microsom/clocks.cfg
Normal file
33
board/solidrun/mx6-microsom/clocks.cfg
Normal file
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2013 SolidRun ltd.
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* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* set the default clock gate to save power */
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DATA 4, CCM_CCGR0, 0x00C03F3F
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DATA 4, CCM_CCGR1, 0x0030FC03
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DATA 4, CCM_CCGR2, 0x0FFFC000
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DATA 4, CCM_CCGR3, 0x3FF00000
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DATA 4, CCM_CCGR4, 0x00FFF300
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DATA 4, CCM_CCGR5, 0x0F0000C3
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DATA 4, CCM_CCGR6, 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
|
||||
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
|
||||
|
||||
/*
|
||||
* Setup CCM_CCOSR register as follows:
|
||||
*
|
||||
* cko1_en = 1 --> CKO1 enabled
|
||||
* cko1_div = 111 --> divide by 8
|
||||
* cko1_sel = 1011 --> ahb_clk_root
|
||||
*
|
||||
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
|
||||
*/
|
||||
DATA 4, CCM_CCOSR, 0x000000fb
|
||||
76
board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
Normal file
76
board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
* Copyright (C) 2013 SolidRun ltd.
|
||||
* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* DDR3 settings
|
||||
* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
|
||||
* memory bus width: 64 bits x16/x32/x64
|
||||
* MX6DL ddr is limited to 800 MHz(400 MHz clock)
|
||||
* memory bus width: 64 bits x16/x32/x64
|
||||
* MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
|
||||
* memory bus width: 32 bits x16/x32
|
||||
*/
|
||||
/* DDR IO TYPE */
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
|
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
||||
/* Clock */
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
|
||||
/* Address */
|
||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00000010
|
||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00000010
|
||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010
|
||||
/* Control */
|
||||
DATA 4, MX6_IOM_DRAM_RESET, 0x00000010
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
|
||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010
|
||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010
|
||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010
|
||||
|
||||
/*
|
||||
* Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS,
|
||||
* CMOS mode saves power, but have less timing margin in case of DDR
|
||||
* timing issue on your board you can try DDR_MODE: [= 0x00020000]
|
||||
*/
|
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
|
||||
|
||||
/*
|
||||
* DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS,
|
||||
* CMOS mode saves power, but have less timing margin in case of DDR
|
||||
* timing issue on your board you can try DDR_MODE: [= 0x00020000]
|
||||
*/
|
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
||||
|
||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
|
||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
|
||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
|
||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
|
||||
DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
|
||||
DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
|
||||
DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
|
||||
DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
|
||||
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
|
||||
|
|
@ -310,6 +310,7 @@ Active arm armv7 mx6 freescale mx6sabresd
|
|||
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de>
|
||||
Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
|
||||
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
|
||||
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
|
||||
Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>
|
||||
|
|
|
|||
226
include/configs/hummingboard.h
Normal file
226
include/configs/hummingboard.h
Normal file
|
|
@ -0,0 +1,226 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2013 SolidRun ltd.
|
||||
* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
|
||||
*
|
||||
* Configuration settings for the SolidRun Hummingboard.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "mx6_common.h"
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/imx-common/gpio.h>
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_MACH_TYPE 4773
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Command definition */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_I2C
|
||||
|
||||
#define CONFIG_CMD_BMODE
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
|
||||
#define CONFIG_LOADADDR 0x12000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000
|
||||
|
||||
/* MMC Configuration */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* Ethernet Configuration */
|
||||
#define CONFIG_FEC_MXC
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_MII
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX6S)
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-hummingboard.dtb"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"update_sd_firmware_filename=u-boot.imx\0" \
|
||||
"update_sd_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if mmc dev ${mmcdev}; then " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${uimage}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H * */
|
||||
Loading…
Reference in a new issue