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Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2013-12-06 10:41:49 +01:00
commit 7988bd4ed6
27 changed files with 7512 additions and 17 deletions
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11
arch/arm/cpu/armv7/rmobile/Makefile
View file

@ -5,16 +5,15 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = lowlevel_init.o
obj-y += cpu_info.o
obj-y = cpu_info.o
obj-y += emac.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
obj-$(CONFIG_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
obj-$(CONFIG_SH73A0) += pfc-sh73a0.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += sh_timer.o
SRCS += $(obj)sh_timer.c

9
arch/arm/cpu/armv7/rmobile/config.mk
View file

@ -1,9 +0,0 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
# Make ARMv5 to allow more compilers to work, even though its v7a.
PLATFORM_CPPFLAGS += -march=armv5

22
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c Normal file
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@ -0,0 +1,22 @@
/*
* arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
* This file is r8a7790 processor support.
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/io.h>
#define PRR 0xFF000044
u32 rmobile_get_cpu_type(void)
{
return (readl(PRR) & 0x00007F00) >> 8;
}
u32 rmobile_get_cpu_rev_integer(void)
{
return (readl(PRR) & 0x000000F0) >> 4;
}

29
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c Normal file
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@ -0,0 +1,29 @@
/*
* arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/io.h>
#define PRR 0xFF000044
u32 rmobile_get_cpu_type(void)
{
u32 product;
product = readl(PRR);
return (u32)((product & 0x00007F00) >> 8);
}
u32 rmobile_get_cpu_rev_integer(void)
{
u32 product;
product = readl(PRR);
return (u32)((product & 0x000000F0) >> 4);
}

10
arch/arm/cpu/armv7/rmobile/cpu_info.c
View file

@ -58,6 +58,16 @@ int print_cpuinfo(void)
rmobile_get_cpu_rev_fraction());
break;
case 0x45:
printf("CPU: Renesas Electronics R8A7790 rev %d\n",
rmobile_get_cpu_rev_integer());
break;
case 0x47:
printf("CPU: Renesas Electronics R8A7791 rev %d\n",
rmobile_get_cpu_rev_integer());
break;
default:
printf("CPU: Renesas Electronics CPU rev %d.%d\n",
rmobile_get_cpu_rev_integer(),

60
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S Normal file
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@ -0,0 +1,60 @@
/*
* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
* This file is lager low level initialize.
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
mrc p15, 0, r4, c0, c0, 5 /* mpidr */
orr r4, r4, r4, lsr #6
and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
b do_lowlevel_init
.pool
/*
* CPU ID #1-#3 come here
*/
.align 4
do_cpu_waiting:
ldr r1, =0xe6180000 /* sysc */
1: ldr r0, [r1, #0x20] /* sbar */
tst r0, r0
beq 1b
bx r0
/*
* Only CPU ID #0 comes here
*/
.align 4
do_lowlevel_init:
/* surpress wfe if ca15 */
tst r4, #4
mrceq p15, 0, r0, c1, c0, 1 /* actlr */
orreq r0, r0, #(1<<7)
mcreq p15, 0, r0, c1, c0, 1
/* and set l2 latency */
mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */
orreq r0, r0, #0x00000800
orreq r0, r0, #0x00000003
mcreq p15, 1, r0, c9, c0, 2
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]
/* initialize system */
bl s_init
ldr lr, [sp]
mov pc, lr
nop
ENDPROC(lowlevel_init)
.ltorg

829
arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c Normal file
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@ -0,0 +1,829 @@
/*
* arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
* This file is r8a7790 processor support - PFC hardware block.
*
* Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Magnus Damm
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <sh_pfc.h>
#include <asm/gpio.h>
#include "pfc-r8a7790.h"
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
GP_ALL(IN),
PINMUX_INPUT_END,
PINMUX_OUTPUT_BEGIN,
GP_ALL(OUT),
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
/* GPSR0 */
FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
FN_IP3_14_12, FN_IP3_17_15,
/* GPSR1 */
FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
/* GPSR2 */
FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
/* GPSR3 */
FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
/* GPSR4 */
FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
FN_IP14_15_12, FN_IP14_18_16,
/* GPSR5 */
FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
/* IPSR0 - IPSR5 */
/* IPSR6 */
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F,
/* IPSR7 */
FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
FN_MII_RXD2,
/* IPSR8 - IPSR16 */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
FN_SEL_SCIF1_4,
FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
FN_SEL_SCIFB1_4,
FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
FN_SEL_SCFA_0, FN_SEL_SCFA_1,
FN_SEL_SOF1_0, FN_SEL_SOF1_1,
FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
FN_SEL_SSI6_0, FN_SEL_SSI6_1,
FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
FN_SEL_VI3_0, FN_SEL_VI3_1,
FN_SEL_VI2_0, FN_SEL_VI2_1,
FN_SEL_VI1_0, FN_SEL_VI1_1,
FN_SEL_VI0_0, FN_SEL_VI0_1,
FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
FN_SEL_LBS_0, FN_SEL_LBS_1,
FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
FN_SEL_SOF3_0, FN_SEL_SOF3_1,
FN_SEL_SOF0_0, FN_SEL_SOF0_1,
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
FN_SEL_CAN1_0, FN_SEL_CAN1_1,
FN_SEL_ADI_0, FN_SEL_ADI_1,
FN_SEL_SSP_0, FN_SEL_SSP_1,
FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
FN_SEL_IIC0_0, FN_SEL_IIC0_1,
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
FN_SEL_IIC2_4,
FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
FN_SEL_I2C2_4,
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
MII_RXD2_MARK,
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_IPSR_DATA(IP6_2_0, DACK0),
PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
PINMUX_IPSR_DATA(IP6_8_6, DACK1),
PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
PINMUX_IPSR_DATA(IP6_13_11, DACK2),
PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_18_16, PWM0),
PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_21_19, PWM1),
PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
PINMUX_IPSR_DATA(IP7_24_22, PWM2),
PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
};
static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO_GP_ALL(),
/*IPSR0 - IPSR5*/
/*IPSR6*/
GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB),
GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B),
GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B),
GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B),
GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2),
GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B),
GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV),
GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D),
GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E),
GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B),
GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E),
GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0),
GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C),
GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1),
GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B),
GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G),
GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E),
GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E),
GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E),
GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F),
/*IPSR7*/
GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E),
GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1),
GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G),
GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN),
GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC),
GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0),
GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C),
GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC),
GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C),
GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B),
GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1),
GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C),
GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0),
GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C),
GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C),
GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
/*IPSR8 - IPSR16*/
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
GP_0_31_FN, FN_IP3_17_15,
GP_0_30_FN, FN_IP3_14_12,
GP_0_29_FN, FN_IP3_11_8,
GP_0_28_FN, FN_IP3_7_4,
GP_0_27_FN, FN_IP3_3_0,
GP_0_26_FN, FN_IP2_28_26,
GP_0_25_FN, FN_IP2_25_22,
GP_0_24_FN, FN_IP2_21_18,
GP_0_23_FN, FN_IP2_17_15,
GP_0_22_FN, FN_IP2_14_12,
GP_0_21_FN, FN_IP2_11_9,
GP_0_20_FN, FN_IP2_8_6,
GP_0_19_FN, FN_IP2_5_3,
GP_0_18_FN, FN_IP2_2_0,
GP_0_17_FN, FN_IP1_29_28,
GP_0_16_FN, FN_IP1_27_26,
GP_0_15_FN, FN_IP1_25_22,
GP_0_14_FN, FN_IP1_21_18,
GP_0_13_FN, FN_IP1_17_15,
GP_0_12_FN, FN_IP1_14_12,
GP_0_11_FN, FN_IP1_11_8,
GP_0_10_FN, FN_IP1_7_4,
GP_0_9_FN, FN_IP1_3_0,
GP_0_8_FN, FN_IP0_30_27,
GP_0_7_FN, FN_IP0_26_23,
GP_0_6_FN, FN_IP0_22_20,
GP_0_5_FN, FN_IP0_19_16,
GP_0_4_FN, FN_IP0_15_12,
GP_0_3_FN, FN_IP0_11_9,
GP_0_2_FN, FN_IP0_8_6,
GP_0_1_FN, FN_IP0_5_3,
GP_0_0_FN, FN_IP0_2_0 }
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
0, 0,
0, 0,
GP_1_29_FN, FN_IP6_13_11,
GP_1_28_FN, FN_IP6_10_9,
GP_1_27_FN, FN_IP6_8_6,
GP_1_26_FN, FN_IP6_5_3,
GP_1_25_FN, FN_IP6_2_0,
GP_1_24_FN, FN_IP5_29_27,
GP_1_23_FN, FN_IP5_26_24,
GP_1_22_FN, FN_IP5_23_21,
GP_1_21_FN, FN_IP5_20_18,
GP_1_20_FN, FN_IP5_17_15,
GP_1_19_FN, FN_IP5_14_13,
GP_1_18_FN, FN_IP5_12_10,
GP_1_17_FN, FN_IP5_9_6,
GP_1_16_FN, FN_IP5_5_3,
GP_1_15_FN, FN_IP5_2_0,
GP_1_14_FN, FN_IP4_29_27,
GP_1_13_FN, FN_IP4_26_24,
GP_1_12_FN, FN_IP4_23_21,
GP_1_11_FN, FN_IP4_20_18,
GP_1_10_FN, FN_IP4_17_15,
GP_1_9_FN, FN_IP4_14_12,
GP_1_8_FN, FN_IP4_11_9,
GP_1_7_FN, FN_IP4_8_6,
GP_1_6_FN, FN_IP4_5_3,
GP_1_5_FN, FN_IP4_2_0,
GP_1_4_FN, FN_IP3_31_29,
GP_1_3_FN, FN_IP3_28_26,
GP_1_2_FN, FN_IP3_25_23,
GP_1_1_FN, FN_IP3_22_20,
GP_1_0_FN, FN_IP3_19_18, }
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
0, 0,
0, 0,
GP_2_29_FN, FN_IP7_15_13,
GP_2_28_FN, FN_IP7_12_10,
GP_2_27_FN, FN_IP7_9_8,
GP_2_26_FN, FN_IP7_7_6,
GP_2_25_FN, FN_IP7_5_3,
GP_2_24_FN, FN_IP7_2_0,
GP_2_23_FN, FN_IP6_31_29,
GP_2_22_FN, FN_IP6_28_26,
GP_2_21_FN, FN_IP6_25_23,
GP_2_20_FN, FN_IP6_22_20,
GP_2_19_FN, FN_IP6_19_17,
GP_2_18_FN, FN_IP6_16_14,
GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
GP_2_16_FN, FN_IP8_27,
GP_2_15_FN, FN_IP8_26,
GP_2_14_FN, FN_IP8_25_24,
GP_2_13_FN, FN_IP8_23_22,
GP_2_12_FN, FN_IP8_21_20,
GP_2_11_FN, FN_IP8_19_18,
GP_2_10_FN, FN_IP8_17_16,
GP_2_9_FN, FN_IP8_15_14,
GP_2_8_FN, FN_IP8_13_12,
GP_2_7_FN, FN_IP8_11_10,
GP_2_6_FN, FN_IP8_9_8,
GP_2_5_FN, FN_IP8_7_6,
GP_2_4_FN, FN_IP8_5_4,
GP_2_3_FN, FN_IP8_3_2,
GP_2_2_FN, FN_IP8_1_0,
GP_2_1_FN, FN_IP7_30_29,
GP_2_0_FN, FN_IP7_28_27 }
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
GP_3_31_FN, FN_IP11_21_18,
GP_3_30_FN, FN_IP11_17_15,
GP_3_29_FN, FN_IP11_14_13,
GP_3_28_FN, FN_IP11_12_11,
GP_3_27_FN, FN_IP11_10_9,
GP_3_26_FN, FN_IP11_8_7,
GP_3_25_FN, FN_IP11_6_5,
GP_3_24_FN, FN_IP11_4,
GP_3_23_FN, FN_IP11_3_0,
GP_3_22_FN, FN_IP10_29_26,
GP_3_21_FN, FN_IP10_25_23,
GP_3_20_FN, FN_IP10_22_19,
GP_3_19_FN, FN_IP10_18_15,
GP_3_18_FN, FN_IP10_14_11,
GP_3_17_FN, FN_IP10_10_7,
GP_3_16_FN, FN_IP10_6_4,
GP_3_15_FN, FN_IP10_3_0,
GP_3_14_FN, FN_IP9_31_28,
GP_3_13_FN, FN_IP9_27_26,
GP_3_12_FN, FN_IP9_25_24,
GP_3_11_FN, FN_IP9_23_22,
GP_3_10_FN, FN_IP9_21_20,
GP_3_9_FN, FN_IP9_19_18,
GP_3_8_FN, FN_IP9_17_16,
GP_3_7_FN, FN_IP9_15_12,
GP_3_6_FN, FN_IP9_11_8,
GP_3_5_FN, FN_IP9_7_6,
GP_3_4_FN, FN_IP9_5_4,
GP_3_3_FN, FN_IP9_3_2,
GP_3_2_FN, FN_IP9_1_0,
GP_3_1_FN, FN_IP8_30_29,
GP_3_0_FN, FN_IP8_28 }
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
GP_4_31_FN, FN_IP14_18_16,
GP_4_30_FN, FN_IP14_15_12,
GP_4_29_FN, FN_IP14_11_9,
GP_4_28_FN, FN_IP14_8_6,
GP_4_27_FN, FN_IP14_5_3,
GP_4_26_FN, FN_IP14_2_0,
GP_4_25_FN, FN_IP13_30_29,
GP_4_24_FN, FN_IP13_28_26,
GP_4_23_FN, FN_IP13_25_23,
GP_4_22_FN, FN_IP13_22_19,
GP_4_21_FN, FN_IP13_18_16,
GP_4_20_FN, FN_IP13_15_13,
GP_4_19_FN, FN_IP13_12_10,
GP_4_18_FN, FN_IP13_9_7,
GP_4_17_FN, FN_IP13_6_3,
GP_4_16_FN, FN_IP13_2_0,
GP_4_15_FN, FN_IP12_30_28,
GP_4_14_FN, FN_IP12_27_25,
GP_4_13_FN, FN_IP12_24_23,
GP_4_12_FN, FN_IP12_22_20,
GP_4_11_FN, FN_IP12_19_17,
GP_4_10_FN, FN_IP12_16_14,
GP_4_9_FN, FN_IP12_13_11,
GP_4_8_FN, FN_IP12_10_8,
GP_4_7_FN, FN_IP12_7_6,
GP_4_6_FN, FN_IP12_5_4,
GP_4_5_FN, FN_IP12_3_2,
GP_4_4_FN, FN_IP12_1_0,
GP_4_3_FN, FN_IP11_31_30,
GP_4_2_FN, FN_IP11_29_27,
GP_4_1_FN, FN_IP11_26_24,
GP_4_0_FN, FN_IP11_23_22 }
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
GP_5_31_FN, FN_IP7_24_22,
GP_5_30_FN, FN_IP7_21_19,
GP_5_29_FN, FN_IP7_18_16,
GP_5_28_FN, FN_DU_DOTCLKIN2,
GP_5_27_FN, FN_IP7_26_25,
GP_5_26_FN, FN_DU_DOTCLKIN0,
GP_5_25_FN, FN_AVS2,
GP_5_24_FN, FN_AVS1,
GP_5_23_FN, FN_USB2_OVC,
GP_5_22_FN, FN_USB2_PWEN,
GP_5_21_FN, FN_IP16_7,
GP_5_20_FN, FN_IP16_6,
GP_5_19_FN, FN_USB0_OVC_VBUS,
GP_5_18_FN, FN_USB0_PWEN,
GP_5_17_FN, FN_IP16_5_3,
GP_5_16_FN, FN_IP16_2_0,
GP_5_15_FN, FN_IP15_29_28,
GP_5_14_FN, FN_IP15_27_26,
GP_5_13_FN, FN_IP15_25_23,
GP_5_12_FN, FN_IP15_22_20,
GP_5_11_FN, FN_IP15_19_18,
GP_5_10_FN, FN_IP15_17_16,
GP_5_9_FN, FN_IP15_15_14,
GP_5_8_FN, FN_IP15_13_12,
GP_5_7_FN, FN_IP15_11_9,
GP_5_6_FN, FN_IP15_8_6,
GP_5_5_FN, FN_IP15_5_3,
GP_5_4_FN, FN_IP15_2_0,
GP_5_3_FN, FN_IP14_30_28,
GP_5_2_FN, FN_IP14_27_25,
GP_5_1_FN, FN_IP14_24_22,
GP_5_0_FN, FN_IP14_21_19 }
},
/*IPSR0 - IPSR5*/
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
/* IP6_31_29 [3] */
FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
/* IP6_28_26 [3] */
FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
/* IP6_25_23 [3] */
FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
/* IP6_22_20 [3] */
FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
/* IP6_19_17 [3] */
FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
/* IP6_16_14 [3] */
FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
FN_SCL2_CIS_E, 0,
/* IP6_13_11 [3] */
FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
/* IP6_10_9 [2] */
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
/* IP6_8_6 [3] */
FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
FN_SSI_SDATA8_C, 0, 0, 0,
/* IP6_5_3 [3] */
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
/* IP6_2_0 [3] */
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
/* IP7_31 [1] */
0, 0,
/* IP7_30_29 [2] */
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
FN_MII_RXD2,
/* IP7_28_27 [2] */
FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
/* IP7_26_25 [2] */
FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
/* IP7_24_22 [3] */
FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
0, 0, 0,
/* IP7_21_19 [3] */
FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
/* IP7_18_16 [3] */
FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
FN_GLO_SS_C, 0, 0, 0,
/* IP7_15_13 [3] */
FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
/* IP7_12_10 [3] */
FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
FN_GLO_SCLK_C, 0, 0, 0,
/* IP7_9_8 [2] */
FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
/* IP7_7_6 [2] */
FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
/* IP7_5_3 [3] */
FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
0, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
},
/*IPSR8 - IPSR16*/
{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
0, 0,
0, 0,
GP_1_29_IN, GP_1_29_OUT,
GP_1_28_IN, GP_1_28_OUT,
GP_1_27_IN, GP_1_27_OUT,
GP_1_26_IN, GP_1_26_OUT,
GP_1_25_IN, GP_1_25_OUT,
GP_1_24_IN, GP_1_24_OUT,
GP_1_23_IN, GP_1_23_OUT,
GP_1_22_IN, GP_1_22_OUT,
GP_1_21_IN, GP_1_21_OUT,
GP_1_20_IN, GP_1_20_OUT,
GP_1_19_IN, GP_1_19_OUT,
GP_1_18_IN, GP_1_18_OUT,
GP_1_17_IN, GP_1_17_OUT,
GP_1_16_IN, GP_1_16_OUT,
GP_1_15_IN, GP_1_15_OUT,
GP_1_14_IN, GP_1_14_OUT,
GP_1_13_IN, GP_1_13_OUT,
GP_1_12_IN, GP_1_12_OUT,
GP_1_11_IN, GP_1_11_OUT,
GP_1_10_IN, GP_1_10_OUT,
GP_1_9_IN, GP_1_9_OUT,
GP_1_8_IN, GP_1_8_OUT,
GP_1_7_IN, GP_1_7_OUT,
GP_1_6_IN, GP_1_6_OUT,
GP_1_5_IN, GP_1_5_OUT,
GP_1_4_IN, GP_1_4_OUT,
GP_1_3_IN, GP_1_3_OUT,
GP_1_2_IN, GP_1_2_OUT,
GP_1_1_IN, GP_1_1_OUT,
GP_1_0_IN, GP_1_0_OUT, }
},
{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
0, 0,
0, 0,
GP_2_29_IN, GP_2_29_OUT,
GP_2_28_IN, GP_2_28_OUT,
GP_2_27_IN, GP_2_27_OUT,
GP_2_26_IN, GP_2_26_OUT,
GP_2_25_IN, GP_2_25_OUT,
GP_2_24_IN, GP_2_24_OUT,
GP_2_23_IN, GP_2_23_OUT,
GP_2_22_IN, GP_2_22_OUT,
GP_2_21_IN, GP_2_21_OUT,
GP_2_20_IN, GP_2_20_OUT,
GP_2_19_IN, GP_2_19_OUT,
GP_2_18_IN, GP_2_18_OUT,
GP_2_17_IN, GP_2_17_OUT,
GP_2_16_IN, GP_2_16_OUT,
GP_2_15_IN, GP_2_15_OUT,
GP_2_14_IN, GP_2_14_OUT,
GP_2_13_IN, GP_2_13_OUT,
GP_2_12_IN, GP_2_12_OUT,
GP_2_11_IN, GP_2_11_OUT,
GP_2_10_IN, GP_2_10_OUT,
GP_2_9_IN, GP_2_9_OUT,
GP_2_8_IN, GP_2_8_OUT,
GP_2_7_IN, GP_2_7_OUT,
GP_2_6_IN, GP_2_6_OUT,
GP_2_5_IN, GP_2_5_OUT,
GP_2_4_IN, GP_2_4_OUT,
GP_2_3_IN, GP_2_3_OUT,
GP_2_2_IN, GP_2_2_OUT,
GP_2_1_IN, GP_2_1_OUT,
GP_2_0_IN, GP_2_0_OUT, }
},
{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
{ },
};
static struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
0, 0, GP_1_29_DATA, GP_1_28_DATA,
GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
},
{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
0, 0, GP_2_29_DATA, GP_2_28_DATA,
GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
},
{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
{ },
};
static struct pinmux_info r8a7790_pinmux_info = {
.name = "r8a7790_pfc",
.unlock_reg = 0xe6060000, /* PMMR */
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_GP_0_0,
.last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */,
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
};
void r8a7790_pinmux_init(void)
{
register_pinmux(&r8a7790_pinmux_info);
}

92
arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h Normal file
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@ -0,0 +1,92 @@
/*
* arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __PFC_R8A7790_H__
#define __PFC_R8A7790_H__
#include <sh_pfc.h>
#include <asm/gpio.h>
#define CPU_32_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_1(fn, pfx##31, sfx)
#define CPU_32_PORT2(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx)
#if defined(CONFIG_R8A7790)
#define CPU_32_PORT1(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx) \
/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT(fn, pfx##_0_, sfx), \
CPU_32_PORT1(fn, pfx##_1_, sfx), \
CPU_32_PORT2(fn, pfx##_2_, sfx), \
CPU_32_PORT(fn, pfx##_3_, sfx), \
CPU_32_PORT(fn, pfx##_4_, sfx), \
CPU_32_PORT(fn, pfx##_5_, sfx)
#elif defined(CONFIG_R8A7791)
#define CPU_32_PORT1(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
/*
* GP_0_0_DATA -> GP_7_25_DATA
* (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
* GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
*/
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT(fn, pfx##_0_, sfx), \
CPU_32_PORT1(fn, pfx##_1_, sfx), \
CPU_32_PORT(fn, pfx##_2_, sfx), \
CPU_32_PORT(fn, pfx##_3_, sfx), \
CPU_32_PORT(fn, pfx##_4_, sfx), \
CPU_32_PORT(fn, pfx##_5_, sfx), \
CPU_32_PORT(fn, pfx##_6_, sfx), \
CPU_32_PORT1(fn, pfx##_7_, sfx)
#else
#error "NO support"
#endif
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
GP##pfx##_IN, GP##pfx##_OUT)
#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
#define PORT_10_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
#define CPU_32_PORT_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
PORT_10_REV(fn, pfx, sfx)
#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
#endif /* __PFC_R8A7790_H__ */

1117
arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c Normal file
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File diff suppressed because it is too large Load diff

8
arch/arm/cpu/armv7/rmobile/timer.c
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@ -6,6 +6,7 @@
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/arch-armv7/globaltimer.h>
#include <asm/arch/rmobile.h>
@ -38,13 +39,16 @@ static u64 get_time_us(void)
u64 timer = get_cpu_global_timer();
timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK);
do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
return timer;
}
static ulong get_time_ms(void)
{
return (ulong)(get_time_us() / 1000);
u64 us = get_time_us();
do_div(us, 1000);
return us;
}
int timer_init(void)

6
arch/arm/include/asm/arch-rmobile/gpio.h
View file

@ -7,6 +7,12 @@ void sh73a0_pinmux_init(void);
#elif defined(CONFIG_R8A7740)
#include "r8a7740-gpio.h"
void r8a7740_pinmux_init(void);
#elif defined(CONFIG_R8A7790)
#include "r8a7790-gpio.h"
void r8a7790_pinmux_init(void);
#elif defined(CONFIG_R8A7791)
#include "r8a7791-gpio.h"
void r8a7791_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */

387
arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h Normal file
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@ -0,0 +1,387 @@
#ifndef __ASM_R8A7790_H__
#define __ASM_R8A7790_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
*/
enum {
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
GPIO_GP_1_28, GPIO_GP_1_29,
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
GPIO_GP_2_28, GPIO_GP_2_29,
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS,
GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2,
GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2,
/* IPSR0 */
GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5,
GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2,
GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B,
GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4,
GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4,
GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5,
GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5,
GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6,
GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B,
GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C,
GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C,
GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0,
GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0,
/* IPSR1 */
GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1,
GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10,
GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2,
GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11,
GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3,
GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3,
GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4,
GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4,
GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N,
GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14,
GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B,
GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6,
GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B,
GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7,
GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4,
/* IPSR2 */
GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3,
GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B,
GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1,
GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7,
GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3,
GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4,
GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B,
GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5,
GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B,
GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6,
GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B,
/* IPSR3 */
GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0,
GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B,
GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1,
GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B,
GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2,
GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2,
GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B,
GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15,
GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16,
GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N,
GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19,
GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20,
GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4,
/* IPSR4 */
GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B,
GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5,
GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2,
GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24,
GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB,
GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6,
GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N,
GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B,
GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B,
GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B,
GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B,
GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK,
GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B,
GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B,
GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2,
/* IPSR5 */
GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1,
GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N,
GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N,
GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B,
GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX,
GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2,
GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N,
GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B,
GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N,
GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3,
GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B,
GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK,
GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B,
GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4,
GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B,
GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N,
GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B,
GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N,
GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C,
GPIO_FN_SSI_WS78_B,
/* IPSR6 */
GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B,
GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C,
GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B,
GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1,
GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C,
GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B,
GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N,
GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B,
GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B,
GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E,
GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER,
GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C,
GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0,
GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C,
GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1,
GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B,
GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G,
GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E,
GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E,
GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E,
GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F,
/* IPSR7 */
GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E,
GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1,
GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F,
GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C,
GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC,
GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0,
GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C,
GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B,
GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0,
GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C,
GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C,
GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C,
GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C,
GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN,
GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK,
GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1,
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2,
GPIO_FN_MII_RXD2,
/* IPSR8 */
GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3,
GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N,
GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N,
GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N,
GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1,
GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER,
GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK,
GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV,
GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D,
GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1,
GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC,
GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO,
GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D,
GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D,
GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5,
GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK,
GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD,
GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B,
/* IPSR9 */
GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B,
GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B,
GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B,
GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B,
GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP,
GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B,
GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP,
GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN,
GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B,
GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK,
GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD,
GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B,
GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK,
GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK,
GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2,
GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B,
GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0,
GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6,
GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B,
GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B,
GPIO_FN_VI3_CLK_B,
/* IPSR10 */
GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN,
GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D,
GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK,
GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B,
GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D,
GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D,
GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B,
GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B,
GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D,
GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B,
GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA,
GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D,
GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B,
GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK,
GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B,
GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3,
GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B,
GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B,
GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4,
GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0,
GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B,
GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B,
/* IPSR11 */
GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN,
GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D,
GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B,
GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD,
GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N,
GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2,
GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3,
GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1,
GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP,
GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C,
GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F,
GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B,
GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B,
GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN,
GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C,
GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B,
GPIO_FN_MOUT0,
/* IPSR12 */
GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1,
GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2,
GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5,
GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6,
GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK,
GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34,
GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC,
GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0,
GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK,
GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N,
GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0,
GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N,
GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1,
GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD,
GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK,
GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS,
GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD,
GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE,
GPIO_FN_CAN_DEBUGOUT4,
/* IPSR13 */
GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2,
GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6,
GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C,
GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6,
GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6,
GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4,
GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6,
GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5,
GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1,
GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6,
GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1,
GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7,
GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7,
GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N,
GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11,
GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B,
GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8,
GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C,
GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9,
GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1,
GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA,
GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14,
/* IPSR14 */
GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D,
GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15,
GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0,
GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C,
GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0,
GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1,
GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N,
GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3,
GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C,
GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS,
GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B,
GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1,
GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1,
GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK,
GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK,
GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS,
GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE,
GPIO_FN_HRTS0_N_C,
/* IPSR15 */
GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7,
GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN,
GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS,
GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17,
GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0,
GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0,
GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3,
GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4,
GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5,
GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK,
GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0,
GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23,
GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0,
GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1,
GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14,
/* IPSR16 */
GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2,
GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B,
GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2,
GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C,
GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC,
GPIO_FN_TCLK1_B,
};
#endif /* __ASM_R8A7790_H__ */

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arch/arm/include/asm/arch-rmobile/r8a7790.h Normal file
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/*
* arch/arm/include/asm/arch-rmobile/r8a7790.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7790_H
#define __ASM_ARCH_R8A7790_H
/*
* R8A7790 I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xFEC00200
#define DBSC3_0_BASE 0xE6790000
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define S3C_QOS_DCACHE_BASE 0xE6784BDC
#define S3C_QOS_CCI0_BASE 0xE6784C00
#define S3C_QOS_CCI1_BASE 0xE6784C24
#define S3C_QOS_MXI_BASE 0xE6784C48
#define S3C_QOS_AXI_BASE 0xE6784C6C
#define DBSC3_0_QOS_R0_BASE 0xE6791000
#define DBSC3_0_QOS_R1_BASE 0xE6791100
#define DBSC3_0_QOS_R2_BASE 0xE6791200
#define DBSC3_0_QOS_R3_BASE 0xE6791300
#define DBSC3_0_QOS_R4_BASE 0xE6791400
#define DBSC3_0_QOS_R5_BASE 0xE6791500
#define DBSC3_0_QOS_R6_BASE 0xE6791600
#define DBSC3_0_QOS_R7_BASE 0xE6791700
#define DBSC3_0_QOS_R8_BASE 0xE6791800
#define DBSC3_0_QOS_R9_BASE 0xE6791900
#define DBSC3_0_QOS_R10_BASE 0xE6791A00
#define DBSC3_0_QOS_R11_BASE 0xE6791B00
#define DBSC3_0_QOS_R12_BASE 0xE6791C00
#define DBSC3_0_QOS_R13_BASE 0xE6791D00
#define DBSC3_0_QOS_R14_BASE 0xE6791E00
#define DBSC3_0_QOS_R15_BASE 0xE6791F00
#define DBSC3_0_QOS_W0_BASE 0xE6792000
#define DBSC3_0_QOS_W1_BASE 0xE6792100
#define DBSC3_0_QOS_W2_BASE 0xE6792200
#define DBSC3_0_QOS_W3_BASE 0xE6792300
#define DBSC3_0_QOS_W4_BASE 0xE6792400
#define DBSC3_0_QOS_W5_BASE 0xE6792500
#define DBSC3_0_QOS_W6_BASE 0xE6792600
#define DBSC3_0_QOS_W7_BASE 0xE6792700
#define DBSC3_0_QOS_W8_BASE 0xE6792800
#define DBSC3_0_QOS_W9_BASE 0xE6792900
#define DBSC3_0_QOS_W10_BASE 0xE6792A00
#define DBSC3_0_QOS_W11_BASE 0xE6792B00
#define DBSC3_0_QOS_W12_BASE 0xE6792C00
#define DBSC3_0_QOS_W13_BASE 0xE6792D00
#define DBSC3_0_QOS_W14_BASE 0xE6792E00
#define DBSC3_0_QOS_W15_BASE 0xE6792F00
#define DBSC3_0_DBADJ2 0xE67900C8
#define CCI_400_MAXOT_1 0xF0091110
#define CCI_400_MAXOT_2 0xF0092110
#define CCI_400_QOSCNTL_1 0xF009110C
#define CCI_400_QOSCNTL_2 0xF009210C
#define MXI_BASE 0xFE960000
#define MXI_QOS_BASE 0xFE960300
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
#define SYS_AXI_IMUX0_BASE 0xFF800600
#define SYS_AXI_IMUX1_BASE 0xFF800640
#define SYS_AXI_IMUX2_BASE 0xFF800680
#define SYS_AXI_LBS_BASE 0xFF8006C0
#define SYS_AXI_MMUDS_BASE 0xFF800700
#define SYS_AXI_MMUM_BASE 0xFF800740
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_RDS_BASE 0xFF8101C0
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
#define MP_AXI_ASDS1_BASE 0xFF820200
#define MP_AXI_MLP_BASE 0xFF820240
#define MP_AXI_MMUMP_BASE 0xFF820280
#define MP_AXI_SPU_BASE 0xFF8202C0
#define MP_AXI_SPUC_BASE 0xFF820300
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
#define CCI_AXI_MMUR_BASE 0xFF880180
#define CCI_AXI_MMUDS_BASE 0xFF8801C0
#define CCI_AXI_MMUM_BASE 0xFF880200
#define CCI_AXI_MXI_BASE 0xFF880240
#define CCI_AXI_MMUS1_BASE 0xFF880280
#define CCI_AXI_MMUMP_BASE 0xFF8802C0
#define MEDIA_AXI_JPR_BASE 0xFE964100
#define MEDIA_AXI_JPW_BASE 0xFE966100
#define MEDIA_AXI_GCU0R_BASE 0xFE964140
#define MEDIA_AXI_GCU0W_BASE 0xFE966140
#define MEDIA_AXI_GCU1R_BASE 0xFE964180
#define MEDIA_AXI_GCU1W_BASE 0xFE966180
#define MEDIA_AXI_TDMR_BASE 0xFE964500
#define MEDIA_AXI_TDMW_BASE 0xFE966500
#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
#define MEDIA_AXI_IMSW_BASE 0xFE966D80
#define MEDIA_AXI_VSP1R_BASE 0xFE965100
#define MEDIA_AXI_VSP1W_BASE 0xFE967100
#define MEDIA_AXI_FDP1R_BASE 0xFE965140
#define MEDIA_AXI_FDP1W_BASE 0xFE967140
#define MEDIA_AXI_IMRR_BASE 0xFE965180
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
#define MEDIA_AXI_VPC0R_BASE 0xFE965980
#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
#define SYS_AXI_CSDMSCR 0xFF802014
#define SYS_AXI_DDMDMSCR 0xFF802018
#define SYS_AXI_ETHDMSCR 0xFF80201C
#define SYS_AXI_G2DDMSCR 0xFF802020
#define SYS_AXI_IMP0DMSCR 0xFF802024
#define SYS_AXI_IMP1DMSCR 0xFF802028
#define SYS_AXI_LBSDMSCR 0xFF80202C
#define SYS_AXI_MMUDSDMSCR 0xFF802030
#define SYS_AXI_MMUMXDMSCR 0xFF802034
#define SYS_AXI_MMURDDMSCR 0xFF802038
#define SYS_AXI_MMUS0DMSCR 0xFF80203C
#define SYS_AXI_MMUS1DMSCR 0xFF802040
#define SYS_AXI_MPXDMSCR 0xFF802044
#define SYS_AXI_MTSB0DMSCR 0xFF802048
#define SYS_AXI_MTSB1DMSCR 0xFF80204C
#define SYS_AXI_PCIDMSCR 0xFF802050
#define SYS_AXI_RTXDMSCR 0xFF802054
#define SYS_AXI_SAT0DMSCR 0xFF802058
#define SYS_AXI_SAT1DMSCR 0xFF80205C
#define SYS_AXI_SDM0DMSCR 0xFF802060
#define SYS_AXI_SDM1DMSCR 0xFF802064
#define SYS_AXI_SDS0DMSCR 0xFF802068
#define SYS_AXI_SDS1DMSCR 0xFF80206C
#define SYS_AXI_ETRABDMSCR 0xFF802070
#define SYS_AXI_ETRKFDMSCR 0xFF802074
#define SYS_AXI_UDM0DMSCR 0xFF802078
#define SYS_AXI_UDM1DMSCR 0xFF80207C
#define SYS_AXI_USB20DMSCR 0xFF802080
#define SYS_AXI_USB21DMSCR 0xFF802084
#define SYS_AXI_USB22DMSCR 0xFF802088
#define SYS_AXI_USB30DMSCR 0xFF80208C
#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
#define SYS_AXI_LBSSLVDMSCR 0xFF802128
#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
#define SYS_AXI_MPXSLVDMSCR 0xFF802134
#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
#define SYS_AXI_MXTSLVDMSCR 0xFF802140
#define SYS_AXI_PCISLVDMSCR 0xFF802144
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
#define RT_AXI_RDMDMSCR 0xFF812008
#define RT_AXI_RDSDMSCR 0xFF81200C
#define RT_AXI_STRDMSCR 0xFF812010
#define RT_AXI_SY2RTDMSCR 0xFF812014
#define RT_AXI_CBSSLVDMSCR 0xFF812100
#define RT_AXI_DBSSLVDMSCR 0xFF812104
#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
#define MP_AXI_ADSPDMSCR 0xFF822000
#define MP_AXI_ASDM0DMSCR 0xFF822004
#define MP_AXI_ASDM1DMSCR 0xFF822008
#define MP_AXI_ASDS0DMSCR 0xFF82200C
#define MP_AXI_ASDS1DMSCR 0xFF822010
#define MP_AXI_MLPDMSCR 0xFF822014
#define MP_AXI_MMUMPDMSCR 0xFF822018
#define MP_AXI_SPUDMSCR 0xFF82201C
#define MP_AXI_SPUCDMSCR 0xFF822020
#define MP_AXI_SY2MPDMSCR 0xFF822024
#define MP_AXI_ADSPSLVDMSCR 0xFF822100
#define MP_AXI_MLMSLVDMSCR 0xFF822104
#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
#define MP_AXI_SPUSLVDMSCR 0xFF822128
#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
#define ADM_AXI_ASDM0DMSCR 0xFF842000
#define ADM_AXI_ASDM1DMSCR 0xFF842004
#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
#define DM_AXI_RAP5SLVDMSCR 0xFF852110
#define DM_AXI_SAP4SLVDMSCR 0xFF852114
#define DM_AXI_SAP5SLVDMSCR 0xFF852118
#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
#define DM_AXI_SAP65SLVDMSCR 0xFF852120
#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
#define SYS_AXI256_MXIDMSCR 0xFF862008
#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
#define MXT_FDPSLVDMSCR 0xFF87210C
#define MXT_IMRSLVDMSCR 0xFF872110
#define MXT_VINSLVDMSCR 0xFF872114
#define MXT_VPC0SLVDMSCR 0xFF872118
#define MXT_VPC1SLVDMSCR 0xFF87211C
#define MXT_VSP0SLVDMSCR 0xFF872120
#define MXT_VSP1SLVDMSCR 0xFF872124
#define MXT_VSPD0SLVDMSCR 0xFF872128
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
#define CCI_AXI_MMURDMSCR 0xFF882008
#define CCI_AXI_MMUDSDMSCR 0xFF88200C
#define CCI_AXI_MMUMDMSCR 0xFF882010
#define CCI_AXI_MXIDMSCR 0xFF882014
#define CCI_AXI_MMUS1DMSCR 0xFF882018
#define CCI_AXI_MMUMPDMSCR 0xFF88201C
#define CCI_AXI_DVMDMSCR 0xFF882020
#define CCI_AXI_CCISLVDMSCR 0xFF882100
#define CCI_AXI_IPMMUIDVMCR 0xFF880400
#define CCI_AXI_IPMMURDVMCR 0xFF880404
#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
#define CCI_AXI_AX2ADDRMASK 0xFF88041C
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct r8a7790_rwdt {
u32 rwtcnt; /* 0x00 */
u32 rwtcsra; /* 0x04 */
u16 rwtcsrb; /* 0x08 */
};
/* SWDT */
struct r8a7790_swdt {
u32 swtcnt; /* 0x00 */
u32 swtcsra; /* 0x04 */
u16 swtcsrb; /* 0x08 */
};
/* LBSC */
struct r8a7790_lbsc {
u32 cs0ctrl;
u32 cs1ctrl;
u32 ecs0ctrl;
u32 ecs1ctrl;
u32 ecs2ctrl;
u32 ecs3ctrl;
u32 ecs4ctrl;
u32 ecs5ctrl;
u32 dummy0[4]; /* 0x20 .. 0x2C */
u32 cswcr0;
u32 cswcr1;
u32 ecswcr0;
u32 ecswcr1;
u32 ecswcr2;
u32 ecswcr3;
u32 ecswcr4;
u32 ecswcr5;
u32 exdmawcr0;
u32 exdmawcr1;
u32 exdmawcr2;
u32 dummy1[9]; /* 0x5C .. 0x7C */
u32 cspwcr0;
u32 cspwcr1;
u32 ecspwcr0;
u32 ecspwcr1;
u32 ecspwcr2;
u32 ecspwcr3;
u32 ecspwcr4;
u32 ecspwcr5;
u32 exwtsync;
u32 dummy2[3]; /* 0xA4 .. 0xAC */
u32 cs0bstctl;
u32 cs0btph;
u32 dummy3[2]; /* 0xB8 .. 0xBC */
u32 cs1gdst;
u32 ecs0gdst;
u32 ecs1gdst;
u32 ecs2gdst;
u32 ecs3gdst;
u32 ecs4gdst;
u32 ecs5gdst;
u32 dummy4[5]; /* 0xDC .. 0xEC */
u32 exdmaset0;
u32 exdmaset1;
u32 exdmaset2;
u32 dummy5[5]; /* 0xFC .. 0x10C */
u32 exdmcr0;
u32 exdmcr1;
u32 exdmcr2;
u32 dummy6[5]; /* 0x11C .. 0x12C */
u32 bcintsr;
u32 bcintcr;
u32 bcintmr;
u32 dummy7; /* 0x13C */
u32 exbatlv;
u32 exwtsts;
u32 dummy8[14]; /* 0x148 .. 0x17C */
u32 atacsctrl;
u32 dummy9[15]; /* 0x184 .. 0x1BC */
u32 exbct;
u32 extct;
};
/* DBSC3 */
struct r8a7790_dbsc3 {
u32 dummy0[3]; /* 0x00 .. 0x08 */
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2C */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3C */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4C */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xAC */
u32 dbbl;
u32 dummy5[3]; /* 0xB4 .. 0xBC */
u32 dbadj0;
u32 dummy6; /* 0xC4 */
u32 dbadj2;
u32 dummy7[5]; /* 0xCC .. 0xDC */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dummy8[2]; /* 0xEC .. 0xF0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy9; /* 0xFC */
u32 dbrnk0;
u32 dummy10[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy11[47]; /* 0x184 ..0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[14]; /* 0x248 .. 0x27C */
u32 dbpdlck;
u32 dummy13[3]; /* 0x284 .. 0x28C */
u32 dbpdrga;
u32 dummy14[3]; /* 0x294 .. 0x29C */
u32 dbpdrgd;
u32 dummy15[24]; /* 0x2A4 .. 0x300 */
u32 dbbs0cnt1;
u32 dummy16[30]; /* 0x308 .. 0x37C */
u32 dbwt0cnf0;
u32 dbwt0cnf1;
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
};
/* GPIO */
struct r8a7790_gpio {
u32 iointsel;
u32 inoutsel;
u32 outdt;
u32 indt;
u32 intdt;
u32 intclr;
u32 intmsk;
u32 posneg;
u32 edglevel;
u32 filonoff;
u32 intmsks;
u32 mskclrs;
u32 outdtsel;
u32 outdth;
u32 outdtl;
u32 bothedge;
};
/* S3C(QoS) */
struct r8a7790_s3c {
u32 s3cexcladdmsk;
u32 s3cexclidmsk;
u32 s3cadsplcr;
u32 s3cmaar;
u32 s3carcr11;
u32 s3crorr;
u32 s3cworr;
u32 s3carcr22;
u32 dummy1[2]; /* 0x20 .. 0x24 */
u32 s3cmctr;
u32 dummy2; /* 0x2C */
u32 cconf0;
u32 cconf1;
u32 cconf2;
u32 cconf3;
};
struct r8a7790_s3c_qos {
u32 s3cqos0;
u32 s3cqos1;
u32 s3cqos2;
u32 s3cqos3;
u32 s3cqos4;
u32 s3cqos5;
u32 s3cqos6;
u32 s3cqos7;
u32 s3cqos8;
};
/* DBSC(QoS) */
struct r8a7790_dbsc3_qos {
u32 dblgcnt;
u32 dbtmval0;
u32 dbtmval1;
u32 dbtmval2;
u32 dbtmval3;
u32 dbrqctr;
u32 dbthres0;
u32 dbthres1;
u32 dbthres2;
u32 dummy0; /* 0x24 */
u32 dblgqon;
};
/* MXI(QoS) */
struct r8a7790_mxi {
u32 mxsaar0;
u32 mxsaar1;
u32 dummy0[7]; /* 0x08 .. 0x20 */
u32 mxaxiracr;
u32 mxs3cracr;
u32 dummy1[2]; /* 0x2C .. 0x30 */
u32 mxaxiwacr;
u32 mxs3cwacr;
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
};
struct r8a7790_mxi_qos {
u32 vspdu0;
u32 vspdu1;
u32 du0;
u32 du1;
};
/* AXI(QoS) */
struct r8a7790_axi_qos {
u32 qosconf;
u32 qosctset0;
u32 qosctset1;
u32 qosctset2;
u32 qosctset3;
u32 qosreqctr;
u32 qosthres0;
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
};
#endif
#endif /* __ASM_ARCH_R8A7790_H */

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arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h Normal file
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#ifndef __ASM_R8A7791_H__
#define __ASM_R8A7791_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
*/
enum {
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
GPIO_GP_1_24, GPIO_GP_1_25,
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19,
GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23,
GPIO_GP_7_24, GPIO_GP_7_25,
GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA,
GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0,
GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2,
GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5,
GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7,
GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
/* IPSR0 */
GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10,
GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15,
GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B,
GPIO_FN_SCL0_C, GPIO_FN_PWM2_B,
GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B,
GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B,
GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK,
/* IPSR1 */
GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8,
GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0,
GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0,
GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D,
GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D,
GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D,
GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D,
GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN,
GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D,
GPIO_FN_A15, GPIO_FN_BPFCLK_C,
GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B,
GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C,
GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C,
/* IPSR2 */
GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C,
GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B,
GPIO_FN_A20, GPIO_FN_SPCLK,
GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0,
GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B,
GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD,
GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B,
GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD,
GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3,
GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD,
GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C,
GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD,
GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1,
GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1,
GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK,
GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC,
GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD,
GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1,
/* IPSR3 */
GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N,
GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2,
GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1,
GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B,
GPIO_FN_PWM1, GPIO_FN_TPU_TO1,
GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2,
GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B,
GPIO_FN_PWM2, GPIO_FN_TPU_TO2,
GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B,
GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D,
GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B,
GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B,
GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B,
GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B,
GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3,
GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON,
GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C,
GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B,
GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D,
GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C,
GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C,
GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C,
GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C,
/* IPSR4 */
GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B,
GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C,
GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B,
GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D,
GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B,
GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D,
GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B,
GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C,
GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B,
GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E,
GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B,
GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E,
GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B,
GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E,
GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3,
GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D,
GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D,
GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D,
GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C,
GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0,
GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B,
/* IPSR5 */
GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0,
GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B,
GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0,
GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B,
GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0,
GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B,
GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK,
GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B,
GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B,
GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B,
GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS,
GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON,
GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B,
GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B,
GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D,
GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D,
GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D,
/* IPSR6 */
GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B,
GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E,
GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B,
GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B,
GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD,
GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N,
GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N,
GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N,
GPIO_FN_IRQ3, GPIO_FN_SCL4_C,
GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N,
GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C,
GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N,
GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E,
GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B,
GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E,
GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B,
GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D,
GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B,
GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D,
/* IPSR7 */
GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D,
GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D,
GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B,
GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B,
GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B,
GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B,
GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B,
GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B,
GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B,
GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B,
GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B,
GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B,
GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B,
GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B,
GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B,
GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B,
GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B,
GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B,
/* IPSR8 */
GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11,
GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B,
GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B,
GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B,
GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B,
GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B,
GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B,
GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B,
GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B,
GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B,
GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B,
GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B,
GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B,
GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B,
GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B,
GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B,
GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B,
GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20,
GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX,
GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3,
GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX,
/* IPSR9 */
GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C,
GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD,
GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C,
GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK,
GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS,
GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK,
GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX,
GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4,
GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS,
GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE,
GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B,
GPIO_FN_DU1_DISP, GPIO_FN_QPOLA,
GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B,
GPIO_FN_VI0_CLKENB, GPIO_FN_TX4,
GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D,
GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D,
GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5,
GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D,
GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5,
GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D,
GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B,
GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4,
GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N,
/* IPSR10 */
GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4,
GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N,
GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C,
GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N,
GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C,
GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N,
GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C,
GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D,
GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C,
GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E,
GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D,
GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D,
GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D,
GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B,
GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N,
GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B,
GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N,
GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3,
GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C,
GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4,
GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C,
GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B,
GPIO_FN_TX0_C, GPIO_FN_SCL1_D,
/* IPSR11 */
GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B,
GPIO_FN_RX0_C, GPIO_FN_SDA1_D,
GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B,
GPIO_FN_TX1_C, GPIO_FN_SCL4_B,
GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E,
GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D,
GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B,
GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B,
GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B,
GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B,
GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B,
GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B,
GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5,
GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6,
GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7,
GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER,
GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO,
GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV,
GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC,
GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC,
GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C,
GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C,
/* IPSR12 */
GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7,
GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7,
GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C,
GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E,
GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C,
GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E,
GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B,
GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E,
GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B,
GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E,
GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3,
GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B,
GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C,
GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C,
GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C,
GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D,
GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C,
GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D,
GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C,
/* IPSR13 */
GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C,
GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C,
GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK,
GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C,
GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL,
GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C,
GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B,
GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C,
GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B,
GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B,
GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B,
GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B,
GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B,
GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F,
GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C,
GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F,
GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C,
GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B,
GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B,
GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B,
GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B,
GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C,
/* IPSR14 */
GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C,
GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD,
GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1,
GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3,
GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C,
GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C,
GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C,
GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C,
GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA,
GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B,
GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP,
GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B,
GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK,
GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B,
GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0,
GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B,
GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E,
GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B,
GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E,
GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B,
/* IPSR15 */
GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D,
GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C,
GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D,
GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B,
GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C,
GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5,
GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C,
GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6,
GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C,
GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C,
GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C,
GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N,
GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C,
GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK,
GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C,
GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C,
GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C,
GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C,
GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C,
/* IPSR16 */
GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B,
GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C,
GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B,
GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C,
GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C,
GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N,
GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B,
GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N,
GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
};
#endif /* __ASM_R8A7791_H__ */

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arch/arm/include/asm/arch-rmobile/r8a7791.h Normal file
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/*
* arch/arm/include/asm/arch-rmobile/r8a7791.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7791_H
#define __ASM_ARCH_R8A7791_H
/*
* R8A7791 I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xFEC00200
#define DBSC3_0_BASE 0xE6790000
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define S3C_QOS_DCACHE_BASE 0xE6784BDC
#define S3C_QOS_CCI0_BASE 0xE6784C00
#define S3C_QOS_CCI1_BASE 0xE6784C24
#define S3C_QOS_MXI_BASE 0xE6784C48
#define S3C_QOS_AXI_BASE 0xE6784C6C
#define DBSC3_0_QOS_R0_BASE 0xE6791000
#define DBSC3_0_QOS_R1_BASE 0xE6791100
#define DBSC3_0_QOS_R2_BASE 0xE6791200
#define DBSC3_0_QOS_R3_BASE 0xE6791300
#define DBSC3_0_QOS_R4_BASE 0xE6791400
#define DBSC3_0_QOS_R5_BASE 0xE6791500
#define DBSC3_0_QOS_R6_BASE 0xE6791600
#define DBSC3_0_QOS_R7_BASE 0xE6791700
#define DBSC3_0_QOS_R8_BASE 0xE6791800
#define DBSC3_0_QOS_R9_BASE 0xE6791900
#define DBSC3_0_QOS_R10_BASE 0xE6791A00
#define DBSC3_0_QOS_R11_BASE 0xE6791B00
#define DBSC3_0_QOS_R12_BASE 0xE6791C00
#define DBSC3_0_QOS_R13_BASE 0xE6791D00
#define DBSC3_0_QOS_R14_BASE 0xE6791E00
#define DBSC3_0_QOS_R15_BASE 0xE6791F00
#define DBSC3_0_QOS_W0_BASE 0xE6792000
#define DBSC3_0_QOS_W1_BASE 0xE6792100
#define DBSC3_0_QOS_W2_BASE 0xE6792200
#define DBSC3_0_QOS_W3_BASE 0xE6792300
#define DBSC3_0_QOS_W4_BASE 0xE6792400
#define DBSC3_0_QOS_W5_BASE 0xE6792500
#define DBSC3_0_QOS_W6_BASE 0xE6792600
#define DBSC3_0_QOS_W7_BASE 0xE6792700
#define DBSC3_0_QOS_W8_BASE 0xE6792800
#define DBSC3_0_QOS_W9_BASE 0xE6792900
#define DBSC3_0_QOS_W10_BASE 0xE6792A00
#define DBSC3_0_QOS_W11_BASE 0xE6792B00
#define DBSC3_0_QOS_W12_BASE 0xE6792C00
#define DBSC3_0_QOS_W13_BASE 0xE6792D00
#define DBSC3_0_QOS_W14_BASE 0xE6792E00
#define DBSC3_0_QOS_W15_BASE 0xE6792F00
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
#define DBSC3_1_QOS_R3_BASE 0xE67A1300
#define DBSC3_1_QOS_R4_BASE 0xE67A1400
#define DBSC3_1_QOS_R5_BASE 0xE67A1500
#define DBSC3_1_QOS_R6_BASE 0xE67A1600
#define DBSC3_1_QOS_R7_BASE 0xE67A1700
#define DBSC3_1_QOS_R8_BASE 0xE67A1800
#define DBSC3_1_QOS_R9_BASE 0xE67A1900
#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
#define DBSC3_1_QOS_W0_BASE 0xE67A2000
#define DBSC3_1_QOS_W1_BASE 0xE67A2100
#define DBSC3_1_QOS_W2_BASE 0xE67A2200
#define DBSC3_1_QOS_W3_BASE 0xE67A2300
#define DBSC3_1_QOS_W4_BASE 0xE67A2400
#define DBSC3_1_QOS_W5_BASE 0xE67A2500
#define DBSC3_1_QOS_W6_BASE 0xE67A2600
#define DBSC3_1_QOS_W7_BASE 0xE67A2700
#define DBSC3_1_QOS_W8_BASE 0xE67A2800
#define DBSC3_1_QOS_W9_BASE 0xE67A2900
#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
#define DBSC3_0_DBADJ2 0xE67900C8
#define CCI_400_MAXOT_1 0xF0091110
#define CCI_400_MAXOT_2 0xF0092110
#define CCI_400_QOSCNTL_1 0xF009110C
#define CCI_400_QOSCNTL_2 0xF009210C
#define MXI_BASE 0xFE960000
#define MXI_QOS_BASE 0xFE960300
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
#define SYS_AXI_IMUX0_BASE 0xFF800600
#define SYS_AXI_IMUX1_BASE 0xFF800640
#define SYS_AXI_IMUX2_BASE 0xFF800680
#define SYS_AXI_LBS_BASE 0xFF8006C0
#define SYS_AXI_MMUDS_BASE 0xFF800700
#define SYS_AXI_MMUM_BASE 0xFF800740
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define SYS_AXI_AX2M_BASE 0xFF800380
#define SYS_AXI_CC50_BASE 0xFF8003C0
#define SYS_AXI_CCI_BASE 0xFF800440
#define SYS_AXI_CS_BASE 0xFF800480
#define SYS_AXI_DDM_BASE 0xFF8004C0
#define SYS_AXI_ETH_BASE 0xFF800500
#define SYS_AXI_MPXM_BASE 0xFF800840
#define SYS_AXI_SAT0_BASE 0xFF800980
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
#define SYS_AXI_TRAB_BASE 0xFF800B00
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_DBG_BASE 0xFF810140
#define RT_AXI_RDM_BASE 0xFF810180
#define RT_AXI_RDS_BASE 0xFF8101C0
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define RT_AXI_SY2RT_BASE 0xFF810280
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
#define MP_AXI_ASDS1_BASE 0xFF820200
#define MP_AXI_MLP_BASE 0xFF820240
#define MP_AXI_MMUMP_BASE 0xFF820280
#define MP_AXI_SPU_BASE 0xFF8202C0
#define MP_AXI_SPUC_BASE 0xFF820300
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
#define CCI_AXI_MMUR_BASE 0xFF880180
#define CCI_AXI_MMUDS_BASE 0xFF8801C0
#define CCI_AXI_MMUM_BASE 0xFF880200
#define CCI_AXI_MXI_BASE 0xFF880240
#define CCI_AXI_MMUS1_BASE 0xFF880280
#define CCI_AXI_MMUMP_BASE 0xFF8802C0
#define MEDIA_AXI_MXR_BASE 0xFE960080
#define MEDIA_AXI_MXW_BASE 0xFE9600C0
#define MEDIA_AXI_JPR_BASE 0xFE964100
#define MEDIA_AXI_JPW_BASE 0xFE966100
#define MEDIA_AXI_GCU0R_BASE 0xFE964140
#define MEDIA_AXI_GCU0W_BASE 0xFE966140
#define MEDIA_AXI_GCU1R_BASE 0xFE964180
#define MEDIA_AXI_GCU1W_BASE 0xFE966180
#define MEDIA_AXI_TDMR_BASE 0xFE964500
#define MEDIA_AXI_TDMW_BASE 0xFE966500
#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
#define MEDIA_AXI_IMSW_BASE 0xFE966D80
#define MEDIA_AXI_VSP1R_BASE 0xFE965100
#define MEDIA_AXI_VSP1W_BASE 0xFE967100
#define MEDIA_AXI_FDP1R_BASE 0xFE965140
#define MEDIA_AXI_FDP1W_BASE 0xFE967140
#define MEDIA_AXI_IMRR_BASE 0xFE965180
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
#define MEDIA_AXI_VPC0R_BASE 0xFE965980
#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
#define SYS_AXI_CSDMSCR 0xFF802014
#define SYS_AXI_DDMDMSCR 0xFF802018
#define SYS_AXI_ETHDMSCR 0xFF80201C
#define SYS_AXI_G2DDMSCR 0xFF802020
#define SYS_AXI_IMP0DMSCR 0xFF802024
#define SYS_AXI_IMP1DMSCR 0xFF802028
#define SYS_AXI_LBSDMSCR 0xFF80202C
#define SYS_AXI_MMUDSDMSCR 0xFF802030
#define SYS_AXI_MMUMXDMSCR 0xFF802034
#define SYS_AXI_MMURDDMSCR 0xFF802038
#define SYS_AXI_MMUS0DMSCR 0xFF80203C
#define SYS_AXI_MMUS1DMSCR 0xFF802040
#define SYS_AXI_MPXDMSCR 0xFF802044
#define SYS_AXI_MTSB0DMSCR 0xFF802048
#define SYS_AXI_MTSB1DMSCR 0xFF80204C
#define SYS_AXI_PCIDMSCR 0xFF802050
#define SYS_AXI_RTXDMSCR 0xFF802054
#define SYS_AXI_SAT0DMSCR 0xFF802058
#define SYS_AXI_SAT1DMSCR 0xFF80205C
#define SYS_AXI_SDM0DMSCR 0xFF802060
#define SYS_AXI_SDM1DMSCR 0xFF802064
#define SYS_AXI_SDS0DMSCR 0xFF802068
#define SYS_AXI_SDS1DMSCR 0xFF80206C
#define SYS_AXI_ETRABDMSCR 0xFF802070
#define SYS_AXI_ETRKFDMSCR 0xFF802074
#define SYS_AXI_UDM0DMSCR 0xFF802078
#define SYS_AXI_UDM1DMSCR 0xFF80207C
#define SYS_AXI_USB20DMSCR 0xFF802080
#define SYS_AXI_USB21DMSCR 0xFF802084
#define SYS_AXI_USB22DMSCR 0xFF802088
#define SYS_AXI_USB30DMSCR 0xFF80208C
#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
#define SYS_AXI_LBSSLVDMSCR 0xFF802128
#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
#define SYS_AXI_MPXSLVDMSCR 0xFF802134
#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
#define SYS_AXI_MXTSLVDMSCR 0xFF802140
#define SYS_AXI_PCISLVDMSCR 0xFF802144
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
#define RT_AXI_RDMDMSCR 0xFF812008
#define RT_AXI_RDSDMSCR 0xFF81200C
#define RT_AXI_STRDMSCR 0xFF812010
#define RT_AXI_SY2RTDMSCR 0xFF812014
#define RT_AXI_CBSSLVDMSCR 0xFF812100
#define RT_AXI_DBSSLVDMSCR 0xFF812104
#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
#define MP_AXI_ADSPDMSCR 0xFF822000
#define MP_AXI_ASDM0DMSCR 0xFF822004
#define MP_AXI_ASDM1DMSCR 0xFF822008
#define MP_AXI_ASDS0DMSCR 0xFF82200C
#define MP_AXI_ASDS1DMSCR 0xFF822010
#define MP_AXI_MLPDMSCR 0xFF822014
#define MP_AXI_MMUMPDMSCR 0xFF822018
#define MP_AXI_SPUDMSCR 0xFF82201C
#define MP_AXI_SPUCDMSCR 0xFF822020
#define MP_AXI_SY2MPDMSCR 0xFF822024
#define MP_AXI_ADSPSLVDMSCR 0xFF822100
#define MP_AXI_MLMSLVDMSCR 0xFF822104
#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
#define MP_AXI_SPUSLVDMSCR 0xFF822128
#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
#define ADM_AXI_ASDM0DMSCR 0xFF842000
#define ADM_AXI_ASDM1DMSCR 0xFF842004
#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
#define DM_AXI_RAP5SLVDMSCR 0xFF852110
#define DM_AXI_SAP4SLVDMSCR 0xFF852114
#define DM_AXI_SAP5SLVDMSCR 0xFF852118
#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
#define DM_AXI_SAP65SLVDMSCR 0xFF852120
#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
#define SYS_AXI256_MXIDMSCR 0xFF862008
#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
#define MXT_FDPSLVDMSCR 0xFF87210C
#define MXT_IMRSLVDMSCR 0xFF872110
#define MXT_VINSLVDMSCR 0xFF872114
#define MXT_VPC0SLVDMSCR 0xFF872118
#define MXT_VPC1SLVDMSCR 0xFF87211C
#define MXT_VSP0SLVDMSCR 0xFF872120
#define MXT_VSP1SLVDMSCR 0xFF872124
#define MXT_VSPD0SLVDMSCR 0xFF872128
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
#define CCI_AXI_MMURDMSCR 0xFF882008
#define CCI_AXI_MMUDSDMSCR 0xFF88200C
#define CCI_AXI_MMUMDMSCR 0xFF882010
#define CCI_AXI_MXIDMSCR 0xFF882014
#define CCI_AXI_MMUS1DMSCR 0xFF882018
#define CCI_AXI_MMUMPDMSCR 0xFF88201C
#define CCI_AXI_DVMDMSCR 0xFF882020
#define CCI_AXI_CCISLVDMSCR 0xFF882100
#define CCI_AXI_IPMMUIDVMCR 0xFF880400
#define CCI_AXI_IPMMURDVMCR 0xFF880404
#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
#define CCI_AXI_AX2ADDRMASK 0xFF88041C
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct r8a7791_rwdt {
u32 rwtcnt; /* 0x00 */
u32 rwtcsra; /* 0x04 */
u16 rwtcsrb; /* 0x08 */
};
/* SWDT */
struct r8a7791_swdt {
u32 swtcnt; /* 0x00 */
u32 swtcsra; /* 0x04 */
u16 swtcsrb; /* 0x08 */
};
/* LBSC */
struct r8a7791_lbsc {
u32 cs0ctrl;
u32 cs1ctrl;
u32 ecs0ctrl;
u32 ecs1ctrl;
u32 ecs2ctrl;
u32 ecs3ctrl;
u32 ecs4ctrl;
u32 ecs5ctrl;
u32 dummy0[4]; /* 0x20 .. 0x2C */
u32 cswcr0;
u32 cswcr1;
u32 ecswcr0;
u32 ecswcr1;
u32 ecswcr2;
u32 ecswcr3;
u32 ecswcr4;
u32 ecswcr5;
u32 exdmawcr0;
u32 exdmawcr1;
u32 exdmawcr2;
u32 dummy1[9]; /* 0x5C .. 0x7C */
u32 cspwcr0;
u32 cspwcr1;
u32 ecspwcr0;
u32 ecspwcr1;
u32 ecspwcr2;
u32 ecspwcr3;
u32 ecspwcr4;
u32 ecspwcr5;
u32 exwtsync;
u32 dummy2[3]; /* 0xA4 .. 0xAC */
u32 cs0bstctl;
u32 cs0btph;
u32 dummy3[2]; /* 0xB8 .. 0xBC */
u32 cs1gdst;
u32 ecs0gdst;
u32 ecs1gdst;
u32 ecs2gdst;
u32 ecs3gdst;
u32 ecs4gdst;
u32 ecs5gdst;
u32 dummy4[5]; /* 0xDC .. 0xEC */
u32 exdmaset0;
u32 exdmaset1;
u32 exdmaset2;
u32 dummy5[5]; /* 0xFC .. 0x10C */
u32 exdmcr0;
u32 exdmcr1;
u32 exdmcr2;
u32 dummy6[5]; /* 0x11C .. 0x12C */
u32 bcintsr;
u32 bcintcr;
u32 bcintmr;
u32 dummy7; /* 0x13C */
u32 exbatlv;
u32 exwtsts;
u32 dummy8[14]; /* 0x148 .. 0x17C */
u32 atacsctrl;
u32 dummy9[15]; /* 0x184 .. 0x1BC */
u32 exbct;
u32 extct;
};
/* DBSC3 */
struct r8a7791_dbsc3 {
u32 dummy0[3]; /* 0x00 .. 0x08 */
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2C */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3C */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4C */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xAC */
u32 dbbl;
u32 dummy5[3]; /* 0xB4 .. 0xBC */
u32 dbadj0;
u32 dummy6; /* 0xC4 */
u32 dbadj2;
u32 dummy7[5]; /* 0xCC .. 0xDC */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dummy8[2]; /* 0xEC .. 0xF0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy9; /* 0xFC */
u32 dbrnk0;
u32 dummy10[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy11[47]; /* 0x184 ..0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[14]; /* 0x248 .. 0x27C */
u32 dbpdlck;
u32 dummy13[3]; /* 0x284 .. 0x28C */
u32 dbpdrga;
u32 dummy14[3]; /* 0x294 .. 0x29C */
u32 dbpdrgd;
u32 dummy15[24]; /* 0x2A4 .. 0x300 */
u32 dbbs0cnt1;
u32 dummy16[30]; /* 0x308 .. 0x37C */
u32 dbwt0cnf0;
u32 dbwt0cnf1;
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
};
/* GPIO */
struct r8a7791_gpio {
u32 iointsel;
u32 inoutsel;
u32 outdt;
u32 indt;
u32 intdt;
u32 intclr;
u32 intmsk;
u32 posneg;
u32 edglevel;
u32 filonoff;
u32 intmsks;
u32 mskclrs;
u32 outdtsel;
u32 outdth;
u32 outdtl;
u32 bothedge;
};
/* S3C(QoS) */
struct r8a7791_s3c {
u32 s3cexcladdmsk;
u32 s3cexclidmsk;
u32 s3cadsplcr;
u32 s3cmaar;
u32 dummy0; /* 0x10 */
u32 s3crorr;
u32 s3cworr;
u32 s3carcr22;
u32 dummy1[2]; /* 0x20 .. 0x24 */
u32 s3cmctr;
u32 dummy2; /* 0x2C */
u32 cconf0;
u32 cconf1;
u32 cconf2;
u32 cconf3;
};
struct r8a7791_s3c_qos {
u32 s3cqos0;
u32 s3cqos1;
u32 s3cqos2;
u32 s3cqos3;
u32 s3cqos4;
u32 s3cqos5;
u32 s3cqos6;
u32 s3cqos7;
u32 s3cqos8;
};
/* DBSC(QoS) */
struct r8a7791_dbsc3_qos {
u32 dblgcnt;
u32 dbtmval0;
u32 dbtmval1;
u32 dbtmval2;
u32 dbtmval3;
u32 dbrqctr;
u32 dbthres0;
u32 dbthres1;
u32 dbthres2;
u32 dummy0; /* 0x24 */
u32 dblgqon;
};
/* MXI(QoS) */
struct r8a7791_mxi {
u32 mxsaar0;
u32 mxsaar1;
u32 dummy0[8]; /* 0x08 .. 0x24 */
u32 mxs3cracr;
u32 dummy1[3]; /* 0x2C .. 0x34 */
u32 mxs3cwacr;
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
};
struct r8a7791_mxi_qos {
u32 vspdu0;
u32 vspdu1;
u32 du0;
u32 du1;
};
/* AXI(QoS) */
struct r8a7791_axi_qos {
u32 qosconf;
u32 qosctset0;
u32 qosctset1;
u32 qosctset2;
u32 qosctset3;
u32 qosreqctr;
u32 qosthres0;
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
};
#endif
#endif /* __ASM_ARCH_R8A7791_H */

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arch/arm/include/asm/arch-rmobile/rmobile.h
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@ -6,6 +6,10 @@
#include <asm/arch/sh73a0.h>
#elif defined(CONFIG_R8A7740)
#include <asm/arch/r8a7740.h>
#elif defined(CONFIG_R8A7790)
#include <asm/arch/r8a7790.h>
#elif defined(CONFIG_R8A7791)
#include <asm/arch/r8a7791.h>
#else
#error "SOC Name not defined"
#endif

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#
# board/renesas/koelsch/Makefile
#
# Copyright (C) 2013 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
obj-y := koelsch.o qos.o

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/*
* board/renesas/koelsch/koelsch.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*
*/
#include <common.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <i2c.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
#define s_init_wait(cnt) \
({ \
u32 i = 0x10000 * cnt; \
while (i > 0) \
i--; \
})
#define dbpdrgd_check(bsc) \
({ \
while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
; \
})
#if defined(CONFIG_NORFLASH)
static void bsc_init(void)
{
struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
/* LBSC */
writel(0x00000020, &lbsc->cs0ctrl);
writel(0x00000020, &lbsc->cs1ctrl);
writel(0x00002020, &lbsc->ecs0ctrl);
writel(0x00002020, &lbsc->ecs1ctrl);
writel(0x077F077F, &lbsc->cswcr0);
writel(0x077F077F, &lbsc->cswcr1);
writel(0x077F077F, &lbsc->ecswcr0);
writel(0x077F077F, &lbsc->ecswcr1);
/* DBSC3 */
s_init_wait(10);
writel(0x0000A55A, &dbsc3_0->dbpdlck);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x80000000, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000006, &dbsc3_0->dbpdrga);
writel(0x0001C000, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FD2480, &dbsc3_0->dbpdrgd);
writel(0x00000010, &dbsc3_0->dbpdrga);
writel(0xF004649B, &dbsc3_0->dbpdrgd);
writel(0x0000000F, &dbsc3_0->dbpdrga);
writel(0x00181EE4, &dbsc3_0->dbpdrgd);
writel(0x0000000E, &dbsc3_0->dbpdrga);
writel(0x33C03812, &dbsc3_0->dbpdrgd);
writel(0x00000003, &dbsc3_0->dbpdrga);
writel(0x0300C481, &dbsc3_0->dbpdrgd);
writel(0x00000007, &dbsc3_0->dbkind);
writel(0x10030A02, &dbsc3_0->dbconf0);
writel(0x00000001, &dbsc3_0->dbphytype);
writel(0x00000000, &dbsc3_0->dbbl);
writel(0x0000000B, &dbsc3_0->dbtr0);
writel(0x00000008, &dbsc3_0->dbtr1);
writel(0x00000000, &dbsc3_0->dbtr2);
writel(0x0000000B, &dbsc3_0->dbtr3);
writel(0x000C000B, &dbsc3_0->dbtr4);
writel(0x00000027, &dbsc3_0->dbtr5);
writel(0x0000001C, &dbsc3_0->dbtr6);
writel(0x00000005, &dbsc3_0->dbtr7);
writel(0x00000018, &dbsc3_0->dbtr8);
writel(0x00000008, &dbsc3_0->dbtr9);
writel(0x0000000C, &dbsc3_0->dbtr10);
writel(0x00000009, &dbsc3_0->dbtr11);
writel(0x00000012, &dbsc3_0->dbtr12);
writel(0x000000D0, &dbsc3_0->dbtr13);
writel(0x00140005, &dbsc3_0->dbtr14);
writel(0x00050004, &dbsc3_0->dbtr15);
writel(0x70233005, &dbsc3_0->dbtr16);
writel(0x000C0000, &dbsc3_0->dbtr17);
writel(0x00000300, &dbsc3_0->dbtr18);
writel(0x00000040, &dbsc3_0->dbtr19);
writel(0x00000001, &dbsc3_0->dbrnk0);
writel(0x00020001, &dbsc3_0->dbadj0);
writel(0x20082008, &dbsc3_0->dbadj2);
writel(0x00020002, &dbsc3_0->dbwt0cnf0);
writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
writel(0x00000015, &dbsc3_0->dbpdrga);
writel(0x00000D70, &dbsc3_0->dbpdrgd);
writel(0x00000016, &dbsc3_0->dbpdrga);
writel(0x00000006, &dbsc3_0->dbpdrgd);
writel(0x00000017, &dbsc3_0->dbpdrga);
writel(0x00000018, &dbsc3_0->dbpdrgd);
writel(0x00000012, &dbsc3_0->dbpdrga);
writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
writel(0x00000013, &dbsc3_0->dbpdrga);
writel(0x1A868300, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
writel(0x00000014, &dbsc3_0->dbpdrga);
writel(0x300214D8, &dbsc3_0->dbpdrgd);
writel(0x0000001A, &dbsc3_0->dbpdrga);
writel(0x930035C7, &dbsc3_0->dbpdrgd);
writel(0x00000060, &dbsc3_0->dbpdrga);
writel(0x330657B2, &dbsc3_0->dbpdrgd);
writel(0x00000011, &dbsc3_0->dbpdrga);
writel(0x1000040B, &dbsc3_0->dbpdrgd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000071, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x2100FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x110000DB, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000181, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x0000FE01, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000000, &dbsc3_0->dbbs0cnt1);
writel(0x01004C20, &dbsc3_0->dbcalcnf);
writel(0x014000AA, &dbsc3_0->dbcaltr);
writel(0x00000140, &dbsc3_0->dbrfcnf0);
writel(0x00081860, &dbsc3_0->dbrfcnf1);
writel(0x00010000, &dbsc3_0->dbrfcnf2);
writel(0x00000001, &dbsc3_0->dbrfen);
writel(0x00000001, &dbsc3_0->dbacen);
}
#else
#define bsc_init() do {} while (0)
#endif /* CONFIG_NORFLASH */
void s_init(void)
{
struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* QoS */
qos_init();
/* BSC */
bsc_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
#define set_guard_reg(addr, mask, value) \
{ \
u32 val; \
val = (readl(addr) & ~(mask)) | (value); \
writel(~val, PMMR); \
writel(val, addr); \
}
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
out_##type((saddr), in_##type(addr) & ~(clear))
#define mstp_setbits_le32(addr, saddr, set) \
mstp_setbits(le32, addr, saddr, set)
#define mstp_clrbits_le32(addr, saddr, clear) \
mstp_clrbits(le32, addr, saddr, clear)
int board_early_init_f(void)
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
#if defined(CONFIG_NORFLASH)
/* SCIF0 */
set_guard_reg(GPSR4, 0x34000000, 0x00000000);
set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
set_guard_reg(GPSR4, 0x00000000, 0x34000000);
#endif
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
/* Init PFC controller */
r8a7791_pinmux_init();
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
};
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
}
int board_late_init(void)
{
return 0;
}
void reset_cpu(ulong addr)
{
}

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board/renesas/koelsch/qos.c Normal file
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board/renesas/koelsch/qos.h Normal file
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/*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __QOS_H__
#define __QOS_H__
void qos_init(void);
#endif

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board/renesas/lager/Makefile Normal file
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#
# board/renesas/lager/Makefile
#
# Copyright (C) 2013 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
obj-y := lager.o qos.o

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board/renesas/lager/lager.c Normal file
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/*
* board/renesas/lager/lager.c
* This file is lager board support.
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
#define s_init_wait(cnt) \
({ \
u32 i = 0x10000 * cnt; \
while (i > 0) \
i--; \
})
#define dbpdrgd_check(bsc) \
({ \
while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
; \
})
#if defined(CONFIG_NORFLASH)
static void bsc_init(void)
{
struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
/* LBSC */
writel(0x00000020, &lbsc->cs0ctrl);
writel(0x00000020, &lbsc->cs1ctrl);
writel(0x00002020, &lbsc->ecs0ctrl);
writel(0x00002020, &lbsc->ecs1ctrl);
writel(0x077F077F, &lbsc->cswcr0);
writel(0x077F077F, &lbsc->cswcr1);
writel(0x077F077F, &lbsc->ecswcr0);
writel(0x077F077F, &lbsc->ecswcr1);
/* DBSC3 */
s_init_wait(10);
writel(0x0000A55A, &dbsc3_0->dbpdlck);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x80000000, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000006, &dbsc3_0->dbpdrga);
writel(0x0001C000, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FD2480, &dbsc3_0->dbpdrgd);
writel(0x00000010, &dbsc3_0->dbpdrga);
writel(0xF004649B, &dbsc3_0->dbpdrgd);
writel(0x0000000F, &dbsc3_0->dbpdrga);
writel(0x00181EE4, &dbsc3_0->dbpdrgd);
writel(0x0000000E, &dbsc3_0->dbpdrga);
writel(0x33C03812, &dbsc3_0->dbpdrgd);
writel(0x00000003, &dbsc3_0->dbpdrga);
writel(0x0300C481, &dbsc3_0->dbpdrgd);
writel(0x00000007, &dbsc3_0->dbkind);
writel(0x10030A02, &dbsc3_0->dbconf0);
writel(0x00000001, &dbsc3_0->dbphytype);
writel(0x00000000, &dbsc3_0->dbbl);
writel(0x0000000B, &dbsc3_0->dbtr0);
writel(0x00000008, &dbsc3_0->dbtr1);
writel(0x00000000, &dbsc3_0->dbtr2);
writel(0x0000000B, &dbsc3_0->dbtr3);
writel(0x000C000B, &dbsc3_0->dbtr4);
writel(0x00000027, &dbsc3_0->dbtr5);
writel(0x0000001C, &dbsc3_0->dbtr6);
writel(0x00000005, &dbsc3_0->dbtr7);
writel(0x00000018, &dbsc3_0->dbtr8);
writel(0x00000008, &dbsc3_0->dbtr9);
writel(0x0000000C, &dbsc3_0->dbtr10);
writel(0x00000009, &dbsc3_0->dbtr11);
writel(0x00000012, &dbsc3_0->dbtr12);
writel(0x000000D0, &dbsc3_0->dbtr13);
writel(0x00140005, &dbsc3_0->dbtr14);
writel(0x00050004, &dbsc3_0->dbtr15);
writel(0x70233005, &dbsc3_0->dbtr16);
writel(0x000C0000, &dbsc3_0->dbtr17);
writel(0x00000300, &dbsc3_0->dbtr18);
writel(0x00000040, &dbsc3_0->dbtr19);
writel(0x00000001, &dbsc3_0->dbrnk0);
writel(0x00020001, &dbsc3_0->dbadj0);
writel(0x20082008, &dbsc3_0->dbadj2);
writel(0x00020002, &dbsc3_0->dbwt0cnf0);
writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
writel(0x00000015, &dbsc3_0->dbpdrga);
writel(0x00000D70, &dbsc3_0->dbpdrgd);
writel(0x00000016, &dbsc3_0->dbpdrga);
writel(0x00000006, &dbsc3_0->dbpdrgd);
writel(0x00000017, &dbsc3_0->dbpdrga);
writel(0x00000018, &dbsc3_0->dbpdrgd);
writel(0x00000012, &dbsc3_0->dbpdrga);
writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
writel(0x00000013, &dbsc3_0->dbpdrga);
writel(0x1A868300, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
writel(0x00000014, &dbsc3_0->dbpdrga);
writel(0x300214D8, &dbsc3_0->dbpdrgd);
writel(0x0000001A, &dbsc3_0->dbpdrga);
writel(0x930035C7, &dbsc3_0->dbpdrgd);
writel(0x00000060, &dbsc3_0->dbpdrga);
writel(0x330657B2, &dbsc3_0->dbpdrgd);
writel(0x00000011, &dbsc3_0->dbpdrga);
writel(0x1000040B, &dbsc3_0->dbpdrgd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000071, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x2100FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x110000DB, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000181, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x0000FE01, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000000, &dbsc3_0->dbbs0cnt1);
writel(0x01004C20, &dbsc3_0->dbcalcnf);
writel(0x014000AA, &dbsc3_0->dbcaltr);
writel(0x00000140, &dbsc3_0->dbrfcnf0);
writel(0x00081860, &dbsc3_0->dbrfcnf1);
writel(0x00010000, &dbsc3_0->dbrfcnf2);
writel(0x00000001, &dbsc3_0->dbrfen);
writel(0x00000001, &dbsc3_0->dbacen);
}
#else
#define bsc_init() do {} while (0)
#endif /* CONFIG_NORFLASH */
void s_init(void)
{
struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* QoS(Quality-of-Service) Init */
qos_init();
/* BSC init */
bsc_init();
}
#define MSTPSR1 0xE6150038
#define SMSTPCR1 0xE6150134
#define TMU0_MSTP125 (1 << 25)
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
#define SCIF0_MSTP721 (1 << 21)
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
#define set_guard_reg(addr, mask, value) \
{ \
u32 val; \
val = (readl(addr) & ~(mask)) | (value); \
writel(~val, PMMR); \
writel(val, addr); \
}
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
out_##type((saddr), in_##type(addr) & ~(clear))
#define mstp_setbits_le32(addr, saddr, set) \
mstp_setbits(le32, addr, saddr, set)
#define mstp_clrbits_le32(addr, saddr, clear) \
mstp_clrbits(le32, addr, saddr, clear)
int board_early_init_f(void)
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
#if defined(CONFIG_NORFLASH)
/* SCIF0 */
set_guard_reg(GPSR4, 0x34000000, 0x00000000);
set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
set_guard_reg(GPSR4, 0x00000000, 0x34000000);
#endif
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_LAGER;
/* adress of boot parameters */
gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
/* Init PFC controller */
r8a7790_pinmux_init();
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
const struct rmobile_sysinfo sysinfo = {
CONFIG_RMOBILE_BOARD_STRING
};
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE;
gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE;
}
int board_late_init(void)
{
return 0;
}
void reset_cpu(ulong addr)
{
}

1119
board/renesas/lager/qos.c Normal file
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File diff suppressed because it is too large Load diff

12
board/renesas/lager/qos.h Normal file
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@ -0,0 +1,12 @@
/*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __QOS_H__
#define __QOS_H__
void qos_init(void);
#endif

4
boards.cfg
View file

@ -338,6 +338,10 @@ Active arm armv7 omap5 ti dra7xx
Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -

133
include/configs/koelsch.h Normal file
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@ -0,0 +1,133 @@
/*
* include/configs/koelsch.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __KOELSCH_H
#define __KOELSCH_H
#undef DEBUG
#define CONFIG_ARMV7
#define CONFIG_R8A7791
#define CONFIG_RMOBILE
#define CONFIG_RMOBILE_BOARD_STRING "Koelsch"
#define CONFIG_SH_GPIO_PFC
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_EDITENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_RUN
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_FLASH
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_OF_LIBFDT
#define BOARD_LATE_INIT
#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS ""
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_TMU_TIMER
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffc
#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
#define KOELSCH_SDRAM_BASE 0x40000000
#define KOELSCH_SDRAM_SIZE (2048u * 1024 * 1024)
#define KOELSCH_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE 512
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF0
#define SCIF0_BASE 0xe6e60000
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (KOELSCH_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
504 * 1024 * 1024)
#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_SDRAM_BASE (KOELSCH_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (KOELSCH_UBOOT_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 10000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ 14745600
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#endif /* __KOELSCH_H */

141
include/configs/lager.h Normal file
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@ -0,0 +1,141 @@
/*
* include/configs/lager.h
* This file is lager board configuration.
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __LAGER_H
#define __LAGER_H
#undef DEBUG
#define CONFIG_ARMV7
#define CONFIG_R8A7790
#define CONFIG_RMOBILE
#define CONFIG_RMOBILE_BOARD_STRING "Lager"
#define CONFIG_SH_GPIO_PFC
#define MACH_TYPE_LAGER 4538
#define CONFIG_MACH_TYPE MACH_TYPE_LAGER
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_EDITENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_RUN
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_FLASH
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_OF_LIBFDT
/* #define CONFIG_OF_LIBFDT */
#define BOARD_LATE_INIT
#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS ""
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_TMU_TIMER
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc
#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
#define LAGER_SDRAM_BASE 0x40000000
#define LAGER_SDRAM_SIZE (2048u * 1024 * 1024)
#define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE 512
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF0
#define SCIF0_BASE 0xe6e60000
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
504 * 1024 * 1024)
#undef CONFIG_SYS_ALT_MEMTEST
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* USE NOR FLASH */
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
/* Board Clock */
#define CONFIG_BASE_CLK_FREQ 20000000u
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#endif /* __LAGER_H */