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Tegra114: Do not program CPCON field for PLLX

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PLLX no longer has the CPCON field on Tegra114, so do not attempt to
program it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Thierry Reding 2013-10-01 17:04:45 +02:00 committed by Tom Warren
parent 44de8e22ec
commit 4475c7752d
1 changed files with 5 additions and 1 deletions
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6
arch/arm/cpu/arm720t/tegra-common/cpu.c
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@ -135,6 +135,7 @@ void adjust_pllp_out_freqs(void)
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
int chip = tegra_get_chip();
u32 reg;
/* If PLLX is already enabled, just return */
@ -151,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
reg = (cpcon << PLL_CPCON_SHIFT);
if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
reg = (cpcon << PLL_CPCON_SHIFT);
else
reg = 0;
/* Set dccon to PLLX_MISC if freq > 600MHz */
if (divn > 600)