Many SPL linker scripts needlessly include linker lists (aka LGAs).
Remove them whenever possible; keep it only in the seven am335x_evm
variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot),
where there is actual content in output section .u_boot_list.
This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets
byte-identical.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Output section .u_boot_list was left unmapped in
u-boot-spl.lds for omap-common, causing the location
counter to roll back to bteween .rodata and .data,
making __image_copy_end and _end symbols wrong.
Mapping output section .u_boot_list to memory .sram
fixes these symbols' mapping.
This modifies the SPL binary but has no functional
impact, as __image_copy_end and _end are never used
in SPLs and u_boot_list is empty for all 29 boards
affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3
omap3_beagle am3517_crane igep0032 mt_ventoux pcm051
am3517_evm omap3_evm_quick_mmc am335x_evm_uart2
am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand
omap3_overo igep0020 am335x_evm omap4_panda omap5_evm
am335x_evm_uart4 devkit8000 tricorder mcx twister
omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand).
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
As the CPU name is not configurable, using CPU string directly
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This adds hardware tripping at 110 degrees celsius which must enable
forced system shutdown in case TMU fails to power off.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these
conflicts manually and comment the #else/#endif lines for clarity.
Conflicts:
arch/arm/include/asm/arch-davinci/gpio.h
drivers/gpio/da8xx_gpio.c
Signed-off-by: Tom Rini <trini@ti.com>
Adding CPU detection support for the DRA752 ES1.0 soc.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
The 1 in wkup domain is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.
Also adding the DDR pad io settings required for
OMAP543X SOCs here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.
While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x
Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.
So adding the nessecary register changes for the same.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.
This avoids unnessecary code addition for future socs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.
These change reduces code addition for future Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.
This helps in addition of a new Soc with minimal
changes.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.
Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what
the TRM describes as the correct sequence. In our current (incorrect)
sequence some edge cases may fail to initalize correctly.
Signed-off-by: Tom Rini <trini@ti.com>
Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Local macros apply to both iMX23 and iMX28. This patch renames local
macros with attribute MX28 to MXS.
Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This patch add timer support to i.MX23 and complete bit fields and values
on regs-timrot.h.
Testet on imx23-olinuxino board.
Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to
enable the 'Fast Auto Pre-Charge' found in the memory chip. The
setting is applied after memory initialization and it is worth
document it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
The power switch option is compatible with i.MX23 and i.MX28 so the
configration option needs to reflect it. We choose
'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.
First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.
Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.
Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.
Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
The real reason for memory instability was the fact that the EMI block
was gated and not reset throughout the boards' operation. This patch
resets the EMI block properly while also reverts the memory voltage bump.
The memory stability issues were caused by the EMI not being reset properly
and thus there is no longer need to run the memory at higher voltage than
it ought to run at.
This partly reverts 8303ed128a .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
This pulls the three following ZYNQ commits into ARM master:
7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board
59c651f4: arm: zynq: Add SLCR support with system reset
00ed3458: arm: zynq: Add lowlevel initialization to C
The issue got introduced in a cleanup by Manjunath Hadli in commit
826e99136e. The eth_getenv_enetaddr_by_index
method will validate the MAC addr and if none is set in the environment
0 will be returned. Set the MAC from the eeprom if no valid address
is found in environment.
Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
This patch adds a function to set ps_hold data driving value high.
This enables the machine to stay powered on even after the initial
power-on condition goes away(e.g. power button).
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds BOOT_DEVICE define for USB booting and fixes
spl_board_init function to call arch_misc_init (this is the place there
musb is initialized).
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
When calling 'make u-boot.imx' the build were failing as it were
expecting the full path for the file; this regression has been
included by commit 71a988a (imximage.cfg: run files through C
preprocessor).
The direct references for u-boot.imx were replaced by $(obj) as
config.mk handles the proper setting of it making it set to $(OBJTREE)
when required.
The build has been test using:
- ./MAKEALL -s mx5 -s mx6
- make u-boot.imx
- make O=/tmp/build
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.
Comparing the watchdog behaviour on a revB versus revC board:
- On a mx6qsabresd revB:
U-Boot > reset
resetting ...
U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
CPU: Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...
- On a mx6qsabresd revC:
U-Boot > reset
resetting ...
U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
CPU: Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR
So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.
Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
These files are for code that runs on the CPU (A15) on T114 boards.
At this time, there is no A15-specific code here.
As T114-specific run-time code is added, it'll go here.
Signed-off-by: Tom Warren <twarren@nvidia.com>
SBC1 is SPI controller 1 on tegra30
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c
Some T30 tables needed whitespace fixes due to checkpatch complaints.
Signed-off-by: Tom Warren <twarren@nvidia.com>
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Using the __weak annotation can make the code cleaner.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
The memory power supply on MX23 didn't pump out enough juice into
the DRAM chip, thus caused occasional memory corruption. Fix this.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.
The mkimage command which uses this preprocessor output
was moved to arch/arm/imx-common/Makefile
.gitignore was updated to ignore .cfgtmp files.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
The MX23 has different handling of the SSP clock and GPMI NAND clock sources,
add necessary quirks into the clock code to properly handle these.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The memory init is slightly different on MX23, thus split the memory
init for mx23 and mx28 into different functions.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The power block on MX23 must first be ungated before it can be operated.
Add function to MXS power init that ungates it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
For i.MX23 we need to pass imx23 as elftosb param.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This adds the boot mode support for i.MX23 processors.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add information to identify i.MX23 chips and its known revisions.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this
synonym and replace with UARTB to disambiguate.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add 16-bit divider support (I2C) to periph table, annotate and
correct some entries, and fix clk_id lookup function.
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch adds basic Tegra30 (T30) build support - no specific
board is targeted.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
These files are for code that runs on the CPU (A9) on T30 boards.
At this time, there are no T30-specific ARMV7 files. As T30-specific
run-time code is added, it'll go here.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidai.com>
This provides SPL support for T30 boards - AVP early init, plus
CPU (A9) init/jump to main U-Boot.
Some changes were made to Tegra20 cpu.c to move common routines
into tegra-common/cpu.c and reduce code duplication.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
When u-boot is compiled for PXA25x processor, pxa/start.S is calling
cpu_init_crit by BL instruction. BL is overwriting lr register so
relocate_code is going into infinite loop. This patch preservs lr
register in r12 before calling cpu_init_crit and after function returns
restores it.
Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Mobile storage is used the CLK_DIV_FSYS3 value.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
To get exactly clock value for mmc, support the get_mmc_clk() like
set_mmc_clk().
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add workaround for the following ARM errata: 743622 and 751472.
The motivation for this change is the following kernel commit 62e4d357a
(ARM: 7609/1: disable errata work-arounds which access
secure registers), which removes the errata from multiplatform kernel.
Since imx has been converted to multiplatform in the kernel, we need to apply
such workarounds into the bootloader.
Workaround code has been taken from arch/arm/mm/proc-v7.S from 3.7.1 kernel.
Explanation of each erratum is provided at "Chip Errata for the i.MX 6Dual/6Quad"
document available at: cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This saves stack and code memory for local copy, and
consumes initialized data memory. For 22 of the 29
kirkwood-based boards, this results in a global saving
of about 30 bytes. For 7 of them, it results in an
increase of 6 to 14 bytes.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Move all the C runtime setup code from every start.S
in arch/arm into arch/arm/lib/crt0.S. This covers
the code sequence from setting up the initial stack
to calling into board_init_r().
Also, rewrite the C runtime setup and make functions
board_init_*() and relocate_code() behave according to
normal C semantics (no jumping across the C stack any
more, etc).
Some SPL targets had to be touched because they use
start.S explicitly or for some reason; the relevant
maintainers and custodians are cc:ed.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Api is added to decode peripheral id based on the interrupt number
of the peripheral.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch add pinmux settings for Exynos4 for mmc0 and mmc2
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Adds functions to extract clock frequency of Exynos4x12 IPs.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit merges branches from samsung, imx and tegra
meant to fix merge issues between u-boot/master and
u-boot-arm/master, as well as a few manual merge fixes.
