Commit graph

22614 commits

Author SHA1 Message Date
Simon Glass
6bc343c24f power: Drop pmic_max77693.c
Drop this driver and the associated CONFIG option, as it is not used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:47 -05:00
Simon Glass
9262fa8b68 nand: Drop CONFIG_NAND_SPEAR
This is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-02-07 14:33:47 -05:00
Simon Glass
9c6e0ee6e1 power: Drop fg_max77693
This is not used in U-Boot. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:47 -05:00
Simon Glass
dd4bd9ad86 qemu: Add a bootdev for qfw
Add a bootdev device for qfw so that it can be used with standard boot.
This simply checks for the correct method and then does the read. Most of
the other logic is handed in a new bootmeth driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-06 13:04:53 -05:00
Simon Glass
a710f5b2eb bootstd: Correct virtio block-device handling
At present virtio tries to attach QEMU services to a bootdev device, which
cannot work. Add a check for this.

Also use bootdev_setup_sibling_blk() to create the bootdev device, since
it allows the correct name to be used and bootdev_get_sibling_blk() to
work as expected.

The bootdev is not created on sandbox since it does have a real virtio
device and it is not possible to read blocks.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: a60f7a3e35 ("bootstd: Add a virtio bootdev")
Reported-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-02-06 13:04:53 -05:00
Simon Glass
d472e93ab4 virtio: Add some debugging
When QEMU does not respond for some reason, it is helpful to have
debugging info to show. Add some.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-06 13:04:53 -05:00
Nikhil M Jain
5f9f816bb8 drivers: video: tidss: TIDSS video driver support for AM62x
Added tidss video driver support which enables display
on oldi panel using AM62x, it creates a simple pipeline
framebuffer==>vidl1==>ovr1==>vp1==>oldi_panel and
calculates clock rates for panel from panel node in
device tree.

To compile TIDSS when user sets CONFIG_VIDEO_TIDSS
add rule in Makefile. Include tidss folder location
in Kconfig.

TIDSS is ported from linux kernel version 5.10.145

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-02-04 18:16:30 +01:00
Nikhil M Jain
3ebe3c703b drivers: video: simple_panel: make simple panel independent of backlight
This patch updates the necessary Kconfigs to make simple panel
driver independent of backlight driver  and compiling backlight
related code in simple-panel driver conditionally to when user
has set CONFIG_BACKLIGHT.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-04 18:16:00 +01:00
Nikhil M Jain
0347cc7732 drivers: core: ofnode: Add panel timing decode.
ofnode_decode_display_timing supports reading timing parameters from
subnode of display-timings node, for displays supporting multiple
resolution, in case if a display supports single resolution, it fails
reading directly from display-timings node, to support it
ofnode_decode_panel_timing is added.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-04 18:13:21 +01:00
Dario Binacchi
f4cf8710a1 video: ti: am335x: restore driver-model code
The commit 82f7b869f5 ("video: Drop CONFIG_AM335X_LCD") removed not
only the LCD legacy implementation but also the code with driver model
support. The patch restores the code with driver model support.

Fixes: 82f7b869f5 ("video: Drop CONFIG_AM335X_LCD")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-04 13:36:23 +01:00
Ioana Ciornei
878a20aa15 drivers: net: fsl_ls_mdio: prevent a NULL pointer dereference
Prevent a NULL pointer dereference in the probe path by checking the
return valud of dev_read_addr_ptr() against NULL.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
cfbd388ae7 drivers: net: fsl-mc: do not use multiple blank lines
Remove the instances in which we have multiple blank lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
f45ed0b5ec drivers: net: fsl-mc: align parameters to the open paranthesis
There were some cases in which the function parameters were not aligned
to the open paranthesis. Fix those instances.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
6dcf5e4477 drivers: net: fsl-mc: remove explicit cast
Remove all the explicit casts from the void* returned by calloc.
With this we also improve a bit the length of those lines and there is
no need to split the assignment.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
8ecf1ca093 drivers: net: fsl-mc: do not prefix decimal values with 0x
The fsl-mc driver printed debug information which used the 0x prefix for
decimal values. This only confuses anyone looking through the log.
Because of this, just remove the prefix and use the "DPXY.<id>" notation
which is the standard one for the DPAA2 objects.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
3ad24e4d36 drivers: net: fsl-mc: remove an useless break statement
The break statement is just after a goto statement, thus it will not get
executed. Just remove it.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Ioana Ciornei
32221ee236 drivers: net: fsl-mc: remove useless assignment of variable
The cur_ptr variable is set to the start of the log buffer but then it's
not used. Just remove the assignment altogether.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-02 14:44:53 -05:00
Tim Harvey
01e7dd050f net: add MV88E6xxx DSA driver
Add a DSA driver for the MV88E6xxx compatible Ethernet switches.

Cc: Marek Behún <marek.behun@nic.cz>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:44:53 -05:00
Tim Harvey
3b8f99a3e7 net: fec: add support for DM_MDIO
Add support for DM_MDIO by registering a UCLASS_MDIO driver and
attempting to use it. This is necessary if wanting to use a DSA
driver for example hanging off of the FEC MAC.

Care is taken to fallback to non DM_MDIO mii bus as several boards define
DM_MDIO without having the proper device-tree configuration necessary
such as an mdio subnode, a phy-mode prop, and either a valid phy-handle
prop or fixed-phy subnode which will cause dm_eth_phy_connect() to fail.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:44:51 -05:00
Tim Harvey
8abb9f6b17 net: ksz9477: remove unnecessary xmit and recv functions
Remove the unnecessary xmit and recv functions.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-02-02 14:22:08 -05:00
Tom Rini
9918b25d21 Merge commit 'refs/pipelines/15015' of https://source.denx.de/u-boot/custodians/u-boot-tegra 2023-02-02 12:44:12 -05:00
Svyatoslav Ryhel
adf869045d drivers: timer: add driver for ARMv7 based Tegra devices and T210
Add timer support for T20/T30/T114/T124 and T210 based devices.
Driver is based on DM, has device tree support and can be
used on SPL and early boot stage.

Arm64 Tegra (apart T210) according to comment in tegra-common.h use
architected timer.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-02 10:16:41 -07:00
Svyatoslav Ryhel
87a758652b ARM: tegra: remap clock_osc_freq for all Tegra family
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
2023-02-02 10:16:41 -07:00
Marek Vasut
1006b33b3a net: ravb: Drop SoC-specific compatible support
The current set of U-Boot upstream R-Car Gen3 DTs all contain generic
"renesas,etheravb-rcar-gen3" compatible strings, drop the SoC specific
compatible string support from U-Boot to reduce size and duplication.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:21 +01:00
Hai Pham
1b4ca865b2 clk: renesas: rcar-gen3: Factor out CPG library
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock and RPC clock handling and hook them to the generic Gen3
CPG driver so we have an equal state.

Based on Linux commit [1] and [2] by Wolfram Sang

[1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library")
[2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to
the library")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
       - Rebase on changes to
         clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
       - Use u32_encode_bits/GENMASK bitfield ops
2023-02-02 01:49:20 +01:00
Hai Pham
d8132ae37a clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. Hence, new clock types are introduced
respectively.

Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0
clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
       - Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types
         which is now part of common clock types in rcar-gen3-cpg.h instead
2023-02-02 01:49:20 +01:00
Hai Pham
4dbbc3f373 clk: renesas: Switch to new SD clock handling
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.

Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk:
renesas: rcar-gen3: Switch to new SD clock handling") and commit
e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
       - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
       - Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and
         rate = 200000000, the divider would be 0 and table lookup
	 would fail.
       - Turn rcar_clk_get_table_val into signed integer, so it can
         return 0 as a valid value and negative values as errors.
       - Make the code operate on correct clock and add comment
         which explains the reasoning behind it.
       - Rebase on changes to
         clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
2023-02-02 01:49:20 +01:00
Hai Pham
c287c184ae clk: renesas: Handle E3/D3 RPCSRC clock
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent.  Add a new
macro to describe it, reusing the existing clock type for R-Car E3.

As both E3/D3 RPCSRC clock divider are different from the rest of R-Car
Gen3, keep the original implementation from Linux.

Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC
clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add
RPC clocks") by Geert Uytterhoeven.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Add D3 tweaks
2023-02-02 01:49:20 +01:00
Hai Pham
a1ec0bbc28 clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
Introduce new helper function to handle clock type that uses
clk_div_table struct. Based vaguely on Linux code. Make use
of clk_div_table in RPC clocks handling.

The E3/D3 RPCSRC need to be handled differently and will be addressed in
subsequence patch.

Based on Linux commit db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC
clocks") by Sergei Shtylyov.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Squash patches to avoid adding unused code:
         clk: renesas: Make use of clk_div_table in RPC clocks handling
         clk: renesas: Introduce rcar_clk_get_rate64_div_table function
       - Move the new code to the beginning of clk-rcar-gen3 to avoid
         tables mixed with code
       - Use rcar_ prefix for get_table_div function
       - Get rid of custom macros, use GENMASK. Use custom field_get
         implementation as the generic FIELD_GET does not support
	 constant mask and u32_get_bits requires higher optimization level
       - Pass in the register bit mask instead of width/shift combination
       - Turn rcar_clk_get_rate64_div_table into s64, as it can return -EINVAL
2023-02-02 01:49:20 +01:00
Marek Vasut
d48c38db13 clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct clk_div_table
Replace custom local structure with matching one from clk-provider.h .
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
3c78ce8680 mmc: renesas-sdhi: Flag non-standard SDnH handling for V3M
V3M handles SDnH differently than other Gen3 SoCs, so let's add a
separate entry for that. This will allow better SDnH handling in the
future.

Based on Linux commit 627151b4966f ("mmc: renesas_sdhi: Flag
non-standard SDnH handling for V3M") by Wolfram Sang

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
89f9e729be mmc: renesas-sdhi: Drop R-Car H3 ES3.0 HS400 calibration table
It is unnecessary, so clean it up.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message, mention ES3.0
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
d919bb9830 mmc: renesas-sdhi: Add R8A77961 M3-W+ support
Support R8A77961 M3-W+ SoC.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
1cdabcc6a4 mmc: renesas-sdhi: Adjust HS400 calibration offsets for M3-W r1.3
Still uses 0x3 for now, adjust the offset value to TMPPORT3 accordingly

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
af95db514d mmc: renesas-sdhi: Adjust HS400 calibration tables
Adjust HS400 calibration tables based on Linux settings

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
6d7d4c4821 mmc: renesas-sdhi: Filter out HS400 on M3-W r1.2, V3M, V3H r1.x, D3
Further filter out HS400 support on certain SoCs.

Since M3-W r1.2 does not support HS400, drop the calibration table and
rename the one for M3-W r1.3 to r8a7796_rev13_calib_table

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-02 01:49:20 +01:00
Hai Pham
01cbce80c1 mmc: renesas-sdhi: R-Car M3 r1.3 also uses 4 tuning taps
Early ES revisions of M3-W SoCs requires 4-tap HS400. Reflect the status
from datasheet.

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
a61a824169 clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_reg
Drop 'core' parameter from gen3_clk_get_rate64_pll_mul_reg() function
as it is only used in debug print. No functional change except for the
debug print, which is disabled by default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
21a8dbc369 clk: renesas: Use pre-defined offset for RPC clocks
Since commit f7b4e4c094 ("clk: renesas: Synchronize R-Car Gen3 tables
with Linux 5.12"), the custom macros for RPC clocks were dropped.

Use pre-defined offset for RPC clocks, same as what Linux does, instead
of retrieving it from the macros

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
326e05c5e2 clk: renesas: Add and enable CPG reset driver
Add trivial reset driver extension to the CPG clock driver. The change
turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy
driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock
driver as well as generic rcar_rst UCLASS_RESET reset driver to the
CPG DT node. This way, any other drivers which use the 'reset' DT
property can now obtain valid reset handle backed by a reset driver.

The clock tables have been updated to represent the CPG driver and only
implement the generic CPG proxy driver bind call, which binds the clock
and reset drivers.

The DM_RESET is now enabled for all R-Car Gen3 platforms.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
d1c886f563 clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
Add support for the R-Car M3-W+ (R8A77961) SoC.
R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for
both SoCs to share a driver.

Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961
CPG/MSSR support")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
9d16ed44f0 clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_CLK_R8A77961.

Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796
to CLK_R8A77960")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
83fc4729a5 clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7
Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
48e65a67bf clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7
Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
993cf4c5d3 clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7
Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
59752ef264 clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7
Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
733da621d5 clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Rename CLK_TYPE_R8A779A0_ to CLK_TYPE_GEN4_ to match the new
clock tables. Add CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_RPC and
CLK_TYPE_GEN4_RPCD2 macros and handling into Gen3 CPG core.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
4fc053f1e2 clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.1.7
Synchronize R-Car R8A77995 D3 clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
68a23c2345 clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.1.7
Synchronize R-Car R8A77990 E3 clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
df5e5b9870 clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.1.7
Synchronize R-Car R8A77980 V3H clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
d3292b7944 clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.1.7
Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
1ec51f9203 clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.1.7
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
5a2d153149 clk: renesas: Synchronize R8A7795 H3 clock tables with Linux 6.1.7
Synchronize R-Car R8A7795 H3 clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Hai Pham
c206dfd27e clk: renesas: Add dummy SDnH clock
Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.

Based on Linux series by Wolfram Sang:
commit a31cf51bf6b4b ("clk: renesas: rcar-gen3: Add dummy SDnH clock"),
commit 1abd04480866c ("clk: renesas: rcar-gen3: Add SDnH clock"),
commit 63494b6f98f26 ("clk: renesas: r8a779a0: Add SDnH clock to V3U")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Switch to gen3_clk_get_rate64
2023-02-02 01:49:20 +01:00
Hai Pham
eaa4a7d411 pinctrl: renesas: r8a7796: Add R8A77961 PFC support
R-Car M3-W+ (R8A77961) is pin compatible with R-Car M3-W (R8A77960),
which allows for both SoCs to share a driver.

Based on Linux commit 708c69e9eacc ("pinctrl: sh-pfc: r8a7796: Add
R8A77961 PFC support") and 74ce7a8044b0 ("pinctrl: renesas: r8a7796:
Optimize pinctrl image size for R8A774A1")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-02-02 01:49:20 +01:00
Marek Vasut
8a9e8ba9ae pinctrl: renesas: Synchronize R8A779A0 V3U PFC tables with Linux 6.1.7
Synchronize R-Car R8A779A0 V3U PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
37fb54b6e6 pinctrl: renesas: Synchronize R8A77995 D3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A77995 D3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
a22eba36a9 pinctrl: renesas: Synchronize R8A77990 E3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A77990 E3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
3bf4933555 pinctrl: renesas: Synchronize R8A77980 V3H PFC tables with Linux 6.1.7
Synchronize R-Car R8A77980 V3H PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
84d7588cc6 pinctrl: renesas: Synchronize R8A77970 V3M PFC tables with Linux 6.1.7
Synchronize R-Car R8A77970 V3M PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
50970e8c2d pinctrl: renesas: Synchronize R8A77965 M3-N PFC tables with Linux 6.1.7
Synchronize R-Car R8A77965 M3-N PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
0a57a382af pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7796 to
PINCTRL_PFC_R8A77960 .

Also note that a new Kconfig option has been added to enable support
for R8A77961 M3-W+ , the Kconfig option name is PINCTRL_PFC_R8A77961 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
9916e8bfc6 pinctrl: renesas: Synchronize R8A7795 H3 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7795 H3 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7795 to
PINCTRL_PFC_R8A77951 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
f46776cce0 pinctrl: renesas: Synchronize R8A7794 E2 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7794 E2 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
f36c55fc6d pinctrl: renesas: Synchronize R8A7792 V2H PFC tables with Linux 6.1.7
Synchronize R-Car R8A7792 V2H PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
9a955714a1 pinctrl: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.1.7
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
f8ea2a6779 pinctrl: renesas: Synchronize R8A7790 H2 PFC tables with Linux 6.1.7
Synchronize R-Car R8A7790 H2 PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
3e81242160 pinctrl: renesas: Synchronize PFC core with Linux 6.1.7
Synchronize R-Car PFC core with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Parts picked from
pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.18.3
- Add pin groups for the green and high8 subsets of the Video IN pins
- Add MediaLB pins
- Add bias support for various SoCs
- Share more pin group data, to reduce size and ease review
- Miscellaneous cleanups, fixes and improvements.

This contains port of Linux kernel commit
6210905586ae ("pinctrl: renesas: Add shorthand for reserved register fields")
to handle negative entries in GROUP() macros correctly.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02 01:49:20 +01:00
Marek Vasut
71d2a5e5ef ARM: dts: rmobile: Synchronize DTs with Linux 6.1.7
Synchronize R-Car device trees with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

The following script has been used for the synchronization:

$ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do
	if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then
		cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ;
	elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then
		cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/
	else
		echo "NOT FOUND: $i"
	fi
done
$ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' )

Move the include/dt-bindings/{clk,clock}/versaclock.h header used by
the renesas boards to match Linux 6.1.y as well.

Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used
by the arch/arm/dts/r8a774c0-cat874.dts board.

Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts
from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" .

Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect
the card enumeration in ebisu.dtsi /aliases DT node .

Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to
reflect the card enumeration in ulcb.dtsi /aliases DT node .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
2023-02-02 01:49:19 +01:00
Tom Rini
1e1cd8eb2d Merge tag 'fsl-qoriq-2023-2-1' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
make QSPI clock selection optional during SoC init for ls102xa
Fix regulator name for ls2_sfp
Update NXP RCW github repo
2023-02-01 09:31:17 -05:00
Tom Rini
3592a61fa8 For 2023.04
-----------
 
 - several conversion to DM_SERIAL and DM_I2C
 - fixes for Toradex boards
 - PSCI
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
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Merge tag 'u-boot-imx-20230201' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2023.04
-----------

- several conversion to DM_SERIAL and DM_I2C
- fixes for Toradex boards
- PSCI

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
2023-02-01 09:30:52 -05:00
Sean Anderson
4992d8360d misc: ls2_sfp: Fix regulator name
Unlike in Linux, -supply is not automatically appended to regulator
requests. Add it.

Fixes: 2645bc0e12 ("arm: layerscape: Add sfp driver")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-02-01 14:17:29 +08:00
Tom Rini
73a3f51391 Merge https://source.denx.de/u-boot/custodians/u-boot-mmc 2023-01-31 18:28:07 -05:00
Ye Li
7246ec1934 imx8: scu_api: sync sc_rm_is_pad_owned api change
SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This
requires u-boot to update API implementation, since it will cause
compatible issue. Otherwise all pad checking will have problem and
cause pad setting not continue.

Due to the compatible issue, the new u-boot only works with new
SCFW (API version: 1.21 and later).

old scfw + old u-boot: API overflow issue
old scfw + new u-boot, or new scfw + old u-boot: API compatible issue
new scfw + new u-boot: Working

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Jason Liu <Jason.hui.liu@nxp.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-01-31 19:44:23 +01:00
Tom Rini
095d909cf1 - jethub j100: add rescue boot from microSD
- move meson sm command to cmd/meson and add efusedump sub-command
 - switch dwc2 otg to DM for G12A, GXL & AXG
 - Add new boards:
  - Odroid Go Ultra
  - Odroid-N2L
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Merge tag 'u-boot-amlogic-20230131' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- jethub j100: add rescue boot from microSD
- move meson sm command to cmd/meson and add efusedump sub-command
- switch dwc2 otg to DM for G12A, GXL & AXG
- Add new boards:
 - Odroid Go Ultra
 - Odroid-N2L
2023-01-31 10:15:39 -05:00
Ashok Reddy Soma
a1f8abf468 mmc: zynq_sdhci: Add support and quirk for HS400
Add support for HS400 in mode2timing array.
Add a quirk for Versal NET platform to indicate that HS400 is supported
through bit63 of capability register.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
2023-01-31 22:02:27 +09:00
Ashok Reddy Soma
386f5d3673 mmc: sdhci: Enable HS400 support if available in caps
HS400 is indicated in bit63 of capability register in few IP's.
Add a quirk to check this and add HS400 to host capabilities.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
2023-01-31 22:02:27 +09:00
Ashok Reddy Soma
6f5bb9913c mmc: sdhci: Check and call config_dll callback functions
Check if the low level driver supports config_dll callback function and
call it if it does. Call with dll disable before calling set_clock and
with dll enable after it.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
2023-01-31 22:02:27 +09:00
Ashok Reddy Soma
14ef4c7be5 mmc: zynq_sdhci: Add support for eMMC5.1 for Versal NET platform
Add support for eMMC 5.1 for Versal NET platform
 - Add new compatible string(xlnx,versal-net-5.1-emmc).
 - Add CONFIG_ARCH_VERSAL_NET condition wherever required.
 - Add DLL and Delay Chain mode support
 - Add input and output tap delays for eMMC.
 - Add Strobe select tap for HS400 mode.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
2023-01-31 22:02:27 +09:00
Marek Vasut
cf1f7355ae cmd: mmc: Expand bkops handling
Add more capable "bkops" command which allows enabling and disabling both
manual and automatic bkops. The existing 'mmc bkops-enable' subcommand is
poorly named to cover all the possibilities, hence the new-ish subcommand.
Note that both commands are wrappers around the same common code.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-01-31 22:02:27 +09:00
Loic Poulain
ad725073d1 serial: mxc: Speed-up character transmission
Instead of waiting for empty FIFO condition before writing a
character, wait for non-full FIFO condition.

This helps in saving several tens of milliseconds during boot
(depending verbosity).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Fabio Estevam <festevam@denx.de>
2023-01-30 23:23:02 +01:00
Loic Poulain
7150f56a85 serial: mxc: Wait for TX completion before reset
The u-boot console may show some corrupted characters when
printing in board_init() due to reset or baudrate change
of the UART (probe) before the TX FIFO has been completely
drained.

To fix this issue, and in case UART is still running, we now
try to flush the FIFO before proceeding to UART reinitialization.
For this we're waiting for Transmitter Complete bit, indicating
that the FIFO and the shift register are empty.

flushing has a 4ms timeout guard, which is normally more than
enough to consume the FIFO @ low baudrate (9600bps).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-30 23:23:02 +01:00
Marek Vasut
910c7a881f pmic: pca9450: Make warm reset on WDOG_B assertion
The default configuration of the PMIC behavior makes the PMIC
power cycle most regulators on WDOG_B assertion. This power
cycling causes the memory contents of OCRAM to be lost.
Some systems neeeds some memory that survives reset and
reboot, therefore this patch is created.

The implementation is taken almost verbatim from Linux commit
2364a64d0673f ("regulator: pca9450: Make warm reset on WDOG_B assertion")

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-01-30 23:23:01 +01:00
Marek Vasut
6e0ca0658e ddr: imx: Handle both 3733 and 3732 MTps rates
The DDR calibration tool for i.MX8M currently produces 3732 MTps rate in
lpddr4_timing.c , while the PHY code expects 3733 MTps rate. Support both
variants to avoid surprises where the system fails to boot.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-30 21:02:27 +01:00
Mark Kettenis
e330c8b83e usb: xhci: Fix root hub descriptor
When a system has multiple XHCI controllers, some of the
properties described in the descriptor of the root hub (such as
the number of ports) might differ between controllers.  Fix this
by switching from a single global hub descriptor to a hub
descriptor per controller.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-27 14:47:58 -05:00
Mark Kettenis
bdebb00d83 pci: Add Apple PCIe controller driver
This driver supports the PCIe controller on the Apple M1 and
M2 SoCs.  The code is adapted from the Linux driver.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-01-27 14:47:58 -05:00
Mark Kettenis
1fc2329121 iommu: Implement mapping IOMMUs for PCI devices
Systems such as Apple's M1 and M2 SoCs may have separate IOMMUs
for each PCIe root port.  In this case the right IOMMU for a
PCI device behind a particular root port is described by an
"iommu-map" property in the device tree.  Parse this property
and use it to find the right IOMMU device for PCI devices.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-01-27 14:47:58 -05:00
Mark Kettenis
ba1efb3d24 usb: xhci: Implement DMA mapping
An XHCI controller that sits behind an IOMMU needs to map and unmap
its memory buffers to do DMA.  Implement this by inroducing new
xhci_dma_map() and xhci_dma_unmap() helper functions.  The
xhci_dma_map() function replaces the existing xhci_virt_to_bus()
function in the sense that it returns the bus address in the case
of simple address translation in the absence of an IOMMU.  The
xhci_bus_to_virt() function is eliminated by storing the CPU
address of the allocated scratchpad memory in struct xhci_ctrl.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-27 14:47:58 -05:00
Mark Kettenis
862b4a0f32 iommu: apple: Implement DMA mapping operations for Apple DART
Implement translation table support for all the variations of
Apple's DART IOMMU that can be found on Apple's M1 and M2 SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-01-27 14:47:58 -05:00
Mark Kettenis
49a1a4becb test: Add test for IOMMU uclass map/unmap ops
Test that the map and unmap operations work for devices that
have DMA translated by an IOMMU and devices that don't have
DMA translated by an IOMMU.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-27 14:47:58 -05:00
Mark Kettenis
dd6b68ed4f iommu: Add DMA mapping operations
In order to support IOMMUs in non-bypass mode we need device ops
to map and unmap DMA memory.  The map operation enters a mapping
for a region specified by CPU address and size into the translation
table of the IOMMU and returns a DMA address suitable for
programming the device to do DMA.  The unmap operation removes
this mapping from the translation table of the IOMMU.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-01-27 14:47:57 -05:00
Mark Kettenis
053827b3c3 serial: s5p: Use IS_ENABLED where appropriate
There are no SPL/TPL variants of CONFIG_CLK_EXYNOS and
CONFIG_ARCH_APPLE, so switch from CONFIG_IS_ENABLED to
IS_ENABLED.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-27 14:32:55 -05:00
Michael Walle
e71505fc98 pinctrl: fix docstring
Fix the copy and paste error.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-27 12:51:26 -05:00
Michael Walle
75013fa724 pinctrl: get rid of some ifdeffery
Don't define an empty version for pinconfig_post_bind(). Just guard the
call and let the linker garbage collection do the rest. This way, we
also don't have to do any guesswork.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-27 12:51:26 -05:00
Michael Walle
72b8c6d1eb pinctrl: don't fall back to pinctrl_select_state_simple()
If CONFIG_PINCTRL_FULL is enabled, never fall back to the simple
implementation. pinctrl_select_state() is called for each device and it
is expected to fail. A fallback to the simple imeplementation doesn't
make much sense.

To keep the return code consistent, we need to change the -EINVAL (which
was ignored before) to -ENOSYS.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-27 12:51:26 -05:00
Tom Rini
9ddbd70ff9 Xilinx chnages for v2023.04-rc1
makefile:
 - Add multi_dtb_fit dependency
 
 clk:
 - Handle error cases
 
 microblaze:
 - Disable falcon mode and cleanup code around
 
 xilinx:
 - Enable regular expression matching in board_fit_config_name_match()
 - Fix FRU handling for 0xC1 format
 - Fix Xilinx legacy format eeprom parsing
 
 zynqmp:
 - Some DT updates/cleanups
 - Fix IDcode for xck24
 - Remove empty mini config files
 - Add support for k24
 
 versal:
 - Remove empty mini config files
 
 versal_net:
 - Setup timer when runs in EL3
 - Build u-boot.elf for mini configurations
 
 zynq-gem:
 - Add support for new compatible strings
 - Remove support for Avnet Ultrazedev SOM
 - Handle SGMII with PCS phy
 
 spi:
 - Add support for gigadevice parts
 
 misc:
 - Remove CONFIG_TARGET_VENUS ifdef
 - Add missing headers to remove sparse warnings
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Merge tag 'xilinx-for-v2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx chnages for v2023.04-rc1

makefile:
- Add multi_dtb_fit dependency

clk:
- Handle error cases

microblaze:
- Disable falcon mode and cleanup code around

xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing

zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24

versal:
- Remove empty mini config files

versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations

zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy

spi:
- Add support for gigadevice parts

misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings
2023-01-27 10:15:39 -05:00
Stefan Roese
a33ad8051e net: zynq_gem: Wait for SGMII PCS link in zynq_gem_init()
In our system using ZynqMP with an external SGMII PHY it's necessary
to wait for the PCS link and auto negotiation to finish before the xfer
starts. Otherwise the first packet(s) might get dropped, resulting in a
delay at the start of the ethernet transfers.

This is only done when the PHY link is already up, which is done in
phy_startup(). As waiting for the PHY link bits via pcsstatus does not
make much sense, when the link is not available in general (e.g. no
cable connected).

This patch adds the necessary code including a minimal delay of 1 ms
which fixes problems of dropped first packages.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Katakam Harini <harini.katakam@amd.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/20230125070908.1343256-1-sr@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-01-27 08:47:37 +01:00
Algapally Santosh Sagar
b387c25824 drivers: mmc: Change datatype of tuning_loop_counter to int
tuning_loop_counter is of char type, which is not capable of handling
the entire data range of this variable. This is pointed by below sparse
warning. Change datatype to int to fix this.
warning: comparison is always false due to limited range of data type.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230120053617.32463-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-01-27 08:42:47 +01:00
Algapally Santosh Sagar
508e1aa58c gpio: zynqmp: Handle error from get_gpio_modepin
There is a unused variable ret, due to which we are getting sparse warning
as below.
warning: variable 'ret' set but not used [-Wunused-but-set-variable].

Return ret incase of error.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230120053617.32463-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-01-27 08:42:47 +01:00
Tom Rini
b3b6cc28c2 FIT improvements with split-elf, especially for Rockchip
Binman positioning by ELF symbol
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 ADTKaNDsDz4D//Ar3PSt+10eGWWKqrY9ClQwls4lJmJJTIqldf+QDw==
 =l2A4
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Merge tag 'dm-pull-26jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm

FIT improvements with split-elf, especially for Rockchip
Binman positioning by ELF symbol
2023-01-26 21:57:38 -05:00
Tom Rini
b6904cc98a Merge https://source.denx.de/u-boot/custodians/u-boot-spi
- fix return code of sf command (Heinrich)
- fix register reads in STIG Mode (Dhruva)
- Infineon s25fs256t support (Takahiro)
2023-01-26 13:07:06 -05:00
Samuel Holland
c2e13aa9e1 dm: core: Use full printf() format when possible
Use a more accurate check for determining if the full format string will
be handled correctly, since SPL_USE_TINY_PRINTF can be disabled.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-26 10:47:45 -07:00
Takahiro Kuwano
87a6d86571 mtd: spi-nor: Add support for Infineon s25fs256t
Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and
differences comparing to other Spansion/Cypress flash familes are:
  - 4-byte address mode by factory default
  - Quad mode is enabled by factory default
  - Supports mixture of 128KB and 64KB sectors by OTP configuration
    (this patch supports uniform 128KB only)

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26 21:07:45 +05:30
Takahiro Kuwano
eadaadbb8f mtd: spi-nor: Rename s25hx_t prefix
Rename s25hx_t prefix to s25 so that the single set of fixup hooks can
support all other S25 families.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Acked-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26 21:07:16 +05:30
Dhruva Gole
53f4ef0a4b spi: cadence_qspi: use STIG mode for small reads
Fix the issue where some flash chips like cypress S25HS256T return the
value of the same register over and over in DAC mode.

For example in the TI K3-AM62x Processors refer [0] Technical Reference
Manual there is a layer of digital logic in front of the QSPI/OSPI
Drive when used in DAC mode. This is part of the Flash Subsystem (FSS)
which provides access to external Flash devices.

The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for
OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit
mode enabled by default.

Thus, by default controller operates in 32 bit mode causing it to always
align all data to 4 bytes from a 4byte aligned address. In some flash
chips like cypress for example if we try to read some regs in DAC mode
then it keeps sending the value of the first register that was requested
and inorder to read the next reg, we have to stop and re-initiate a new
transaction.

This causes wrong register values to be read than what is desired when
registers are read in DAC mode. Hence if the data.nbytes is very less
then prefer STIG mode for such small reads.

[0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf

Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
[jagan: add tab space for comments]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26 21:01:56 +05:30
Dhruva Gole
2330af2722 spi: cadence_qspi: setup ADDR Bits in cmd reads
Setup the Addr bit field while issuing register reads in STIG mode. This
is needed for example flashes like cypress define in their transaction
table that to read any register there is 1 cmd byte and a few more address
bytes trailing the cmd byte. Absence of addr bytes will obviously fail
to read correct data from flash register that maybe requested by flash
driver because the controller doesn't even specify which address of the
flash register the read is being requested from.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26 21:01:01 +05:30
Takahiro Kuwano
da16d72efd mtd: spi-nor-core: Make CFRx reg fields generic
Cypress defines two flavors of configuration registers, volatile and
non volatile, and both use the same bit fields. Rename the bitfields in
the configuration registers so that they can be used for both flavors.

Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26 20:58:09 +05:30
Kunihiko Hayashi
358f803ae2 spi: Add Socionext F_OSPI SPI flash controller driver
Introduce Socionext F_OSPI controller driver. This controller is used to
communicate with slave devices such as SPI flash memories. It supports
4 slave devices and up to 8-bit wide bus, but supports master mode only.

This driver uses spi-mem framework for SPI flash memory access, and
can only operate indirect access mode and single data rate mode.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26 20:53:20 +05:30
Pengfei Fan
730fcadc67 drivers: spi: sh_qspi.c: Use log_warning() instead of printf()
Use log_warning() instead of printf() to print out driver information

Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26 20:53:20 +05:30
Pengfei Fan
d466f6209d drivers: spi: fix some typos
Fix some typos in spi drivers

Signed-off-by: Pengfei Fan <fanpengfei1@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-01-26 20:53:20 +05:30
Tony Dinh
54a08c4139 ddr: marvell: a38x: Add support for DDR4 from Marvell mv-ddr-marvell repository
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git

up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c

This patch was created by following steps:

	1. Replace all a38x files in U-Boot tree by files from upstream github
	Marvell mv-ddr-marvell repository.

	2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:

	files=drivers/ddr/marvell/a38x/*
	unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
		-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
		-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
		-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
		-UCONFIG_64BIT $files

	3. Manually change license to SPDX-License-Identifier
	(upstream license in  upstream github repository contains long license
	texts and U-Boot is using just SPDX-License-Identifier.

After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.

The only change in this patch are:
	1. Some fixes with include files.
	2. Some function return and basic type defines changes in
	mv_ddr_plat.c (to correct Marvell bug).
	3. Remove of dead code in newly copied files (as a result of the
	filter script stripping out everything other than a38x, dd3, and ddr4).

Reference:
    "ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
    107c3391b9

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-01-26 07:30:20 +01:00
Tom Rini
17e8e58fe6 Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi
This contains some fixes, and the first bunch of some clean up patches
to get rid of legacy GPIO and PMIC code.
Highlight is the DM AXP PMIC driver, which is required to convert some
drivers over to use DM regulators, and also is required to get rid
of some less optimal PMIC setup code in Trusted Firmware. This isn't
enabled by any defconfig yet, but can be enabled manually and works. For
the full glory some patches are still missing, and this requires more
testing, which would be simpler if the core code is upstream.
2023-01-24 21:07:01 -05:00
Michal Simek
988b3fa08d soc: zynqmp: Fix IDcode for xck24
ID code was added by commit ddf8deabc3 ("arm64: zynqmp: Add support for
SVD devices") based on documentation but after receiving part new ID code
came up. That's why fix IDcode to match xck24 module.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7b39aeeec211458ba4132a10beb7ad295eedb87f.1674030324.git.michal.simek@amd.com
2023-01-24 13:55:05 +01:00
Simon Glass
eacc261178 bootstd: Add a new pre-scan priority for bootdevs
We need extensions to be set up before we start trying to boot any of the
bootdevs. Add a new priority before all the others for tht sort of thing.
Also add a 'none' option, so that the first one is not 0.

While we are here, comment enum bootdev_prio_t fully and expand the test
for the 'bootdev hunt' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:41 -05:00
Simon Glass
0c1f4a9fb1 bootstd: Add a SPI flash bootdev
Add a bootdev for SPI flash so that these devices can be used with
standard boot. It only supports loading a script.

Add a special case for the label, since we want to use "spi", not
"spi_flash".

Enable the new bootdev on sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:41 -05:00
Simon Glass
2b3ebf2013 ata: Don't try to use non-existent ports
The controller indicates the number of ports but also has a port map
which specifies which ports are actually valid. Make use of this to
avoid trying to send commands to an invalid port.

This avoids a crash on some controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
a60f7a3e35 bootstd: Add a virtio bootdev
Add a bootdev for virtio so that these devices can be used with standard
boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
00fc8cade8 virtio: Add a block device
The test code for virtio is fairly simplistic and does not actually create
a block device. Add a way to specify the device type in the device tree.
Add a block device so that we can do more testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
902400201d virtio: Avoid strange behaviour on removal
This device does a check on removal which is better handled in the actual
test. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
811c81e889 virtio: Fix returning -ENODEV
This has a special meaning in driver model. There is clearly a device, so
it does not make sense to return this error code. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
59a6be9b11 virtio: Avoid repeating a long expression
Use a local variable to hold this name, to reduce the amount of code that
needs to be read.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
758c706c68 bootstd: Add an NVMe bootdev
Add a bootdev for NVMe so that these devices can be used with standard
boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
0d77f8f1ca bootstd: Add an IDE bootdev
Add a bootdev for IDE so that these devices can be used with standard
boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
8f090b67d0 bootstd: Add a SCSI bootdev
Add a bootdev for SCSI so that these devices can be used with standard
boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
6febc26471 scsi: Remove all children of SCSI devices before rescanning
At present this only unbinds block devices of a certain type. But SCSI
device can have different types of children, including bootdevs.

Unbind all children so tht everything is clean and ready for a new scan.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
ca93d28171 scsi: Correct allocation of block-device name
This should be allocated so that it does not go out of scope. Fix this and
set the log category while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
843160fa7a bootstd: Add an MMC hunter
Add a hunter for MMC. This doesn't do anything at present, since MMC is
currently set up when U-Boot starts. If MMC moves to lazy init then we can
add a hunter function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
04fb2b6e45 bootstd: Add a USB hunter
Add a hunter for USB which enumerates the bus to find new bootdevs.

Update the tests and speed up bootdev_test_prio() while we are here, by
dropping the USB delays.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
ecdf3ab01f dm: usb: Mark the device name as alloced when binding
Since usb_find_and_bind_driver() allocates the device name it should tell
driver about that, to avoid memory leaks. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:40 -05:00
Simon Glass
b85fc8dbab bootstd: Add a default method to get bootflows
The code in these functions turns out to often be the same. Add a default
get_bootflow() function and allow the drivers to select it by setting
the method to NULL.

This saves a little code space.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:39 -05:00
Simon Glass
3a2cb96e5d dm: mmc: Use bootdev_setup_sibling_blk()
At present MMC uses the bootdev_setup_for_dev() function to set up the
bootdev. This is because MMC only has one block-device child, so does not
need to worry about naming of the bootdev.

However this inconsistency with other bootdevs that use block devices is a
bit annoying. The only real reason for it is to have a name like
'mmc0.bootdev' instead of 'mmc0.blk.bootdev'.

Update bootdev_setup_sibling_blk() to drop '.blk' from the name where it
appears, thus removing the only reason to use the bootdev_setup_for_dev().
Switch MMC over to the subling function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:39 -05:00
Simon Glass
d0075059e4 ide: Drop non-DM code for BLK
We require CONFIG_BLK to be enabled now, so this code is unused. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:39 -05:00
Simon Glass
67bb973122 sandbox: mmc: Start off with a zeroed file
When running multiple tests the mmc emulator calls malloc() to obtain the
memory for its disk image. Since the memory is not cleared, it is possible
that it happens to contain a partition table.

The dm_test_part() test (for one) relies on mmc0 being empty on startup.
Zero the memory to ensure that it is.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:39 -05:00
Simon Glass
3d01254140 dm: core: Support sorting devices with dm tree
Add a -s flag to sort the top-level devices in order of uclass ID.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-23 18:11:39 -05:00
Jernej Skrabec
cd108f2795 video: sunxi: dw-hdmi: Read address from DT node
Currently HDMI controller MMIO address is hardcoded. Change that so
address is read from DT node. That will make adding support for new
variants a bit easier.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-23 01:18:31 +00:00
Jernej Skrabec
2f52be8b8d video: sunxi: dw-hdmi: Probe driver by compatible
Currently the sunxi dw-hdmi driver is probed unconditionally,
even if there is no such device.

Switch the driver to probing via a compatible string. This brings many
benefits; the driver is only probed when needed, and now it can read the
DT node.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-23 01:18:31 +00:00
Samuel Holland
77024aa7d9 clk: sunxi: Add DE2 display-related clocks/resets
Add clock/reset definitions for display-related peripherals, including
the display engine, TCONs, and DSI and HDMI encoders, so those drivers
can be converted to DM clock consumers instead of directly manipulating
the CCU registers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-23 01:18:31 +00:00
Samuel Holland
55ad509c11 power: pmic: axp: Bind regulators from the DT
Now that a regulator driver exists for this PMIC, hook it up to the
device tree "regulators" subnodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-23 01:18:31 +00:00
Samuel Holland
27a93dd4a9 power: regulator: Add a driver for AXP PMIC regulators
This driver handles most voltage regulators found in X-Powers AXP PMICs.
It is based on, and intended to replace, the regulator driver in TF-A.

AXP PMIC regulators can be divided into 6 categories:
 - Switches without voltage control => fully supported.
 - Single linear range => fully supported.
 - Two linear ranges, "step" and "2 * step" => fully supported.
 - Two linear ranges, "step" and "5 * step" => only the first range is
   supported. No boards are known to use the second range.
 - Non-linear voltage values => fully supported.
 - LDOs shared with GPIO pins => not supported.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-23 01:18:31 +00:00
Samuel Holland
dc1b1d1458 power: pmic: axp: Provide a variant ID in the driver data
Subordinate regulator drivers can use this enumerated ID instead of
matching the compatible string again.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-23 01:18:31 +00:00
Andre Przywara
ba16b53101 sunxi: mmc: group non-DM specific functions
As the SPL code for sunxi boards does not use the driver model, we have
two mmc_ops structures, one for DM, one for non-DM. The actual hardware
access code is shared, with the respective callback functions using that
common code.

To make this more obvious and easier to read, reorder the functions to
group them: we first have the common code, then the non-DM bits, and
the proper DM implementation at the end.
Also document this structure in the comment at the beginning of the file.

No functional change intended.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-01-21 01:32:23 +00:00
Andre Przywara
5db81f1cc8 sunxi: mmc: ignore card detect in SPL
The sunxi MMC code does not use the DM in the SPL, as we don't have a
device tree available that early, also no space for it.
This also means we cannot access the card-detect GPIO information from
there, so we have Kconfig symbols called CONFIG_MMCx_CD_PIN, which each
board has to define. This is a burden, also requires extra GPIO code in
the SPL.
As the SPL is the natural successor of the BootROM (from which we are
loaded), we can actually ignore the CD pin completely, as this is what
the BootROM does as well: CD GPIOs are board specific, but the BootROM
is not, so accesses the MMC devices anyway.
Also, as we must have been loaded from an MMC device when reaching this
code, there must have been a card in the slot.

Remove the card detect code from the non-DM implementation of the sunxi
MMC driver, to get rid of this unneeded code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-01-21 01:32:23 +00:00
Tom Rini
6e7df1d151 global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-20 12:27:24 -05:00
Tom Rini
ad24234468 watchdog: Clean up defaults for imx_watchdog / ulp_wdog
In imx_watchdog, clean up the comment to just note the range now, as we
do not need to set the default here as Kconfig does this for us. For
ulp_wdog, set the default value via Kconfig instead.

Cc: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-01-20 12:27:23 -05:00
Tom Rini
c50c778ea7 usbtty: Remove default CONFIG_USBD_* values
For this legacy driver, the only user sets these values in Kconfig, so
we can remove them from the header.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:23 -05:00
Tom Rini
89c90cadf3 nxp: Finish migration of SYS_FSL_IFC_BANK_COUNT to Kconfig
As this is used on both ARM and PowerPC platforms, this needs to be
asked in arch/Kconfig.nxp.  Set the PowerPC defaults based on
arch/powerpc/include/asm/config_mpc85xx.h and remove the default set in
drivers/mtd/nand/raw/fsl_ifc_nand.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:06 -05:00
Tom Rini
bd22bde92e net: phy: mv88e61xx: Finish migration of MV88E61XX_FIXED_PORTS
Set the default for MV88E61XX_FIXED_PORTS to 0x0 in Kconfig, and move
the comment from code to the help to explain what this does.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-20 12:27:06 -05:00
Tom Rini
8de73b7bc1 usb: musb: Rename CONFIG_USB_MUSB_TIMEOUT to MUSB_TIMEOUT
This variable has never been configured to another value at present, and
was not converted to Kconfig. Opt instead to rename this to
MUSB_TIMEOUT.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-20 12:27:06 -05:00
Tom Rini
8fe042be9a fpga: Migrate CONFIG_MAX_FPGA_DEVICES to Kconfig
This is always defined to 5, so use that as the default.

Cc: Michal Simek <michal.simek@amd.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
2023-01-20 12:27:06 -05:00
Tom Rini
81451a3985 i2c: fsl_i2c: Rework usage of CONFIG_SYS_IMMR
This driver is used on both m68k, where CONFIG_SYS_IMMR is not used, and
PowerPC an ARM where it is. Abstract this to a new value rather than
re-defining a CONFIG symbol on m68k.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-20 12:27:06 -05:00