P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:
9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.
Signed-off-by: Chunhe Lan <b25806@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Set default configuration to have SDHC controller enabled,
AUDIO enabled(codec clock sources is 12MHz) and disable TDM.
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Make the support for ATI graphics cards mutually exclusive with DIU.
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We don't really ever use Video cards on corenet_ds style boards and its
bloating our image which is close the its max size. Drop support and
also kill some defines for non-PNP PCI which we never use.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM
and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more
appropriate CONFIG_SYS prefix as well as be consistent with 83xx.
Signed-off-by: Matthew McClintock <msm@freescale.com>
cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
U-Boot itself takes up more than 0x40000 bytes, so we can't use that
sector for the environment. Move it down a page.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Have CONFIG_ENV_ADDR be based on CONFIG_ENV_OFFSET rather than the other
way around so that we can use CONFIG_ENV_OFFSET during build. It also
avoids a little address duplication.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Info about the hardware can be found here:
http://www.dilnetpc.com/dnp0086.htm
Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
collect code which protects default sectors in a function, called
flash_protect_default. So boardspecific code can call it too.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Clean up the macro defintions used to enable DIU (video) support on the
MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS,
which is newer. Add software cursor support to all three boards.
Also document the CONFIG_FSL_DIU_FB in the README.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We implement our own mmc_get_env_addr since the environment variables are
written to just after the u-boot image on SDCard, so we must read the MBR
to get the start address and code length of the u-boot image, then
calculate the address of the env.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.
In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage
device support using PCI EHCI module.
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
PCA9557 is parallel I/O expansion device on I2C bus which stores various
board switch settings like NOR Flash-Bank selection, SD Data width.
On board:
switch SW5[6] is to select width for eSDHC
ON - 4-bit [Enable eSPI]
OFF - 8-bit [Disable eSPI]
switch SW4[8] is to select NOR Flash Bank for Booting
OFF - Primary Bank
ON - Secondary Bank
Read board switch settings on p1_p2_rdb and configure corresponding
eSDHC width.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash
boot loaders because:
- P1_P2_RDB boards have soldered DDR so no need for SPD
- Also P102x has 256K L2 cache size so becomes a limiting factor for
size of image that could be loaded in SRAM mode and would require three
stage boot loader (TPL).
Changes done:
1. CONFIG_SYS_TEXT_BASE to 0x11000000
2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.
* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
(features doesn't exist on P1023/P1017)
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move the include of mpc85xx/u-boot-nand.lds to utilize
CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Read MAC address from EEPROM. Add hwconfig settings.
Modified the default othbootargs to include the cache-sram-size
parameter. This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB kernel and used by the Gianfar driver.
Also cleanup some of the boot commands.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9
respectively).
We enable EXT2, FAT, and parition support for both MMC & USB configs.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Purple SoC and eval board are not actively maintained since years.
This patch removes the support completely as aggreed with Wolfgang Denk.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
This patch adds support for reading an ONFI page parameter from a NAND
device supporting it. If this is the case, struct nand_chip onfi_version
member contains the supported ONFI version, 0 otherwise.
This allows NAND drivers past nand_scan_ident to set the best timings for the
NAND chip.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on
P1022/P1013 SoCs.
Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is common pwm driver of S5P.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Update the PCIe address map to match standard FSL memory map.
Additionally, fix the TLBs so the cover the PCIe address space properly
so cards plugged in like an e1000 work correctly.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For example, an input of 0x80000000 should print:
2147.484 instead of -2147.-483.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If no Flash is connected to cs1, Linux crashes, because
reg entries are not correct adapted.
Following fix is needed:
- swap base addresses in CONFIG_SYS_FLASH_BANKS_LIST, as
flash bank 1 is on chipselect 0 and flash bank 2 on
chipselect 1
- call fdt_fixup_nor_flash_size() from ft_board_setup()
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Wolfgang Denk <hs@denx.de>
cc: Werner Pfister <Pfister_Werner@intercontrol.de>
cc: Detlev Zundel <dzu@denx.de>
Currently, pixis_reset altbank does not work properly. This patch
uses the correct mask to boot into the alternate bank.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Since there are lots of difference between kirkwood and armada series,
it is better to seperate them but still keep the most common file
shared by all marvell platform in the mv-common configure file.
This patch move the kirkwood only driver definitoin in mv-common to
the <soc_name>/config.h.
This patch is tested with compilation for armada100 and guruplug.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Port USB gadget RNDIS protocol support from linux-2.6.26
(.27 gadget stack actually has composite drivers).
Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>
This adds support for using USB Ethernet dongles in host mode. This is just
the framework - drivers will come later. A new config option called
CONFIG_USB_HOST_ETHER can be defined in board config files to switch this
on.
The was originally written by NVIDIA and was cleaned up for release by the
Chromium authors.
Signed-off-by: Simon Glass <sjg@chromium.org>
Changed both to use a common timeout for URB submission, since they were using
different values and EHCI's was too short.
Also fixed EHCI to actually check if urb submission succeeded, rather than
silently continuing into the weeds.
Change-Id: I7f71499ffaa05187d8e5618db2419e1606007b82
Signed-off-by: Simon Glass <sjg@chromium.org>
Fix the problem which cannot build the U-boot, if we only set
the CONFIG_ENV_IS_IN_SPI_FLASH.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Board EEPROM is used to read/save Ethernet MAC addresses.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Use SPMR instead of HRCWL when calculating clocks as HCRWL
may be changed and the CPU will not pick up all changes
until there is a POR. u-boot will think SPMF has changed and get
the clocks wrong.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fix a problem for the pcie enumeration when the mpc83xx
pcie controller is connected with switch or we use both of the two
pcie controller.
Signed-off-by: Leo Liu <liucai.lfn@gmail.com>
fix codingstyle and compiler warning: 'pcie_priv' defined but not used
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Some VCT boards lacks the support of networking or USB.
Additionally that support is disabled in small image
configurations.
If CONFIG_CMD_NET should not used the CONFIG_CMD_NFS option
have to be disabled too. Otherwise the linker fails with
unresolved symbols.
If CONFIG_VCT_SMALL_IMAGE is set than CONFIG_CMD_NET and
CONFIG_CMD_USB are disabled at the end of vct.h.
This is not adequate because CONFIG_CMD_USB enables additional
options and the linker fails again with unresolved symbols.
This patch adds an early check against CONFIG_VCT_SMALL_IMAGE
so the additional options are only enabled if they are really
needed.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Using hwconfig to turn on/off ECC, without re-compiling.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM,
Ethernet, and more.
This patch supports the following functions:
- 256MB DDR3-SDRAM
- SPI ROM
- Ethernet
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Move CONFIG_SYS_TEXT_BASE to the board's config file, and remove the
unnecessary config.mk file.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds support for Samsung s5pc210 universal board
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* add CONFIG_SYS_SDRAM_BASE and CONFIG_SYS_INIT_SP_ADDR
* do not update gd->bd in dram_init() because bd is unavailable then
* move CONFIG_SYS_TEXT_BASE from config.mk to a320evb.h
* remove config.mk
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Support for DM6467 was incomplete and the build failed
as well. Patches were sent to the list but have not been
added. This enhances the DM6467 support.
Some more patches will need to be sent to bring
it in line with what is available in internal TI
trees
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Added support for MMC/SD cards for Davinci. This feature is enabled by
CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC
options. This is tested on DM355 and DM365 EVMs with both the available mmc
controllers.
Signed-off-by: Alagu Sankar <alagusankar@embwise.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The patch adds suupport for the Freescale's mx35pdk board
(known as well as mx35_3stack).
The board boots from the NOR flash. Following devices
are supported:
- two ethernet devices (FEC and SMC911x on debug board)
- I2C
- PMIC (MC13892) via I2C interface
- UART
- NOR flash (64MB)
- NAND flash (2GB)
- basic access to mc9sdz60 registers via I2C interface
Signed-off-by: Stefano Babic <sbabic@denx.de>
The patch adds helper funtions for basic access to the registers
of the MC9sdz60 chip (multifunctional device with RTC and CAN) via
I2C interface.
Signed-off-by: Stefano Babic <sbabic@denx.de>
The patch adds basic support for the Freescale's i.MX35
(arm1136 based) processor.
The patch adds also a prototype for the initialization
of the FEC(ethernet controller) to netdev.h to avoid
warnings.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Supported:
MMC
IDE
PMIC
SPI flash
LEDs
I can boot the kernel supplied by freescale/genesi with this from MMC card
and/or PATA disk.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Add initial support for Freescale MX53 processor,
- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro
Signed-off-by: Jason Liu <r64343@freescale.com>
The early bootup information is not print out due to
the UART pin iomux not set up correctly before board_init
Add the board_early_init_f function and enable the
CONFIG_BOARD_EARLY_INIT_F. Move the UART pin setting
from board_init to board_early_init_f function.
This patch also move the FEC pin iomux setup to the
board_early_init_f.
Signed-off-by: Jason Liu <r64343@freescale.com>
Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.
Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling). This is achieved by means of
custom ld script.
Signed-off-by: Alex Dubov <oakad@yahoo.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix the bits for ngpixis to reset to alternative bank. Originally the mask
was 0xE0, which left it possible to reset to bank 3 if DIP switch is set to
boot from bank 1. Changing to 0xF0 gurantees to reset to bank 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
u-boot cannot be compiled after disabling CONFIG_PCI.
Place PCI related codes under #ifdef CONFIG_PCI
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ECC can be turned on/off by hwconfig without recompiling. So enable it
by default.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.
Eventually this should be handled by Kconfig & defconfigs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
There are several users of the hwconfig APIs (8xxx DDR) before we have
the environment properly setup. This causes issues because of the
numerous ways the environment might be accessed because of the
non-volatile memory it might be stored in. Additionally the access
might be so early that memory isn't even properly setup for us.
Towards resolving these issues we provide versions of all the hwconfig
APIs that can be passed in a buffer to parse and leave it to the caller
to determine how to allocate and populate the buffer.
We use the _f naming convention for these new APIs even though they are
perfectly useable after relocation and the environment being ready.
We also now warn if the non-f APIs are called before the environment is
ready to allow users to address the issues.
Finally, we convert the 8xxx DDR code to utilize the new APIs to
hopefully address the issue once and for all. We have the 8xxx DDR code
create a buffer on the stack and populate it via getenv_f().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
Rather than defining it config.mk we can set it in config.h and remove
config.mk from several boards that don't need it.
We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for
config.h to set.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
Crc7 is used to compute mmc spi command packet checksum.
Copy from linux-2.6 lib/crc7.c include/linux/crc7.h
commit ad241528c4919505afccb022acbab3eeb0db4d80
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
difference to previous board version:
- M29W128GH flash from Numonyx
- SDRAM ISSI IS45S16800 (Option A2 105°C)
- rev5 uses RTC RV-3029-C2
- update cs0 and cs1 baseaddr and length
depending on the detected flash size.
- added Werner Pfister <Pfister_Werner@intercontrol.de>
as maintainer for the digsy board variants
- As the M29W128GH needs a special flash_cmd_reset()
document that in the new file doc/README.cfi.
- move "#endif /* CONFIG_CMD_IDE */" to the right place
- remove LOWBOOT config option for digsy_mtc and digsy_mtc_rev5
boards
- change doc/README.cfi as Stefan Roese suggested
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
cc: Wolfgang Denk <hs@denx.de>
cc: Stefan Roese <sr@denx.de>
cc: Werner Pfister <Pfister_Werner@intercontrol.de>
cc: Detlev Zundel <dzu@denx.de>
The MPC852 based mgsuvd and kmsupx4 boards from keymile
were initially ported but later on not developed further. So
the respective files were removed to avoid unneeded merging
and maintenance.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher<hs@denx.de>
Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus
monitor timeout. Set timeout to maximum to avoid.
Based on a patch from Lan Chunhe <b25806@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CoreNet Platform Cache single-bit data error scrubbing will cause data
corruption. Disable the feature to workaround the issue.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CoreNet Platform Cache single-bit tag error scrubbing will cause tag
corruption. Disable the feature to workaround the issue.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CONFIG_SYS_BOOTMAPSZ has been 16M on these boards for some time so we
should also allow the kernel image to be up to 16M decompressed.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
False multi-bit ECC errors will be reported by the eSDHC buffer which
can trigger a reset request.
We disable all ECC error checking on SDHC.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.
Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P2020 has 2 SRIO ports and they are useable on the P2020 DS board.
Enable them using the common SRIO init code.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe
controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
Remove duplicated code in MPC8610HPCD board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in P1_P2_RDB boards and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in MPC8569MDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in MPC8568MDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in MPC8548CDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in MPC8641HPCN board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in MPC8544DS board and utilize the common
fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3
specially to setup the additional memory map region and we utilize a
single LAW to cover the controller.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in P2020DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in MPC8572DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus. Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.
Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
This config option is for an erratum workaround; rename it to be more
clear. Also, drop it from config files don't need it and were
undefining it.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some new platform's esdhc pins don't share with other function.
The eSDHC shouldn't be disabled, even if "esdhc" isn't defined
in hwconfig env variable.
Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem.
Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting
from NAND.
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Neither of these parts should have the erratum this is meant to
work around. Delete it.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The PM854/PM856 boards are no longer maintained and thus we are removing
support for them.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
This patch sync with David's patch on Linux for handling nand_scan_ident.
commit 5e81e88a4c140586d9212999cea683bcd66a15c6
Author: David Woodhouse <David.Woodhouse@intel.com>
Date: Fri Feb 26 18:32:56 2010 +0000
mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
This patch add addition suffix to nand write to give the uboot
the power to directly burn the yaffs image to nand.
Signed-off-by: Lei Wen <leiwen@marvell.com>
PCI is not used at all on lwmon5. So lets remove it. It saves space and
reduces boot time a bit (approx. 50ms).
Signed-off-by: Stefan Roese <sr@denx.de>
Patch "Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value"
(sha1: 25ddd1fb0a)
introduce GENERATED_GBL_DATA_SIZE which is sizeof aligned gd_t
(currently 0x40).
Microblaze configs used 0x40(128) because this place also contained
board info structure which lies on the top of ram.
U-Boot is placed to the top of the ram (for example 0xd7ffffff)
and bd structure was moved out of ram.
This patch is fixing this scheme with GENERATED_BD_INFO_SIZE
which swap global data and board info structures.
For example:
Current: gd 0xd7ffffc0, bd 0xd8000000
Fixed: gd 0xd7ffffc0, bd 0xd7ffff90
Signed-off-by: Michal Simek <monstr@monstr.eu>
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We have config_defaults.h which are random configuration settings that
everyone gets by default. We also have config_cmd_default.h which is a
recommended list of defaults but boards have to opt into. Now we have
config_cmd_defaults.h which is a list of defaults that everyone gets
and has to actively opt out of.
For now, we populate it with the bootm command which previously was
unable to be disabled.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch supports T-SH7706LSR board.
This is constitution almost same as shmin (T-SH7706LAN).
Therefore, most functions work by a change of the setting of config.
http://web.kyoto-inet.or.jp/people/takagaki/T-SH7706/T-SH7706LSR.htm
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds support for the SHMIN SH7706 board(T-SH7706LAN).
The CPU of this board is SH7706.
There are SDRAM of 32M byte, Flash memory of 512K byte, Serial,
10Base Ether and MMC.
http://web.kyoto-inet.or.jp/people/takagaki/T-SH7706/T-SH7706.htm
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add reginfo as a default command for p1022ds boards
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The non-reentrant versions of the hashtable functions operate on a single
shared hashtable. So if two different people try using these funcs for
two different purposes, they'll cause problems for the other.
Avoid this by converting all existing hashtable consumers over to the
reentrant versions and then punting the non-reentrant ones.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch adds the possibility to (optinally) write to the
flash configuration register. The Intel style CFI chips support
such a register that can be used to configure the operation
mode to a non-default value.
This method will be used by the t3corp board, which needs to
configure the DS617 Xilinx flash for async read mode.
Signed-off-by: Stefan Roese <sr@denx.de>
Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch includes the following changes for the lwmon5 board support:
- Enable cache in SDRAM
- Use common EHCI driver instead of the PPC4xx specific OHCI driver
This can be done since only high-speed devices are connected.
- Remove cached TLB entry again after ECC setup
- Use correct define for cache enabling
(CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE)
- Enable FIT image support
Signed-off-by: Stefan Roese <sr@denx.de>
The t3corp board has an Xilinx DS617 flash chip connected to the
onboard FPGA. This patch adds support for these chips. Board
specific flash accessor functions are needed, since the chips
can only be read correctly in 16bit mode.
Additionally the FPGA chip-selects are configured for device-paced
transfers (ready is enabled).
Signed-off-by: Stefan Roese <sr@denx.de>
