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powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Poonam Aggrwal
Kumar Gala
parent
66c74fca18
commit
e0082f7cb4
4 changed files with 84 additions and 7 deletions
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@ -107,6 +107,9 @@ int checkboard (void)
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cpu = gd->cpu;
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printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
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#ifdef CONFIG_PHYS_64BIT
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puts ("(36-bit addrmap) \n");
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#endif
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setbits_be32(&pgpio->gpdir, GPIO_DIR);
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/*
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@ -25,19 +25,20 @@
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
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CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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12
boards.cfg
12
boards.cfg
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@ -509,15 +509,24 @@ MPC8572DS powerpc mpc85xx mpc8572ds freesca
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MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
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MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
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P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB
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P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT
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P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD
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P1011RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SPIFLASH
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P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND
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P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD
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P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH
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P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB
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P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT
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P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD
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P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH
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P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND
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P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
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P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH
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P1022DS powerpc mpc85xx p1022ds freescale
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P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB
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P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT
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P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD
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P2010RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SPIFLASH
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P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND
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P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD
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P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH
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@ -525,6 +534,9 @@ P2020DS powerpc mpc85xx p2020ds freesca
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P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT
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P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2
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P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB
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P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT
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P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD
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P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SPIFLASH
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P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND
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P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD
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P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH
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@ -30,6 +30,10 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_36BIT
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#define CONFIG_PHYS_64BIT
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#endif
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#ifdef CONFIG_P1011RDB
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#define CONFIG_P1011
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#endif
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@ -123,6 +127,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP 1
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x1fffffff
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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@ -144,7 +153,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
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#else
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
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#endif
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/* CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
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/* CONFIG_SYS_IMMR */
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@ -197,13 +210,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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*/
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#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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@ -231,6 +248,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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#endif
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
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@ -242,10 +271,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#ifndef CONFIG_NAND_SPL
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#else
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#define CONFIG_SYS_NAND_BASE 0xfff00000
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#endif
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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@ -292,7 +331,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_VSC7385_BASE 0xffb00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
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#else
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#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
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#endif
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#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
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| BR_PS_8 | BR_V)
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@ -376,23 +419,41 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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/* controller 2, Slot 2, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_NAME "Slot 1"
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
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#else
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
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#endif
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, Slot 1, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_NAME "Slot 2"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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