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powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code

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Remove duplicated code in MPC8610HPCD board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2010-12-17 10:42:33 -06:00
parent 06eb4d8c68
commit b8526212ca
3 changed files with 19 additions and 65 deletions
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8
board/freescale/mpc8610hpcd/law.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008,2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -31,14 +31,8 @@ struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
#endif
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
};
int num_law_entries = ARRAY_SIZE(law_table);

72
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View file

@ -213,78 +213,34 @@ config_table:pci_mpc86xxcts_config_table
};
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif
#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
struct fsl_pci_info pci_info[3];
struct fsl_pci_info pci_info;
u32 devdisr, pordevsr;
int first_free_busno = 0;
int num = 0;
int pci_agent, pcie_ep, pcie_configured;
int first_free_busno;
int pci_agent;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
#ifdef CONFIG_PCIE1
pcie_configured = is_serdes_configured(PCIE1);
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf("PCIE1: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
#endif
#ifdef CONFIG_PCIE2
pcie_configured = is_serdes_configured(PCIE2);
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
printf("PCIE2: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
#endif
first_free_busno = fsl_pcie_init_board(0);
#ifdef CONFIG_PCI1
if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info[num], 1);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
SET_STD_PCI_INFO(pci_info, 1);
set_next_law(pci_info.mem_phys,
law_size_bits(pci_info.mem_size), pci_info.law);
set_next_law(pci_info.io_phys,
law_size_bits(pci_info.io_size), pci_info.law);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
printf("PCI: connected to PCI slots as %s" \
" (base address %lx)\n",
pci_agent ? "Agent" : "Host",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
pci_info.regs);
first_free_busno = fsl_pci_init_port(&pci_info,
&pci1_hose, first_free_busno);
} else {
printf("PCI: disabled\n");
@ -294,6 +250,8 @@ void pci_init_board(void)
#else
setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
#endif
fsl_pcie_init_board(first_free_busno);
}
#if defined(CONFIG_OF_BOARD_SETUP)

4
include/configs/MPC8610HPCD.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
* Copyright 2007, 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -276,6 +276,7 @@
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
/* controller 1, Base address 0xa000 */
#define CONFIG_SYS_PCIE1_NAME "ULI"
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
@ -284,6 +285,7 @@
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
/* controller 2, Base Address 0x9000 */
#define CONFIG_SYS_PCIE2_NAME "Slot 1"
#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */