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ppc/85xx: Fix compile err when PCI disabled on P1_P2_RDB
u-boot cannot be compiled after disabling CONFIG_PCI. Place PCI related codes under #ifdef CONFIG_PCI Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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768d5b2baf
commit
b707090432
3 changed files with 14 additions and 7 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -222,7 +222,9 @@ void ft_board_setup(void *blob, bd_t *bd)
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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#if defined(CONFIG_PCI)
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ft_pci_board_setup(blob);
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#endif /* #if defined(CONFIG_PCI) */
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_16M, 1),
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#if defined(CONFIG_PCI)
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@ -68,6 +69,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_256K, 1),
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#endif /* #if defined(CONFIG_PCI) */
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/* *I*G - NAND */
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@ -83,17 +83,23 @@
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
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#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
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#define CONFIG_PCI 1 /* Enable PCI/PCIE */
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#if defined(CONFIG_PCI)
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#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#endif /* #if defined(CONFIG_PCI) */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_PCI)
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#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
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#endif
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#ifndef __ASSEMBLY__
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extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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@ -364,6 +370,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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*/
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/* controller 2, Slot 2, tgtid 2, Base address 9000 */
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#if defined(CONFIG_PCI)
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#define CONFIG_SYS_PCIE2_NAME "Slot 1"
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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@ -385,8 +392,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#if defined(CONFIG_PCI)
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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@ -405,11 +410,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_TSEC1 1
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