U-Boot SPL binary does not read BIN header arguments, so passing some dummy
values 0000005b and 00000068 has no effect for U-Boot SPL code.
Probably these two values comes from old Marvell DDR training code which
was separated from U-Boot and used it for some configuration.
Seems that two 32-bit values were specified here to ensure SPL code
alignment to 128-bit boundary as it is required e.g. for A370 or AXP
processors. Main kwbimage header is 64-byte long which is aligned to
128-bit boundary. Optional kwbheader is 32-bit long, number of BIN header
arguments is stored in 32-bit number. So for alignment to 128-bit boundary
is needed 64-bit padding which exactly these two 32-bit dummy arguments
provided.
Now when mkimage correctly aligns start of executable code in BIN header to
128-bit boundary, there is no requirement to put dummy argument values into
kwbimage. So remove them.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Important detail is availability of kwbimage BIN header arguments passed
via r0 and r1 registers by BootROM.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
We can only select SPL_SKIP_LOWLEVEL_INIT if SPL is enabled, otherwise
we get a warning about unmet dependencies on platforms that don't use
SPL.
Fixes: cf47a8cf8f ("arm: mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BIT")
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Instead of declaring CONFIG_SPL_DRIVERS_MISC in board config header,
select it in Kconfig.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Instead of declaring CONFIG_SYS_MALLOC_SIMPLE dependant on
CONFIG_SPL_BUILD in board config header, select
CONFIG_SPL_SYS_MALLOC_SIMPLE in Kconfig.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Select SPL_SKIP_LOWLEVEL_INIT on 32bit Armada platforms via Kconfig,
as this was removed from mach/config.h in a2ac2b96 ("Convert
CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig").
Signed-off-by: Stefan Roese <sr@denx.de>
Fixes: a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig")
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Behún <kabel@kernel.org>
Cc: Pali Rohár <pali@kernel.org>
Tested-by: Pali Rohár <pali@kernel.org>
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Remove unused PCIe functions from SerDes code. They are unused and are
duplicated either from generic PCIe code or from pci_mvebu.c.
Remove also unused PCIe macros from SerDes code. They are just obfuscated
variants of standards macros in include/pci.h or in pci_mvebu.c.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
This code is trying to parse PCIe config space of PCIe card connected on
the other end of link and then is trying to force 5.0 GT/s speed via Target
Link Speed bits in PCIe Root Port Link Control 2 Register on the local part
of link if it sees that card supports 5.0 GT/s via Max Link Speed bits in
Link Capabilities Register.
The code is incorrect for more reasons:
- Accessing config space of an endpoint card cannot be done immediately.
If the PCIe link is not up, reading vendor/device ID registers will
return all ones.
- Parsing is incomplete, so it can cause issues even for working cards.
Moreover there is no need to force speed to 5.0 GT/s via Target Link Speed
bits on PCIe Root Port Link Control 2 Register. Hardware changes speed from
2.5 GT/s to 5.0 GT/s autonomously when it is supported.
Most importantly, this code does not change link speed at all, since
because after updating Target Link Speed bits on PCIe Root Port Link
Control 2 Register, it is required to retrain the link, and the code for
that is completely missing.
The code was probably needed for making buggy endpoint cards work. Such a
workaround, though, should be implemented via PCIe subsystem (via quirks,
for example), as buggy cards could also affect other PCIe controllers.
Note that this code is fully unrelated to a38x SerDes code and really
should not have been included in SerDes initialization. Usage of magic
constants without names and comments made this SerDes code hard to read and
understand.
Remove this PCIe application code from low level SerDes code. As this code
is configuring only 5.0 GT/s part, in the worst case, it could leave buggy
cards at the initial speed of 2.5 GT/s (if somehow before this change they
could have been "upgraded" to 5.0 GT/s speed even with missing link
retraining). Compliant cards which just need longer initialization should
work better after this change.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
PCI device ID is part of the PCIe controller SoC / revision. For Root
Complex mode (which is the default and the only mode supported currently
by U-Boot and Linux kernel), it is PCI device ID of PCIe Root Port device.
If there is some issue with this device ID, it should be set / updated by
PCIe controller driver (pci_mvebu.c), as this register resides in address
space of the controller. It shouldn't be done in SerDes initialization
code.
In the worst case (a specific board for example) it could be done via
U-Boot's weak function board_pex_config().
But it should not be overwritten globally for all A38x devices.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Enabling Common Clock Configuration bit in PCIe Root Port Link Control
Register should not be done unconditionally. It is enabled by operating
system as part of ASPM. Also after enabling Common Clock Configuration it
is required to do more work, like retraining link. Some cards may be broken
due to this incomplete Common Clock Configuration and some cards are broken
and do not support ASPM at all.
Remove this incomplete code for Common Clock Configuration. It really
should not be done in SerDes code as it is not related to SerDes, but to
PCIe subsystem.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Device/Port Type bits of PCIe Root Port PCI Express Capabilities Register
are read-only SAR registers and are initialized according to current mode
configured by PCIe controller. Changing PCIe controller mode (from Root
Complex mode to Endpoint mode or the other way) is possible via PCI
Express Control Register (offset 0x41A00), bit 1 (ConfRoot Complex). This
has to be done in PCIe controller driver (in our case pci_mvebu.c). Note
that default mode is Root Complex.
Maximum Link Speed bits of PCIe Root Port Link Capabilities Register are
platform specific and overwriting them does not make sense. They are set by
PCIe controller according to current SerDes configuration. For A38x it is
5.0 GT/s if SerDes supports appropriate speed.
Maximum Link Width bits of PCIe Root Port Link Capabilities Register are
read-only SAR registers, but unfortunately if this is not set correctly
here, then access PCI config space of the endpoint card behind this Root
Port does not work.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Add comments to understand what this magic code is doing.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
SoC Control 1 Register (offset 0x18204) is already defined by macro
SOC_CONTROL_REG1.
Use macro SOC_CONTROL_REG1 instead of macro SOC_CTRL_REG in ctrl_pex.c
code and remove the other definition.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Replace magic register offsets by macros to make code more readable.
Add comments about what this code is doing.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Rename these options so that CONFIG_IS_ENABLED can be used with them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Fixup some incorrect renames]
Signed-off-by: Tom Rini <trini@konsulko.com>
Move the function get_boot_device() from spl.c to cpu.c.
Make it visible, so that it may be used from other files.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
File mach/soc.h is included also in 64-bit mvebu processors, so define
Armada XP related macros only when compiling for Armada XP.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
default n/no doesn't need to be specified. It is default option anyway.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Rework FSP_USE_UPD portion]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SKIP_LOWLEVEL_INIT
CONFIG_SKIP_LOWLEVEL_INIT_ONLY
In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.
Signed-off-by: Tom Rini <trini@konsulko.com>
Move CONFIG_DDR_32BIT/64BIT to Kconfig as a choice for Armada XP
platforms. Make 64bit the default as this mirrors the current code.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
If ddr3_init() fails then DDR was not initialized and we cannot load and
execute U-Boot. We cannot continue, we cannot do anything in this case, so
hang.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This mvebu axp platform always uses fixed 250 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.
Now every #if-#else case of soc.h file defines CONFIG_SYS_TCLK, so remove
useless default CONFIG_SYS_TCLK value from the end of soc.h file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This mvebu msys platform always uses fixed 200 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Use CONFIG_PCI instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Correct macro usage)
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that proper load and execution addresses are set in v1 kwbimage we
can use it for loading and booting U-Boot proper.
Use the new spl_parse_board_header() function to implement parsing the
kwbimage v1 header. Use information from this header to locate offset and
size of the U-Boot proper binary, instead of using the legacy U-Boot
header which is prepended to the U-Boot proper binary stored at fixed
offset. This has the advantage that we do not need to relay on legacy
U-Boot header anymore and therefore U-Boot proper binary can be stored at
any offset, as is the case when loading & booting U-Boot proper by
BootROM. The CONFIG_SYS_U_BOOT_OFFS option is therefore not used by SPL
code anymore.
Also allow to compile U-Boot SPL without CONFIG_SPL_SPI_FLASH_SUPPORT,
CONFIG_SPL_MMC_SUPPORT or CONFIG_SPL_SATA_SUPPORT set. In this case
BootROM is used for loading and executing U-Boot proper. This reduces the
size of U-Boot's SPL image. By default these config options are enabled
and so BootROM loading is not used. In some cases BootROM reads from SPI
NOR at lower speed than U-Boot SPL. So people can decide whether they
want to have smaller SPL binary at the cost of slower boot.
Therefore dependency on CONFIG_SPL_DM_SPI, CONFIG_SPL_SPI_FLASH_SUPPORT,
CONFIG_SPL_SPI_LOAD, CONFIG_SPL_SPI_SUPPORT, CONFIG_SPL_DM_GPIO,
CONFIG_SPL_DM_MMC, CONFIG_SPL_GPIO_SUPPORT, CONFIG_SPL_LIBDISK_SUPPORT,
CONFIG_SPL_MMC_SUPPORT, CONFIG_SPL_SATA_SUPPORT and
CONFIG_SPL_LIBDISK_SUPPORT is changed from strict to related "imply"
(which can be selectivelly turned off and causes booting via BootROM).
Options CONFIG_SYS_SPI_U_BOOT_OFFS,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR and
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET have to to be set to
zero as they define the location where kwbimage header starts. It is the
location where BootROM expects start of the kwbimage from which it reads,
parses and executes SPL part. The same applies to option
CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR, which has to be set to one.
Update all config files to set correct values of these options and set
CONFIG_SYS_U_BOOT_OFFS to the correct value - the offset where U-Boot
proper starts.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Current code uses hack in board_init_f() which calls return_to_bootrom()
to skip U-Boot SPL code and return back to BootROM to load U-Boot via
UART or from NAND.
This change migrates that hack from the board_init_f() function and
changes it to return BOOT_DEVICE_BOOTROM instead of returning to BootROM
directly, so that U-Boot's SPL framework is used for returning to
BootROM.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
U-Boot's SPL framework already has an API for loading U-Boot via
BootROM.
Implement the function board_return_to_bootrom() for mvebu SPL code.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
This function does not return, so add the appropriate compiler flag.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Register r0 should be set to return value 0x0 - NO_ERR.
Set r0 with return value after all registers are restored from the
stack, so that the return value is always correct.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 944c7a3176 ("arm: mvebu: Add option to use UART xmodem protocol via kwboot")
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
If fixup offset is zero then there is nothing to fix. All calculation in
this case just increase addresses by value zero which results in identity.
So in this case skip whole fixup re-calculation as it is not needed.
This is just an optimization for special case when fix_offset is zero which
skips code path which does only identity operations (meaning nothing). No
functional changes.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Current version of this function uses a lot of incorrect assumptions about
the `ranges` DT property:
* parent(#address-cells) == 2
* #size-cells == 2
* number of entries == 2
* address size of first entry == 0x1000000
* second child address entry == base + 0x1000000
Trying to increase PCIe MEM space to more than 16 MiB leads to an overlap
with PCIe IO space, and trying to define additional MEM space (as a third
entry in the `ranges` DT property) causes U-Boot to crash when booting the
kernel.
## Flattened Device Tree blob at 04f00000
Booting using the fdt blob at 0x4f00000
Loading Device Tree to 000000001fb01000, end 000000001fb08f12 ... OK
ERROR: board-specific fdt fixup failed: <unknown error>
- must RESET the board to recover.
Fix a3700_fdt_fix_pcie_regions() to properly parse and update all addresses
in the `ranges` property according to
https://elinux.org/Device_Tree_Usage#PCI_Address_Translation
Now it is possible to increase PCIe MEM space from 16 MiB to maximal value
of 127 MiB.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Fixes: cb2ddb291e ("arm64: mvebu: a37xx: add device-tree fixer for PCIe regions")
Reviewed-by: Stefan Roese <sr@denx.de>
Find PCIe DT node by compatible string instead of retrieving it by using
hardcoded DT path.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit does the same thing as Linux commit 33def8498fdd.
Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.
Remove the quote operator # from compiler_attributes.h __section macro.
Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some of the setups including cn9130 opens mmio window starting from
0xc0000000, reflect it in the u-boot code.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
There is region left by ATF, which needs to remain in memory to provide RT
services. To prevent overwriting it by u-boot, do not provide any mapping
for this memory region, so any attempt to access it will trigger
synchronous exception.
Update sr 2021-04-12:
Don't update armada3700/cpu.c mmu table, as this has specific changes
included in mainline.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the base support for the Marvell Octeon TX2 CN9130 CRB.
Not all interfaces are supported fully yet.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Config option ARMADA_39X is never set so remove all dead code hidden under
ifdef CONFIG_ARMADA_39X blocks.
Also remove useless checks for CONFIG_ARMADA_38X define as this macro is
always defined for a38x code path.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this out of the common header and include it only where needed. In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly. Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Hardware testing of a board using the Armada 385 has shown that an
impedance threshold setting of 0x7 performs better in an eye-diagram
test than with Marvell's recommended value 0x6.
As other boards may still perform better with Marvell's reccomended value,
a configuration option is added with a default value of 0x6.
Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Reviewed-by: Stefan Roese <sr@denx.de>
This converts the following to Kconfig:
CONFIG_ENV_OVERWRITE
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Rerun migration, remove some comments]
Signed-off-by: Tom Rini <trini@konsulko.com>
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:
It's a **mistake** to use typedef for structures and pointers.
Besides, using typedef for structures is annoying when you try to make
headers self-contained.
Let's say you have the following function declaration in a header:
void foo(bd_t *bd);
This is not self-contained since bd_t is not defined.
To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>
#include <asm/u-boot.h>
void foo(bd_t *bd);
Then, the include direcective pulls in more bloat needlessly.
If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:
struct bd_info;
void foo(struct bd_info *bd);
Right, typedef'ing bd_t is a mistake.
I used coccinelle to generate this commit.
The semantic patch that makes this change is as follows:
<smpl>
@@
typedef bd_t;
@@
-bd_t
+struct bd_info
</smpl>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
When running USB compliance tests on our Armada-385 hardware platforms
we have seen some eye mask violations. Marvell's internal documentation
says: Based on silicon test results, it is recommended to change the
impedance calibration threshold setting to 0x6 prior to calibration.
Port changes from Marvell's u-boot fork[1] to address this.
[1] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/a6221551
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Convert the CRS305-1G-4S board to CRS3xx-98DX3236 to enable easier
implementation of new CRS3xx series boards, based on Marvell Prestera
98DX3236.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.
Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Have this symbol follow the pattern of all other such symbols.
This patch also removes a TODO from the code.
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Update mvebu SPL boot selection mechanism for the move to driver model
usage by ensuring that the required driver support for SPI and MMC
booting is available in SPL when the respective boot method is
selected.
Previously, all mvebu boards selected a boot method (implicitly
MVEBU_SPL_BOOT_DEVICE_SPI for many) even if SPL booting wasn't used.
This changes mvebu boot method selection to depend on SPL usage which
resolves the issue with aarch64 boards which don't use SPL getting an
implicit boot device selection resulting in unmet dependencies. The
32-bit arm boards do use SPL, but I'm led to conclude that most aren't
intentionally using the MVEBU_SPL_BOOT_DEVICE selection since none have
SPL_DM_SPI enabled in their defconfig even though they still implicitly
select the SPI boot method.
This also results in the new addition of SPL_GPIO_SUPPORT to helios4.
The mainline dts for helios4 includes the cd-gpios entry for sdhci with
identical addresses as the clearfog dts. I don't have a helios4 board
to confirm, but based on the current source conclude that the board
itself is either wired to pull the signal low for eMMC, or the default
MMC boot isn't fully functional in mainline. In either case, as far as
I can tell, including the GPIO support will at least cause no
regression.
Tested on SolidRun ClearFog devices.
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
In case when ARM Trusted Firmware changes the default address of PCIe
regions (which can be done for devices with 4 GB RAM to maximize the
amount of RAM the device can use) we add code that looks at how ATF
changed the PCIe windows in the CPU Address Decoder and changes given
device-tree blob accordingly.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Currently on Armada-37xx the mem_map structure is statically defined to
map first 2 GB of memory as RAM region, and system registers and PCIe
region device region.
This is insufficient for when there is more RAM or when for example the
PCIe windows is mapped to another address by the CPU Address Decoder.
In the case when the board has 4 GB RAM, on some boards the ARM Trusted
Firmware can move the PCIe window to another address, in order to
maximize possible usable RAM.
Also the dram_init and dram_init_banksize looks for information in
device-tree, and therefore different device trees are needed for boards
with different RAM sizes.
Therefore we add code that looks at how the ARM Trusted Firmware has
configured the CPU Address Decoder windows, and then we update the
mem_map structure and compute gd->ram_size and gd->bd->bi_dram bank
base addresses and sizes accordingly.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Move Armada-8k specific DRAM init code into armada-8k specific
directory.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Add a unique entry for ClearFog Base variant, reflected in the board
name and adjusted SerDes topology.
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Update the RTC (Read Timing Control) values for PCIe memory wrappers
following an ERRATA (ERRATA# TDB). This means the PCIe accesses will
used slower memory Read Timing, to allow more efficient energy
consumption, in order to lower the minimum VDD of the memory. Will lead
to more robust memory when voltage drop occurs (VDDSEG)
The code is based on changes from Marvell's U-Boot, specifically:
20cd270407eb608a7c8dc4af19ae2b
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.
Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Set the kernel device-tree file (fdtfile environment variable) based on
run-time detection of the platform.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
Move this function into init.h which seems to be designed for this sort
of thing. Also update the header to declare struct global_data so that it
can be included without global_data.h being needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.
Move them over.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
As mentioned in doc/README.arm-relocation gd->bd is not available in
dram_init() so we shouldn't attempt to access it.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
At present some boards generate kwbimage.cfg in the source tree
during the build. This breaks buildman testing on some systems
where the source tree is read-only. Update makefile rules to
generate it in the build tree instead.
Note some other boards have the kwbimage.cfg file written in
advance, hence we need check if the file exists in the build
tree first, otherwise we fall back to one in the source tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than
1600MHz. This reduces core voltage level from 1.25V to 1.15V, which
saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
Add the required Kconfig and macro definitions to allow boot from SATA
on Armada 38x systems.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
SPL does not initialize mbus_dram_info. Don't change the ahci mbus
settings of the ROM. This allows the ahci to work in SPL.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and
like some of the other similar boards requires bin_hdr.
bin_hdr (DDR3 init stage) is currently retrieved from the stock
bootloader and compiled into the kwb image.
Adds support for U-Boot, enable UART, SPI, Winbond SPI flash chip
support and writing env to SPI flash.
Signed-off-by: Luka Kovacic <me@lukakovacic.xyz>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
There is a Factory RESET button on the back side of the Turris Omnia
router. When user presses this button before powering the device up and
keeps it pressed, the microcontroller prevents the main CPU from booting
and counts how long the RESET button is being pressed (and indicates
this by lighting up front LEDs).
The idea behind this is that the user can boot the device into several
Factory RESET modes.
This patch adds support for U-Boot to read into which Factory RESET mode
the user booted the device. The value is an integer stored into the
omnia_reset environment variable. It is 0 if the button was not pressed
at all during power up, otherwise it is the number identifying the
Factory RESET mode.
This patch also changes bootcmd to a special hardcoded value if Factory
RESET button was pressed during device powerup. This special bootcmd
value sets the colors of all the LEDs on the front panel to green and
then tries to load the rescue image from the SPI flash memory and boot
it.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This driver is required for Turris Omnia to read ethernet addresses.
Move the dependency from turris_omnia_defconfig to Kconfig.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The I2C dependencies are defined in include/configs/turris_omnia.h,
because Turris Omnia won't boot correctly without I2C support.
Move these dependencies to Kconfig, so that they are selected if Turris
Omnia is selected as target.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The new DM implementation currently does not support the Sheeva
88SV331xV5 specific quirk present in the legacy implementation. The
legacy code is thus kept for this SoC and others not yet migrated to
DM_MMC.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Testing has shown that the current DM implementation of a platform /
board specific translation offset, as its needed for the SPL on MVEBU
platforms is buggy. The translation offset is confingured too late,
after the driver bind functions are run. This may result in incorrect
address translations. With the current implementation its not possible
to configure the offset earlier, as the DM code has not run at all.
This patch now removed the set_/get_translation_offset() calls and
moves the translation offset into the GD variable translation_offset.
This variable will get used when CONFIG_TRANSLATION_OFFSET is enabled.
This option is enabled only for MVEBU on ARM32 platforms, where its
currenty needed and configured in the SPL.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pierre Bourdon <delroth@gmail.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Pierre Bourdon <delroth@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
The DB-XC3-24G4XG is a switch development board from Marvell. It can
either use and external CPU card such as the db-88f6820-amc or the
internal CPU that is integrated into the switch.
Add support for running U-Boot on the internal CPU and enable the USB,
SPI and NAND peripherals. For now this needs the bin_hdr from the
Marvell U-Boot for this board.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
One difference with the integrated CPUs is that they use a different
clock control block to the Armada devices. Update mvebu_get_nand_clock()
accordingly.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
We now have MEVBU boards without SPL support (e.g. db-xc3-24g4xg).
Because of this, a new compile time warning from Kconfig is show:
WARNING: unmet direct dependencies detected for SPL_OF_CONTROL
Depends on [n]: SUPPORT_OF_CONTROL [=y] && SPL [=n] && OF_CONTROL [=y]
Selected by [y]:
- ARMADA_32BIT [=y] && ARM [=y] && ARCH_MVEBU [=y]
WARNING: unmet direct dependencies detected for SPL_DM
Depends on [n]: DM [=y] && SPL [=n]
Selected by [y]:
- ARMADA_32BIT [=y] && ARM [=y] && ARCH_MVEBU [=y]
...
This patch fixes this issue and removes these warnings.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
This patch enables the PCIe port specific link capabilities configuration
for Armada XP. The weak function board_sat_r_get() was used to return
a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This
is now changed with this patch to return a bit per PCIe port (4 bits
in this case, bit 0 for PCIe port 0, etc).
The theadorable board uses this new feature to configure PCIe port 0
as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards
using this function are not changed in the configuration and still
configure all ports as PCIe Gen2.
This patch also removes the parameter "pex_mode" from
board_serdes_cfg_get() as this parameter was not used in any of the
implementations.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
This allows the ahci_mvebu driver to do A38x platform specific
configuration at initialization.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The mvebu mbus code already had most of the support required for
kirkwood. The only difference is that unlike the other mvebu targets
kirkwood doesn't have a bridge control block so the code related to
managing that needs to be compiled out.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
