reset: Remove addr parameter from reset_cpu()

Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to.  This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value.  Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.

Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g.  COLD vs WARM resets).  As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).

To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely.  Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.

This transformation was done with the following coccinelle patch:

    @@
    expression argvalue;
    @@
    - reset_cpu(argvalue)
    + reset_cpu()

    @@
    identifier argname;
    type argtype;
    @@
    - reset_cpu(argtype argname)
    + reset_cpu(void)
    { ... }

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

arch/arc/lib/reset.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <cpu_func.h>
 
-__weak void reset_cpu(ulong addr)
+__weak void reset_cpu(void)
 {
 	/* Stop debug session here */
 	__builtin_arc_brk();
@@ -17,7 +17,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	printf("Resetting the board...\n");
 
-	reset_cpu(0);
+	reset_cpu();
 
 	return 0;
 }

arch/arm/cpu/arm920t/ep93xx/cpu.c

@@ -14,7 +14,7 @@
 #include <asm/io.h>
 
 /* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
-extern void reset_cpu(ulong addr)
+extern void reset_cpu(void)
 {
 	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
 	uint32_t value;

arch/arm/cpu/arm920t/imx/timer.c

@@ -81,7 +81,7 @@ ulong get_tbclk(void)
 /*
  * Reset the cpu by setting up the watchdog timer and let him time out
  */
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	/* Disable watchdog and set Time-Out field to 0 */
 	WCR = 0x00000000;

arch/arm/cpu/arm926ejs/armada100/timer.c

@@ -142,7 +142,7 @@ int timer_init(void)
  * 2. Write key value to TMP_WSAR reg.
  * 3. Perform write operation.
  */
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
 {
 	struct armd1mpmu_registers *mpmu =
 		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;

arch/arm/cpu/arm926ejs/mx25/reset.c

@@ -23,7 +23,7 @@
 /*
  * Reset the cpu by setting up the watchdog timer and let it time out
  */
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */

arch/arm/cpu/arm926ejs/mx27/reset.c

@@ -23,7 +23,7 @@
 /*
  * Reset the cpu by setting up the watchdog timer and let it time out
  */
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */

arch/arm/cpu/arm926ejs/mxs/mxs.c

@@ -32,9 +32,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 __weak void lowlevel_init(void) {}
 
-void reset_cpu(ulong ignored) __attribute__((noreturn));
+void reset_cpu(void) __attribute__((noreturn));
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	struct mxs_rtc_regs *rtc_regs =
 		(struct mxs_rtc_regs *)MXS_RTC_BASE;

arch/arm/cpu/arm926ejs/spear/reset.c

@@ -11,7 +11,7 @@
 #include <asm/arch/spr_syscntl.h>
 #include <linux/delay.h>
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	struct syscntl_regs *syscntl_regs_p =
 	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;

arch/arm/cpu/arm946es/cpu.c

@@ -56,7 +56,7 @@ static void cache_flush (void)
 
 #ifndef CONFIG_ARCH_INTEGRATOR
 
-__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+__attribute__((noreturn)) void reset_cpu(void)
 {
 	writew(0x0, 0xfffece10);
 	writew(0x8, 0xfffece10);

arch/arm/cpu/armv7/bcm281xx/reset.c

@@ -13,7 +13,7 @@
 #define CLKS_SHIFT	20		/* Clock period shift */
 #define LD_SHIFT	0		/* Reload value shift */
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	/*
 	 * Set WD enable, RST enable,

arch/arm/cpu/armv7/bcmcygnus/reset.c

@@ -10,7 +10,7 @@
 #define CRMU_MAIL_BOX1		0x03024028
 #define CRMU_SOFT_RESET_CMD	0xFFFFFFFF
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	/* Send soft reset command via Mailbox. */
 	writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1);

arch/arm/cpu/armv7/bcmnsp/reset.c

@@ -9,7 +9,7 @@
 
 #define CRU_RESET_OFFSET	0x1803F184
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	/* Reset the cpu by setting software reset request bit */
 	writel(0x1, CRU_RESET_OFFSET);

arch/arm/cpu/armv7/ls102xa/cpu.c

@@ -375,7 +375,7 @@ void smp_kick_all_cpus(void)
 }
 #endif
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 

arch/arm/cpu/armv7/s5p4418/cpu.c

@@ -88,7 +88,7 @@ int print_cpuinfo(void)
 }
 #endif
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
 	const u32 sw_rst_enb_bitpos = 3;

arch/arm/cpu/armv7/stv0991/reset.c

@@ -9,7 +9,7 @@
 #include <asm/io.h>
 #include <asm/arch/stv0991_wdru.h>
 #include <linux/delay.h>
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	puts("System is going to reboot ...\n");
 	/*

arch/arm/cpu/armv7m/cpu.c

@@ -47,7 +47,7 @@ int cleanup_before_linux(void)
 /*
  * Perform the low-level reset.
  */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	/*
 	 * Perform reset but keep priority group unchanged.

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1231,7 +1231,7 @@ int timer_init(void)
 
 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 
-void __efi_runtime reset_cpu(ulong addr)
+void __efi_runtime reset_cpu(void)
 {
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	/* clear the RST_REQ_MSK and SW_RST_REQ */
@@ -1260,7 +1260,7 @@ void __efi_runtime EFIAPI efi_reset_system(
 	case EFI_RESET_COLD:
 	case EFI_RESET_WARM:
 	case EFI_RESET_PLATFORM_SPECIFIC:
-		reset_cpu(0);
+		reset_cpu();
 		break;
 	case EFI_RESET_SHUTDOWN:
 		/* Nothing we can do */

arch/arm/cpu/armv8/s32v234/generic.c

@@ -319,7 +319,7 @@ static char *get_reset_cause(void)
 
 #define SRC_SCR_SW_RST					(1<<12)
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	printf("Feature not supported.\n");
 };

arch/arm/cpu/pxa/pxa2xx.c

@@ -267,9 +267,9 @@ void i2c_clk_enable(void)
 	writel(readl(CKEN) | CKEN14_I2C, CKEN);
 }
 
-void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
+void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	uint32_t tmp;
 

arch/arm/cpu/sa1100/cpu.c

@@ -55,7 +55,7 @@ static void cache_flush (void)
 #define RSRR	0x00
 #define RCSR	0x04
 
-__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+__attribute__((noreturn)) void reset_cpu(void)
 {
 	/* repeat endlessly */
 	while (1) {

arch/arm/lib/interrupts.c

@@ -53,7 +53,7 @@ int disable_interrupts(void)
 void bad_mode (void)
 {
 	panic ("Resetting CPU ...\n");
-	reset_cpu(0);
+	reset_cpu();
 }
 
 static void show_efi_loaded_images(struct pt_regs *regs)

arch/arm/lib/interrupts_m.c

@@ -59,7 +59,7 @@ void dump_regs(struct autosave_regs *regs)
 void bad_mode(void)
 {
 	panic("Resetting CPU ...\n");
-	reset_cpu(0);
+	reset_cpu();
 }
 
 void do_hard_fault(struct autosave_regs *autosave_regs)

arch/arm/lib/reset.c

@@ -39,7 +39,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	disable_interrupts();
 
 	reset_misc();
-	reset_cpu(0);
+	reset_cpu();
 
 	/*NOTREACHED*/
 	return 0;

arch/arm/mach-at91/arm920t/reset.c

@@ -24,7 +24,7 @@ void  __attribute__((weak)) board_reset(void)
 	/* true empty function for defining weak symbol */
 }
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
 

arch/arm/mach-at91/arm926ejs/reset.c

@@ -12,7 +12,7 @@
 #include <asm/arch/at91_rstc.h>
 
 /* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
 

arch/arm/mach-at91/armv7/reset.c

@@ -15,7 +15,7 @@
 #include <asm/arch/at91_rstc.h>
 
 /* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
 

arch/arm/mach-bcm283x/reset.c

@@ -48,7 +48,7 @@ __reset_cpu(struct bcm2835_wdog_regs *wdog_regs, ulong ticks)
 	writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc);
 }
 
-void reset_cpu(ulong ticks)
+void reset_cpu(void)
 {
 	struct bcm2835_wdog_regs *regs =
 		(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;

arch/arm/mach-davinci/reset.c

@@ -12,7 +12,7 @@
 #include <asm/arch/timer_defs.h>
 #include <asm/arch/hardware.h>
 
-void reset_cpu(unsigned long a)
+void reset_cpu(void)
 {
 	struct davinci_timer *const wdttimer =
 		(struct davinci_timer *)DAVINCI_WDOG_BASE;

arch/arm/mach-exynos/soc.c

@@ -20,7 +20,7 @@ extern void _main(void);
 void *secondary_boot_addr = (void *)_main;
 #endif /* CONFIG_TARGET_ESPRESSO7420 */
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 #ifdef CONFIG_CPU_V7A
 	writel(0x1, samsung_get_base_swreset());

arch/arm/mach-imx/imx8m/soc.c

@@ -910,7 +910,7 @@ usb_modify_speed:
 #endif
 
 #if !CONFIG_IS_ENABLED(SYSRESET)
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 

arch/arm/mach-imx/mx7ulp/soc.c

@@ -197,7 +197,7 @@ void s_init(void)
 #endif
 
 #ifndef CONFIG_ULP_WATCHDOG
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
 	while (1)

arch/arm/mach-k3/common.c

@@ -320,7 +320,7 @@ int fdt_disable_node(void *blob, char *node_path)
 #endif
 
 #ifndef CONFIG_SYSRESET
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 }
 #endif

arch/arm/mach-keystone/ddr3.c

@@ -345,7 +345,7 @@ void ddr3_check_ecc_int(u32 base)
 
 		if (!ecc_test) {
 			puts("Reseting the device ...\n");
-			reset_cpu(0);
+			reset_cpu();
 		}
 	}
 
@@ -445,7 +445,7 @@ void ddr3_err_reset_workaround(void)
 		tmp &= ~KS2_RSTYPE_PLL_SOFT;
 		__raw_writel(tmp, KS2_RSTCTRL_RSCFG);
 
-		reset_cpu(0);
+		reset_cpu();
 	}
 }
 #endif

arch/arm/mach-keystone/init.c

@@ -192,7 +192,7 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
 	u32 tmp;

arch/arm/mach-kirkwood/cpu.c

@@ -19,7 +19,7 @@
 #include <asm/arch/soc.h>
 #include <mvebu_mmc.h>
 
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
 {
 	struct kwcpu_registers *cpureg =
 	    (struct kwcpu_registers *)KW_CPU_REG_BASE;

arch/arm/mach-lpc32xx/cpu.c

@@ -17,7 +17,7 @@
 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
 static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	/* Enable watchdog clock */
 	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);

arch/arm/mach-mediatek/mt7622/init.c

@@ -27,7 +27,7 @@ int dram_init(void)
 
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

arch/arm/mach-mediatek/mt8512/init.c

@@ -43,7 +43,7 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	struct udevice *watchdog_dev = NULL;
 

arch/arm/mach-mediatek/mt8516/init.c

@@ -85,7 +85,7 @@ int mtk_soc_early_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

arch/arm/mach-mediatek/mt8518/init.c

@@ -42,7 +42,7 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

arch/arm/mach-meson/board-common.c

@@ -167,7 +167,7 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	struct pt_regs regs;
 
@@ -182,7 +182,7 @@ void reset_cpu(ulong addr)
 		;
 }
 #else
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

arch/arm/mach-mvebu/armada3700/cpu.c

@@ -314,7 +314,7 @@ int a3700_fdt_fix_pcie_regions(void *blob)
 	return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
 }
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	/*
 	 * Write magic number of 0x1d1e to North Bridge Warm Reset register

arch/arm/mach-mvebu/armada8k/cpu.c

@@ -104,7 +104,7 @@ void enable_caches(void)
 	dcache_enable();
 }
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	u32 reg;
 

arch/arm/mach-mvebu/cpu.c

@@ -42,7 +42,7 @@ void lowlevel_init(void)
 	 */
 }
 
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
 {
 	struct mvebu_system_registers *reg =
 		(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;

arch/arm/mach-octeontx/cpu.c

@@ -72,6 +72,6 @@ u64 get_page_table_size(void)
 	return 0x80000;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }

arch/arm/mach-octeontx2/cpu.c

@@ -68,6 +68,6 @@ u64 get_page_table_size(void)
 	return 0x80000;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }

arch/arm/mach-omap2/omap5/hwinit.c

@@ -417,7 +417,7 @@ void omap_die_id(unsigned int *die_id)
 	die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
 }
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 	u32 omap_rev = omap_revision();
 

arch/arm/mach-omap2/reset.c

@@ -14,7 +14,7 @@
 #include <asm/arch/cpu.h>
 #include <linux/compiler.h>
 
-void __weak reset_cpu(unsigned long ignored)
+void __weak reset_cpu(void)
 {
 	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
 }

arch/arm/mach-orion5x/cpu.c

@@ -20,7 +20,7 @@
 
 #define BUFLEN	16
 
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
 {
 	struct orion5x_cpu_registers *cpureg =
 	    (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;

arch/arm/mach-owl/soc.c

@@ -74,7 +74,7 @@ int board_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

arch/arm/mach-socfpga/include/mach/reset_manager.h

@@ -8,7 +8,7 @@
 
 phys_addr_t socfpga_get_rstmgr_addr(void);
 
-void reset_cpu(ulong addr);
+void reset_cpu(void);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);

arch/arm/mach-sunxi/board.c

@@ -338,7 +338,7 @@ void board_init_f(ulong dummy)
 }
 #endif
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
 	static const struct sunxi_wdog *wdog =

arch/arm/mach-tegra/cmd_enterrcm.c

@@ -40,7 +40,7 @@ static int do_enterrcm(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	tegra_pmc_writel(2, PMC_SCRATCH0);
 	disable_interrupts();
-	reset_cpu(0);
+	reset_cpu();
 
 	return 0;
 }

arch/arm/mach-tegra/pmc.c

@@ -85,7 +85,7 @@ void tegra_pmc_writel(u32 value, unsigned long offset)
 	writel(value, NV_PA_PMC_BASE + offset);
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	u32 value;
 

arch/arm/mach-uniphier/arm32/psci.c

@@ -158,5 +158,5 @@ s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
 
 void __secure psci_system_reset(void)
 {
-	reset_cpu(0);
+	reset_cpu();
 }

arch/arm/mach-uniphier/reset.c

@@ -18,7 +18,7 @@
 #define __SECURE
 #endif
 
-void __SECURE reset_cpu(unsigned long ignored)
+void __SECURE reset_cpu(void)
 {
 	u32 tmp;
 

arch/arm/mach-zynq/cpu.c

@@ -78,7 +78,7 @@ unsigned int zynq_get_silicon_version(void)
 						>> ZYNQ_SILICON_VER_SHIFT;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	zynq_slcr_cpu_reset();
 	while (1)

arch/arm/mach-zynqmp-r5/cpu.c

@@ -30,7 +30,7 @@ int arch_cpu_init(void)
 /*
  * Perform the low-level reset.
  */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	while (1)
 		;

arch/nds32/cpu/n1213/ag101/cpu.c

@@ -46,7 +46,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	/*
 	 * reset to the base addr of andesboot.
 	 * currently no ROM loader at addr 0.
-	 * do not use reset_cpu(0);
+	 * do not use reset_cpu();
 	 */
 #ifdef CONFIG_FTWDT010_WATCHDOG
 	/*

arch/nds32/lib/interrupts.c

@@ -66,7 +66,7 @@ int disable_interrupts(void)
 void bad_mode(void)
 {
 	panic("Resetting CPU ...\n");
-	reset_cpu(0);
+	reset_cpu();
 }
 
 void show_regs(struct pt_regs *regs)

arch/sandbox/cpu/sdl.c

@@ -69,14 +69,14 @@ static void sandbox_sdl_poll_events(void)
 	 * We don't want to include common.h in this file since it uses
 	 * system headers. So add a declation here.
 	 */
-	extern void reset_cpu(unsigned long addr);
+	extern void reset_cpu(void);
 	SDL_Event event;
 
 	while (SDL_PollEvent(&event)) {
 		switch (event.type) {
 		case SDL_QUIT:
 			puts("LCD window closed - quitting\n");
-			reset_cpu(1);
+			reset_cpu();
 			break;
 		}
 	}

arch/sh/cpu/sh4/cpu.c

@@ -32,7 +32,7 @@ int cleanup_before_linux (void)
 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	disable_interrupts();
-	reset_cpu(0);
+	reset_cpu();
 	return 0;
 }
 

arch/sh/cpu/sh4/watchdog.c

@@ -51,7 +51,7 @@ int watchdog_disable(void)
 }
 #endif
 
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
 {
 	/* Address error with SR.BL=1 first. */
 	trigger_address_error();

arch/x86/cpu/ivybridge/cpu.c

@@ -143,7 +143,7 @@ int checkcpu(void)
 
 		/* System is not happy after keyboard reset... */
 		debug("Issuing CF9 warm reset\n");
-		reset_cpu(0);
+		reset_cpu();
 	}
 
 	ret = cpu_common_init();

board/BuR/brppt2/board.c

@@ -540,7 +540,7 @@ void board_init_f(ulong dummy)
 	spl_dram_init();
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }
 #endif /* CONFIG_SPL_BUILD */

board/abilis/tb100/tb100.c

@@ -9,7 +9,7 @@
 #include <netdev.h>
 #include <asm/io.h>
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 #define CRM_SWRESET	0xff101044
 	writel(0x1, (void *)CRM_SWRESET);

board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c

@@ -115,7 +115,7 @@ int board_init(void)
 /*
  * Board specific reset that is system reset.
  */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	/* TODO */
 }

board/armltd/total_compute/total_compute.c

@@ -63,6 +63,6 @@ int dram_init_banksize(void)
 }
 
 /* Nothing to be done here as handled by PSCI interface */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }

board/armltd/vexpress/vexpress_common.c

@@ -174,7 +174,7 @@ int v2m_cfg_write(u32 devfn, u32 data)
 }
 
 /* Use the ARM Watchdog System to cause reset */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
 		printf("Unable to reboot\n");

board/armltd/vexpress64/vexpress64.c

@@ -143,7 +143,7 @@ void *board_fdt_blob_setup(void)
 #endif
 
 /* Actual reset is done via PSCI. */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }
 

board/atmark-techno/armadillo-800eva/armadillo-800eva.c

@@ -322,6 +322,6 @@ int board_late_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }

board/beacon/beacon-rzg2m/beacon-rzg2m.c

@@ -47,7 +47,7 @@ int dram_init_banksize(void)
 #define RST_CA57RESCNT	(RST_BASE + 0x40)
 #define RST_CODE	0xA5A5000F
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	writel(RST_CODE, RST_CA57RESCNT);
 }

board/bosch/shc/board.c

@@ -486,7 +486,7 @@ static void bosch_check_reset_pin(void)
 		printf("Resetting ...\n");
 		writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
 		disable_interrupts();
-		reset_cpu(0);
+		reset_cpu();
 		/*NOTREACHED*/
 	}
 }

board/broadcom/bcmns2/northstar2.c

@@ -57,7 +57,7 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

board/broadcom/bcmns3/ns3.c

@@ -185,7 +185,7 @@ ulong board_get_usable_ram_top(ulong total_size)
 	return BCM_NS3_MEM_END;
 }
 
-void reset_cpu(ulong level)
+void reset_cpu(void)
 {
 	/* Perform a level 3 reset */
 	psci_system_reset2(3, 0);

board/broadcom/bcmstb/bcmstb.c

@@ -43,7 +43,7 @@ u32 get_board_rev(void)
 	return 0;
 }
 
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
 {
 }
 

board/cavium/thunderx/thunderx.c

@@ -110,7 +110,7 @@ int dram_init(void)
 /*
  * Board specific reset that is system reset.
  */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }
 

board/compulab/cm_t335/spl.c

@@ -96,7 +96,7 @@ static void probe_sdram_size(long size)
 		break;
 	default:
 		puts("Failed configuring DRAM, resetting...\n\n");
-		reset_cpu(0);
+		reset_cpu();
 	}
 	debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
 	config_ddr(303, &ioregs, &ddr3_data,

board/cortina/presidio-asic/presidio.c

@@ -115,7 +115,7 @@ int dram_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
 }

board/freescale/imx8qm_mek/imx8qm_mek.c

@@ -105,7 +105,7 @@ int board_init(void)
 /*
  * Board specific reset that is system reset.
  */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	/* TODO */
 }

board/freescale/imx8qxp_mek/imx8qxp_mek.c

@@ -129,7 +129,7 @@ int board_init(void)
 /*
  * Board specific reset that is system reset.
  */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	/* TODO */
 }

board/freescale/mx6memcal/spl.c

@@ -425,7 +425,7 @@ void board_init_f(ulong dummy)
 		    is_cpu_type(MXC_CPU_MX6SL)) {
 			printf("cpu type 0x%x doesn't support 64-bit bus\n",
 			       get_cpu_type());
-			reset_cpu(0);
+			reset_cpu();
 		}
 	}
 #ifdef CONFIG_MX6SL

board/ge/b1x5v2/spl.c

@@ -436,7 +436,7 @@ static int get_boardmem_size(struct spi_flash *spi)
 	return 1024;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }
 

board/highbank/highbank.c

@@ -128,7 +128,7 @@ static int is_highbank(void)
 	return (midr & 0xfff0) == 0xc090;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
 	if (is_highbank())

board/hisilicon/hikey/hikey.c

@@ -486,7 +486,7 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	writel(0x48698284, &ao_sc->stat0);
 	wfi();

board/hisilicon/hikey960/hikey960.c

@@ -185,7 +185,7 @@ int board_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

board/hisilicon/poplar/poplar.c

@@ -60,7 +60,7 @@ int checkboard(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

board/kmc/kzm9g/kzm9g.c

@@ -366,7 +366,7 @@ int board_eth_init(struct bd_info *bis)
 	return ret;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	/* Soft Power On Reset */
 	writel((1 << 31), RESCNT2);

board/liebherr/display5/spl.c

@@ -376,7 +376,7 @@ void board_boot_order(u32 *spl_boot_list)
 #endif
 }
 
-void reset_cpu(ulong addr) {}
+void reset_cpu(void) {}
 
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)

board/phytium/durian/durian.c

@@ -42,7 +42,7 @@ int board_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	struct arm_smccc_res res;
 

board/qualcomm/dragonboard410c/dragonboard410c.c

@@ -203,7 +203,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

board/qualcomm/dragonboard820c/dragonboard820c.c

@@ -127,7 +127,7 @@ int board_init(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	psci_system_reset();
 }

board/renesas/alt/alt.c

@@ -111,7 +111,7 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	struct udevice *dev;
 	const u8 pmic_bus = 7;

board/renesas/alt/alt_spl.c

@@ -408,6 +408,6 @@ void board_boot_order(u32 *spl_boot_list)
 	spl_boot_list[2] = BOOT_DEVICE_NONE;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 }

board/renesas/blanche/blanche.c

@@ -360,7 +360,7 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	struct udevice *dev;
 	const u8 pmic_bus = 6;

board/renesas/condor/condor.c

@@ -34,7 +34,7 @@ int board_init(void)
 #define RST_CA57_CODE	0xA5A5000F
 #define RST_CA53_CODE	0x5A5A000F
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	unsigned long midr, cputype;
 

board/renesas/draak/draak.c

@@ -75,7 +75,7 @@ int board_init(void)
 #define RST_CA53RESCNT	(RST_BASE + 0x44)
 #define RST_CA53_CODE	0x5A5A000F
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	writel(RST_CA53_CODE, RST_CA53RESCNT);
 }

board/renesas/eagle/eagle.c

@@ -78,7 +78,7 @@ int board_init(void)
 #define RST_CA57_CODE	0xA5A5000F
 #define RST_CA53_CODE	0x5A5A000F
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	unsigned long midr, cputype;
 

board/renesas/ebisu/ebisu.c

@@ -42,7 +42,7 @@ int board_init(void)
 #define RST_CA53RESCNT	(RST_BASE + 0x44)
 #define RST_CA53_CODE	0x5A5A000F
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	writel(RST_CA53_CODE, RST_CA53RESCNT);
 }

board/renesas/gose/gose.c

@@ -117,7 +117,7 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
+void reset_cpu(void)
 {
 	struct udevice *dev;
 	const u8 pmic_bus = 6;