u-boot/arch/arm/mach-mvebu
Pali Rohár 177ee6c77e arm: mvebu: a38x: serdes: Don't configure PCIe cards in SerDes init code
This code is trying to parse PCIe config space of PCIe card connected on
the other end of link and then is trying to force 5.0 GT/s speed via Target
Link Speed bits in PCIe Root Port Link Control 2 Register on the local part
of link if it sees that card supports 5.0 GT/s via Max Link Speed bits in
Link Capabilities Register.

The code is incorrect for more reasons:
- Accessing config space of an endpoint card cannot be done immediately.
  If the PCIe link is not up, reading vendor/device ID registers will
  return all ones.
- Parsing is incomplete, so it can cause issues even for working cards.

Moreover there is no need to force speed to 5.0 GT/s via Target Link Speed
bits on PCIe Root Port Link Control 2 Register. Hardware changes speed from
2.5 GT/s to 5.0 GT/s autonomously when it is supported.

Most importantly, this code does not change link speed at all, since
because after updating Target Link Speed bits on PCIe Root Port Link
Control 2 Register, it is required to retrain the link, and the code for
that is completely missing.

The code was probably needed for making buggy endpoint cards work. Such a
workaround, though, should be implemented via PCIe subsystem (via quirks,
for example), as buggy cards could also affect other PCIe controllers.

Note that this code is fully unrelated to a38x SerDes code and really
should not have been included in SerDes initialization. Usage of magic
constants without names and comments made this SerDes code hard to read and
understand.

Remove this PCIe application code from low level SerDes code. As this code
is configuring only 5.0 GT/s part, in the worst case, it could leave buggy
cards at the initial speed of 2.5 GT/s (if somehow before this change they
could have been "upgraded" to 5.0 GT/s speed even with missing link
retraining). Compliant cards which just need longer initialization should
work better after this change.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
..
armada8k arm64: mvebu: extend the mmio region 2021-05-16 06:48:45 +02:00
armada3700 arm: a37xx: pci: Optimize a3700_fdt_fix_pcie_regions() when fixup offset is zero 2021-07-15 10:53:05 +02:00
include/mach Prepare v2021.10-rc4 2021-09-16 10:29:40 -04:00
serdes arm: mvebu: a38x: serdes: Don't configure PCIe cards in SerDes init code 2021-10-08 08:33:52 +02:00
.gitignore mvebu: select boot device at SoC level 2018-08-06 14:07:23 +02:00
arm64-common.c pci: arm: mvebu: Drop DM_PCI check from arch_early_init_r 2021-08-06 08:20:45 -04:00
cpu.c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell 2021-09-01 10:11:21 -04:00
dram.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
efuse.c common: Drop linux/bitops.h from common header 2020-05-18 21:19:23 -04:00
gpio.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
Kconfig sata: Rename SATA_SUPPORT to SATA 2021-09-04 12:26:02 -04:00
kwbimage.cfg.in mvebu: select boot device at SoC level 2018-08-06 14:07:23 +02:00
lowlevel_spl.S arm: mvebu: Fix return_to_bootrom() 2021-07-31 09:49:32 +02:00
Makefile rename symbol: CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD 2020-05-15 14:47:35 -04:00
mbus.c treewide: Convert macro and uses of __section(foo) to __section("foo") 2021-05-24 14:21:30 -04:00
spl.c Prepare v2021.10-rc4 2021-09-16 10:29:40 -04:00
timer.c treewide: Convert macro and uses of __section(foo) to __section("foo") 2021-05-24 14:21:30 -04:00