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Prepare v2021.04-rc4

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Merge tag 'v2021.04-rc4' into next

Prepare v2021.04-rc4
This commit is contained in:
Tom Rini 2021-03-15 12:15:38 -04:00
commit 22fc991daf
313 changed files with 13482 additions and 2308 deletions
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2
.azure-pipelines.yml
View file

@ -148,7 +148,7 @@ jobs:
export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
./tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
./tools/buildman/buildman -t
./tools/dtoc/dtoc -t

2
.gitlab-ci.yml
View file

@ -168,7 +168,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
./tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl;
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;

4
MAINTAINERS
View file

@ -160,7 +160,7 @@ F: drivers/clk/aspeed/
F: drivers/pinctrl/aspeed/
N: aspeed
ARM BROADCOM BCM283X
ARM BROADCOM BCM283X / BCM27XX
M: Matthias Brugger <mbrugger@suse.com>
S: Maintained
F: arch/arm/dts/bcm283*
@ -175,6 +175,8 @@ F: drivers/video/bcm2835.c
F: include/dm/platform_data/serial_bcm283x_mu.h
F: include/dt-bindings/pinctrl/bcm2835.h
F: drivers/pinctrl/broadcom/
F: configs/rpi_*
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
ARM BROADCOM BCMSTB
M: Thomas Fitzsimmons <fitzsim@fitzsim.org>

19
Makefile
View file

@ -3,7 +3,7 @@
VERSION = 2021
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@ -792,6 +792,7 @@ libs-y += drivers/usb/dwc3/
libs-y += drivers/usb/common/
libs-y += drivers/usb/emul/
libs-y += drivers/usb/eth/
libs-$(CONFIG_USB_DEVICE) += drivers/usb/gadget/
libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
libs-y += drivers/usb/host/
@ -1263,11 +1264,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
spl/u-boot-spl.hex: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
@ -1548,7 +1544,10 @@ flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
endif
endif
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
u-boot.uim: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
@ -1937,6 +1936,12 @@ spl/u-boot-spl.bin: spl/u-boot-spl
@:
$(SPL_SIZE_CHECK)
spl/u-boot-spl-dtb.bin: spl/u-boot-spl
@:
spl/u-boot-spl-dtb.hex: spl/u-boot-spl
@:
spl/u-boot-spl: tools prepare \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)

6
arch/arm/Kconfig
View file

@ -970,7 +970,7 @@ config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
select ARM64 if TARGET_SOCFPGA_SOC64
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
@ -982,7 +982,7 @@ config ARCH_SOCFPGA
select SPL_LIBGENERIC_SUPPORT
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
select SPL_SERIAL_SUPPORT
select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT
@ -991,7 +991,7 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY

10
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -640,3 +640,13 @@ config HAS_FSL_XHCI_USB
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.
config SYS_FSL_BOOTROM_BASE
hex
depends on FSL_LSCH2
default 0
config SYS_FSL_BOOTROM_SIZE
hex
depends on FSL_LSCH2
default 0x1000000

11
arch/arm/dts/Makefile
View file

@ -648,10 +648,17 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-pcm052.dtb \
vf610-bk4r1.dtb
dtb-$(CONFIG_MX23) += \
imx23-evk.dtb
dtb-$(CONFIG_MX28) += \
imx28-xea.dtb
dtb-$(CONFIG_MX51) += \
imx51-babbage.dtb
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
imx53-qsb.dtb \
imx53-kp.dtb \
imx53-m53menlo.dtb
@ -783,6 +790,10 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
imx8mm-venice-gw73xx-0x.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \

2
arch/arm/dts/fsl-imx8qm-apalis.dts
View file

@ -503,7 +503,7 @@
pinctrl-0 = <&pinctrl_fec1>;
fsl,magic-packet;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 11 1>;
status = "okay";

2
arch/arm/dts/fsl-imx8qxp-apalis.dts
View file

@ -229,7 +229,7 @@
pinctrl-0 = <&pinctrl_fec1>;
fsl,magic-packet;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-post-delay = <150>;
phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/imx23-evk-u-boot.dtsi Normal file
View file

@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
#include "imx23-u-boot.dtsi"

145
arch/arm/dts/imx23-evk.dts Normal file
View file

@ -0,0 +1,145 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx23.dtsi"
/ {
model = "Freescale i.MX23 Evaluation Kit";
compatible = "fsl,imx23-evk", "fsl,imx23";
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x08000000>;
};
reg_vddio_sd0: regulator-vddio-sd0 {
compatible = "regulator-fixed";
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 29 0>;
};
reg_lcd_3v3: regulator-lcd-3v3 {
compatible = "regulator-fixed";
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 18 0>;
enable-active-high;
};
reg_lcd_5v: regulator-lcd-5v {
compatible = "regulator-fixed";
regulator-name = "lcd-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
panel {
compatible = "sii,43wvf1g";
backlight = <&backlight_display>;
dvdd-supply = <&reg_lcd_3v3>;
avdd-supply = <&reg_lcd_5v>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
apb@80000000 {
apbh@80000000 {
nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
status = "okay";
};
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
bus-width = <4>;
wp-gpios = <&gpio1 30 0>;
vmmc-supply = <&reg_vddio_sd0>;
status = "okay";
};
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_LCD_RESET__GPIO_1_18
MX23_PAD_PWM3__GPIO_1_29
MX23_PAD_PWM4__GPIO_1_30
MX23_PAD_SSP1_DETECT__SSP1_DETECT
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a>;
status = "okay";
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
apbx@80040000 {
lradc@80050000 {
status = "okay";
fsl,lradc-touchscreen-wires = <4>;
};
pwm: pwm@80064000 {
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pins_a>;
status = "okay";
};
auart0: serial@8006c000 {
pinctrl-names = "default";
pinctrl-0 = <&auart0_pins_a>;
status = "okay";
};
duart: serial@80070000 {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
usbphy0: usbphy@8007c000 {
status = "okay";
};
};
};
ahb@80080000 {
usb0: usb@80080000 {
status = "okay";
};
};
backlight_display: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 2 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};

333
arch/arm/dts/imx23-pinfunc.h Normal file
View file

@ -0,0 +1,333 @@
/*
* Header providing constants for i.MX23 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
#define __DT_BINDINGS_MX23_PINCTRL_H__
#include "mxs-pinfunc.h"
#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
#define MX23_PAD_LCD_D00__LCD_D00 0x1000
#define MX23_PAD_LCD_D01__LCD_D01 0x1010
#define MX23_PAD_LCD_D02__LCD_D02 0x1020
#define MX23_PAD_LCD_D03__LCD_D03 0x1030
#define MX23_PAD_LCD_D04__LCD_D04 0x1040
#define MX23_PAD_LCD_D05__LCD_D05 0x1050
#define MX23_PAD_LCD_D06__LCD_D06 0x1060
#define MX23_PAD_LCD_D07__LCD_D07 0x1070
#define MX23_PAD_LCD_D08__LCD_D08 0x1080
#define MX23_PAD_LCD_D09__LCD_D09 0x1090
#define MX23_PAD_LCD_D10__LCD_D10 0x10a0
#define MX23_PAD_LCD_D11__LCD_D11 0x10b0
#define MX23_PAD_LCD_D12__LCD_D12 0x10c0
#define MX23_PAD_LCD_D13__LCD_D13 0x10d0
#define MX23_PAD_LCD_D14__LCD_D14 0x10e0
#define MX23_PAD_LCD_D15__LCD_D15 0x10f0
#define MX23_PAD_LCD_D16__LCD_D16 0x1100
#define MX23_PAD_LCD_D17__LCD_D17 0x1110
#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120
#define MX23_PAD_LCD_RS__LCD_RS 0x1130
#define MX23_PAD_LCD_WR__LCD_WR 0x1140
#define MX23_PAD_LCD_CS__LCD_CS 0x1150
#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
#define MX23_PAD_PWM0__PWM0 0x11a0
#define MX23_PAD_PWM1__PWM1 0x11b0
#define MX23_PAD_PWM2__PWM2 0x11c0
#define MX23_PAD_PWM3__PWM3 0x11d0
#define MX23_PAD_PWM4__PWM4 0x11e0
#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
#define MX23_PAD_ROTARYA__ROTARYA 0x2070
#define MX23_PAD_ROTARYB__ROTARYB 0x2080
#define MX23_PAD_EMI_A00__EMI_A00 0x2090
#define MX23_PAD_EMI_A01__EMI_A01 0x20a0
#define MX23_PAD_EMI_A02__EMI_A02 0x20b0
#define MX23_PAD_EMI_A03__EMI_A03 0x20c0
#define MX23_PAD_EMI_A04__EMI_A04 0x20d0
#define MX23_PAD_EMI_A05__EMI_A05 0x20e0
#define MX23_PAD_EMI_A06__EMI_A06 0x20f0
#define MX23_PAD_EMI_A07__EMI_A07 0x2100
#define MX23_PAD_EMI_A08__EMI_A08 0x2110
#define MX23_PAD_EMI_A09__EMI_A09 0x2120
#define MX23_PAD_EMI_A10__EMI_A10 0x2130
#define MX23_PAD_EMI_A11__EMI_A11 0x2140
#define MX23_PAD_EMI_A12__EMI_A12 0x2150
#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160
#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170
#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180
#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
#define MX23_PAD_EMI_D00__EMI_D00 0x3000
#define MX23_PAD_EMI_D01__EMI_D01 0x3010
#define MX23_PAD_EMI_D02__EMI_D02 0x3020
#define MX23_PAD_EMI_D03__EMI_D03 0x3030
#define MX23_PAD_EMI_D04__EMI_D04 0x3040
#define MX23_PAD_EMI_D05__EMI_D05 0x3050
#define MX23_PAD_EMI_D06__EMI_D06 0x3060
#define MX23_PAD_EMI_D07__EMI_D07 0x3070
#define MX23_PAD_EMI_D08__EMI_D08 0x3080
#define MX23_PAD_EMI_D09__EMI_D09 0x3090
#define MX23_PAD_EMI_D10__EMI_D10 0x30a0
#define MX23_PAD_EMI_D11__EMI_D11 0x30b0
#define MX23_PAD_EMI_D12__EMI_D12 0x30c0
#define MX23_PAD_EMI_D13__EMI_D13 0x30d0
#define MX23_PAD_EMI_D14__EMI_D14 0x30e0
#define MX23_PAD_EMI_D15__EMI_D15 0x30f0
#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140
#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
#define MX23_PAD_GPMI_D00__LCD_D8 0x0001
#define MX23_PAD_GPMI_D01__LCD_D9 0x0011
#define MX23_PAD_GPMI_D02__LCD_D10 0x0021
#define MX23_PAD_GPMI_D03__LCD_D11 0x0031
#define MX23_PAD_GPMI_D04__LCD_D12 0x0041
#define MX23_PAD_GPMI_D05__LCD_D13 0x0051
#define MX23_PAD_GPMI_D06__LCD_D14 0x0061
#define MX23_PAD_GPMI_D07__LCD_D15 0x0071
#define MX23_PAD_GPMI_D08__LCD_D18 0x0081
#define MX23_PAD_GPMI_D09__LCD_D19 0x0091
#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1
#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1
#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1
#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1
#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101
#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111
#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
#define MX23_PAD_AUART1_RX__IR_RX 0x01c1
#define MX23_PAD_AUART1_TX__IR_TX 0x01d1
#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
#define MX23_PAD_LCD_D00__ETM_DA8 0x1001
#define MX23_PAD_LCD_D01__ETM_DA9 0x1011
#define MX23_PAD_LCD_D02__ETM_DA10 0x1021
#define MX23_PAD_LCD_D03__ETM_DA11 0x1031
#define MX23_PAD_LCD_D04__ETM_DA12 0x1041
#define MX23_PAD_LCD_D05__ETM_DA13 0x1051
#define MX23_PAD_LCD_D06__ETM_DA14 0x1061
#define MX23_PAD_LCD_D07__ETM_DA15 0x1071
#define MX23_PAD_LCD_D08__ETM_DA0 0x1081
#define MX23_PAD_LCD_D09__ETM_DA1 0x1091
#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1
#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1
#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1
#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1
#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1
#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1
#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131
#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
#define MX23_PAD_PWM0__ROTARYA 0x11a1
#define MX23_PAD_PWM1__ROTARYB 0x11b1
#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1
#define MX23_PAD_PWM3__ETM_TCTL 0x11d1
#define MX23_PAD_PWM4__ETM_TCLK 0x11e1
#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071
#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081
#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
#define MX23_PAD_PWM0__DUART_RX 0x11a2
#define MX23_PAD_PWM1__DUART_TX 0x11b2
#define MX23_PAD_PWM3__AUART1_CTS 0x11d2
#define MX23_PAD_PWM4__AUART1_RTS 0x11e2
#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
#define MX23_PAD_ROTARYA__SPDIF 0x2072
#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003
#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013
#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023
#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033
#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043
#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053
#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063
#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073
#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083
#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093
#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103
#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113
#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133
#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143
#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153
#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
#define MX23_PAD_PWM0__GPIO_1_26 0x11a3
#define MX23_PAD_PWM1__GPIO_1_27 0x11b3
#define MX23_PAD_PWM2__GPIO_1_28 0x11c3
#define MX23_PAD_PWM3__GPIO_1_29 0x11d3
#define MX23_PAD_PWM4__GPIO_1_30 0x11e3
#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073
#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083
#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093
#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103
#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113
#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123
#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133
#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143
#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153
#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */

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arch/arm/dts/imx23-u-boot.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
&gpio0 {
gpio-ranges = <&pinctrl 0 0 32>;
};
&gpio1 {
gpio-ranges = <&pinctrl 0 32 31>;
};
&gpio2 {
gpio-ranges = <&pinctrl 0 63 32>;
};

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arch/arm/dts/imx23.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
#include "imx23-pinfunc.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&icoll>;
/*
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
*/
chosen {};
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
serial0 = &auart0;
serial1 = &auart1;
spi0 = &ssp0;
spi1 = &ssp1;
usbphy0 = &usbphy0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
reg = <0>;
};
};
apb@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x80000>;
ranges;
apbh@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x40000>;
ranges;
icoll: interrupt-controller@80000000 {
compatible = "fsl,imx23-icoll", "fsl,icoll";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x80000000 0x2000>;
};
dma_apbh: dma-apbh@80004000 {
compatible = "fsl,imx23-dma-apbh";
reg = <0x80004000 0x2000>;
interrupts = <0 14 20 0
13 13 13 13>;
interrupt-names = "empty", "ssp0", "ssp1", "empty",
"gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <8>;
clocks = <&clks 15>;
};
ecc@80008000 {
reg = <0x80008000 0x2000>;
status = "disabled";
};
nand-controller@8000c000 {
compatible = "fsl,imx23-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <56>;
interrupt-names = "bch";
clocks = <&clks 34>;
clock-names = "gpmi_io";
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
status = "disabled";
};
ssp0: spi@80010000 {
reg = <0x80010000 0x2000>;
interrupts = <15>;
clocks = <&clks 33>;
dmas = <&dma_apbh 1>;
dma-names = "rx-tx";
status = "disabled";
};
etm@80014000 {
reg = <0x80014000 0x2000>;
status = "disabled";
};
pinctrl: pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-pinctrl", "simple-bus";
reg = <0x80018000 0x2000>;
gpio0: gpio@0 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
reg = <0>;
interrupts = <16>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@1 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
reg = <1>;
interrupts = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
reg = <2>;
interrupts = <18>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
duart_pins_a: duart@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_PWM0__DUART_RX
MX23_PAD_PWM1__DUART_TX
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
auart0_pins_a: auart0@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_AUART1_RX__AUART1_RX
MX23_PAD_AUART1_TX__AUART1_TX
MX23_PAD_AUART1_CTS__AUART1_CTS
MX23_PAD_AUART1_RTS__AUART1_RTS
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
auart0_2pins_a: auart0-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_I2C_SCL__AUART1_TX
MX23_PAD_I2C_SDA__AUART1_RX
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
auart1_2pins_a: auart1-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_D14__AUART2_RX
MX23_PAD_GPMI_D15__AUART2_TX
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
gpmi_pins_a: gpmi-nand@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__GPMI_D00
MX23_PAD_GPMI_D01__GPMI_D01
MX23_PAD_GPMI_D02__GPMI_D02
MX23_PAD_GPMI_D03__GPMI_D03
MX23_PAD_GPMI_D04__GPMI_D04
MX23_PAD_GPMI_D05__GPMI_D05
MX23_PAD_GPMI_D06__GPMI_D06
MX23_PAD_GPMI_D07__GPMI_D07
MX23_PAD_GPMI_CLE__GPMI_CLE
MX23_PAD_GPMI_ALE__GPMI_ALE
MX23_PAD_GPMI_RDY0__GPMI_RDY0
MX23_PAD_GPMI_RDY1__GPMI_RDY1
MX23_PAD_GPMI_WPN__GPMI_WPN
MX23_PAD_GPMI_WRN__GPMI_WRN
MX23_PAD_GPMI_RDN__GPMI_RDN
MX23_PAD_GPMI_CE1N__GPMI_CE1N
MX23_PAD_GPMI_CE0N__GPMI_CE0N
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
gpmi_pins_fixup: gpmi-pins-fixup@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_WPN__GPMI_WPN
MX23_PAD_GPMI_WRN__GPMI_WRN
MX23_PAD_GPMI_RDN__GPMI_RDN
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
};
mmc0_4bit_pins_a: mmc0-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA0__SSP1_DATA0
MX23_PAD_SSP1_DATA1__SSP1_DATA1
MX23_PAD_SSP1_DATA2__SSP1_DATA2
MX23_PAD_SSP1_DATA3__SSP1_DATA3
MX23_PAD_SSP1_CMD__SSP1_CMD
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc0_8bit_pins_a: mmc0-8bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA0__SSP1_DATA0
MX23_PAD_SSP1_DATA1__SSP1_DATA1
MX23_PAD_SSP1_DATA2__SSP1_DATA2
MX23_PAD_SSP1_DATA3__SSP1_DATA3
MX23_PAD_GPMI_D08__SSP1_DATA4
MX23_PAD_GPMI_D09__SSP1_DATA5
MX23_PAD_GPMI_D10__SSP1_DATA6
MX23_PAD_GPMI_D11__SSP1_DATA7
MX23_PAD_SSP1_CMD__SSP1_CMD
MX23_PAD_SSP1_DETECT__SSP1_DETECT
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc0_pins_fixup: mmc0-pins-fixup@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DETECT__SSP1_DETECT
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc0_sck_cfg: mmc0-sck-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc1_4bit_pins_a: mmc1-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__SSP2_DATA0
MX23_PAD_GPMI_D01__SSP2_DATA1
MX23_PAD_GPMI_D02__SSP2_DATA2
MX23_PAD_GPMI_D03__SSP2_DATA3
MX23_PAD_GPMI_RDY1__SSP2_CMD
MX23_PAD_GPMI_WRN__SSP2_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc1_8bit_pins_a: mmc1-8bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__SSP2_DATA0
MX23_PAD_GPMI_D01__SSP2_DATA1
MX23_PAD_GPMI_D02__SSP2_DATA2
MX23_PAD_GPMI_D03__SSP2_DATA3
MX23_PAD_GPMI_D04__SSP2_DATA4
MX23_PAD_GPMI_D05__SSP2_DATA5
MX23_PAD_GPMI_D06__SSP2_DATA6
MX23_PAD_GPMI_D07__SSP2_DATA7
MX23_PAD_GPMI_RDY1__SSP2_CMD
MX23_PAD_GPMI_WRN__SSP2_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
pwm2_pins_a: pwm2@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_PWM2__PWM2
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
lcdif_24bit_pins_a: lcdif-24bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_LCD_D00__LCD_D00
MX23_PAD_LCD_D01__LCD_D01
MX23_PAD_LCD_D02__LCD_D02
MX23_PAD_LCD_D03__LCD_D03
MX23_PAD_LCD_D04__LCD_D04
MX23_PAD_LCD_D05__LCD_D05
MX23_PAD_LCD_D06__LCD_D06
MX23_PAD_LCD_D07__LCD_D07
MX23_PAD_LCD_D08__LCD_D08
MX23_PAD_LCD_D09__LCD_D09
MX23_PAD_LCD_D10__LCD_D10
MX23_PAD_LCD_D11__LCD_D11
MX23_PAD_LCD_D12__LCD_D12
MX23_PAD_LCD_D13__LCD_D13
MX23_PAD_LCD_D14__LCD_D14
MX23_PAD_LCD_D15__LCD_D15
MX23_PAD_LCD_D16__LCD_D16
MX23_PAD_LCD_D17__LCD_D17
MX23_PAD_GPMI_D08__LCD_D18
MX23_PAD_GPMI_D09__LCD_D19
MX23_PAD_GPMI_D10__LCD_D20
MX23_PAD_GPMI_D11__LCD_D21
MX23_PAD_GPMI_D12__LCD_D22
MX23_PAD_GPMI_D13__LCD_D23
MX23_PAD_LCD_DOTCK__LCD_DOTCK
MX23_PAD_LCD_ENABLE__LCD_ENABLE
MX23_PAD_LCD_HSYNC__LCD_HSYNC
MX23_PAD_LCD_VSYNC__LCD_VSYNC
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
spi2_pins_a: spi2@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_WRN__SSP2_SCK
MX23_PAD_GPMI_RDY1__SSP2_CMD
MX23_PAD_GPMI_D00__SSP2_DATA0
MX23_PAD_GPMI_D03__SSP2_DATA3
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
i2c_pins_a: i2c@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_I2C_SCL__I2C_SCL
MX23_PAD_I2C_SDA__I2C_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
i2c_pins_b: i2c@1 {
reg = <1>;
fsl,pinmux-ids = <
MX23_PAD_LCD_ENABLE__I2C_SCL
MX23_PAD_LCD_HSYNC__I2C_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
i2c_pins_c: i2c@2 {
reg = <2>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA1__I2C_SCL
MX23_PAD_SSP1_DATA2__I2C_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
};
digctl@8001c000 {
compatible = "fsl,imx23-digctl";
reg = <0x8001c000 2000>;
status = "disabled";
};
emi@80020000 {
reg = <0x80020000 0x2000>;
status = "disabled";
};
dma_apbx: dma-apbx@80024000 {
compatible = "fsl,imx23-dma-apbx";
reg = <0x80024000 0x2000>;
interrupts = <7 5 9 26
19 0 25 23
60 58 9 0
0 0 0 0>;
interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
"saif0", "empty", "auart0-rx", "auart0-tx",
"auart1-rx", "auart1-tx", "saif1", "empty",
"empty", "empty", "empty", "empty";
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 16>;
};
dcp: crypto@80028000 {
compatible = "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <53 54>;
status = "okay";
};
pxp@8002a000 {
reg = <0x8002a000 0x2000>;
status = "disabled";
};
efuse@8002c000 {
compatible = "fsl,imx23-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x8002c000 0x2000>;
clocks = <&clks 15>;
};
axi-ahb@8002e000 {
reg = <0x8002e000 0x2000>;
status = "disabled";
};
lcdif@80030000 {
compatible = "fsl,imx23-lcdif";
reg = <0x80030000 2000>;
interrupts = <46 45>;
clocks = <&clks 38>;
status = "disabled";
};
ssp1: spi@80034000 {
reg = <0x80034000 0x2000>;
interrupts = <2>;
clocks = <&clks 33>;
dmas = <&dma_apbh 2>;
dma-names = "rx-tx";
status = "disabled";
};
tvenc@80038000 {
reg = <0x80038000 0x2000>;
status = "disabled";
};
};
apbx@80040000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80040000 0x40000>;
ranges;
clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
saif0: saif@80042000 {
reg = <0x80042000 0x2000>;
dmas = <&dma_apbx 4>;
dma-names = "rx-tx";
status = "disabled";
};
power@80044000 {
reg = <0x80044000 0x2000>;
status = "disabled";
};
saif1: saif@80046000 {
reg = <0x80046000 0x2000>;
dmas = <&dma_apbx 10>;
dma-names = "rx-tx";
status = "disabled";
};
audio-out@80048000 {
reg = <0x80048000 0x2000>;
dmas = <&dma_apbx 1>;
dma-names = "tx";
status = "disabled";
};
audio-in@8004c000 {
reg = <0x8004c000 0x2000>;
dmas = <&dma_apbx 0>;
dma-names = "rx";
status = "disabled";
};
lradc: lradc@80050000 {
compatible = "fsl,imx23-lradc";
reg = <0x80050000 0x2000>;
interrupts = <36 37 38 39 40 41 42 43 44>;
status = "disabled";
clocks = <&clks 26>;
#io-channel-cells = <1>;
};
spdif@80054000 {
reg = <0x80054000 2000>;
dmas = <&dma_apbx 2>;
dma-names = "tx";
status = "disabled";
};
i2c: i2c@80058000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-i2c";
reg = <0x80058000 0x2000>;
interrupts = <27>;
clock-frequency = <100000>;
dmas = <&dma_apbx 3>;
dma-names = "rx-tx";
status = "disabled";
};
rtc@8005c000 {
compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
reg = <0x8005c000 0x2000>;
interrupts = <22>;
};
pwm: pwm@80064000 {
compatible = "fsl,imx23-pwm";
reg = <0x80064000 0x2000>;
clocks = <&clks 30>;
#pwm-cells = <2>;
fsl,pwm-number = <5>;
status = "disabled";
};
timrot@80068000 {
compatible = "fsl,imx23-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
interrupts = <28 29 30 31>;
clocks = <&clks 28>;
};
auart0: serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24>;
clocks = <&clks 32>;
dmas = <&dma_apbx 6>, <&dma_apbx 7>;
dma-names = "rx", "tx";
status = "disabled";
};
auart1: serial@8006e000 {
compatible = "fsl,imx23-auart";
reg = <0x8006e000 0x2000>;
interrupts = <59>;
clocks = <&clks 32>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
status = "disabled";
};
duart: serial@80070000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80070000 0x2000>;
interrupts = <0>;
clocks = <&clks 32>, <&clks 16>;
clock-names = "uart", "apb_pclk";
status = "disabled";
};
usbphy0: usbphy@8007c000 {
compatible = "fsl,imx23-usbphy";
reg = <0x8007c000 0x2000>;
clocks = <&clks 41>;
status = "disabled";
};
};
};
ahb@80080000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80080000 0x80000>;
ranges;
usb0: usb@80080000 {
compatible = "fsl,imx23-usb", "fsl,imx27-usb";
reg = <0x80080000 0x40000>;
interrupts = <11>;
fsl,usbphy = <&usbphy0>;
clocks = <&clks 40>;
status = "disabled";
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&lradc 8>;
};
};

726
arch/arm/dts/imx51-babbage.dts Normal file
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@ -0,0 +1,726 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx51.dtsi"
/ {
model = "Freescale i.MX51 Babbage Board";
compatible = "fsl,imx51-babbage", "fsl,imx51";
chosen {
stdout-path = &uart1;
};
memory@90000000 {
device_type = "memory";
reg = <0x90000000 0x20000000>;
};
ckih1 {
clock-frequency = <22579200>;
};
clk_osc: clk-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk_osc_gate: clk-osc-gate {
compatible = "gpio-gate-clock";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_clk26mhz_osc>;
clocks = <&clk_osc>;
#clock-cells = <0>;
enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
clk_audio: clk-audio {
compatible = "gpio-gate-clock";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_clk26mhz_audio>;
clocks = <&clk_osc_gate>;
#clock-cells = <0>;
enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
};
clk_usb: clk-usb {
compatible = "gpio-gate-clock";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_clk26mhz_usb>;
clocks = <&clk_osc_gate>;
#clock-cells = <0>;
enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
display1: disp1 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp1>;
};
};
port@1 {
reg = <1>;
parallel_display_out: endpoint {
remote-endpoint = <&tfp410_in>;
};
};
};
display2: disp2 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2>;
status = "disabled";
display-timings {
native-mode = <&timing1>;
timing1: claawvga {
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
port {
display1_in: endpoint {
remote-endpoint = <&ipu_di1_disp2>;
};
};
};
dvi-connector {
compatible = "dvi-connector";
digital;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
dvi-encoder {
compatible = "ti,tfp410";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&parallel_display_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-diagnostic {
label = "diagnostic";
gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_hub_reset: regulator@0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotgreg>;
reg = <0>;
regulator-name = "hub_reset";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx51-babbage-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx51-babbage-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <3>;
};
usbphy1: usbphy1 {
compatible = "usb-nop-xceiv";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1reg>;
clocks = <&clk_usb>;
clock-names = "main_clk";
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
vcc-supply = <&vusb_reg>;
#phy-cells = <0>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_LOW>;
status = "okay";
pmic: mc13892@0 {
compatible = "fsl,mc13892";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
spi-max-frequency = <6000000>;
spi-cs-high;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
fsl,mc13xxx-uses-adc;
fsl,mc13xxx-uses-rtc;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1375000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
vpll_reg: vpll {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdig_reg: vdig {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
};
vsd_reg: vsd {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3150000>;
};
vusb_reg: vusb {
regulator-boot-on;
};
vusb2_reg: vusb2 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2775000>;
regulator-boot-on;
regulator-always-on;
};
vvideo_reg: vvideo {
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
};
vaudio_reg: vaudio {
regulator-min-microvolt = <2300000>;
regulator-max-microvolt = <3000000>;
};
vcam_reg: vcam {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3000000>;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-always-on;
};
};
};
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_audio>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
};
&ipu_di0_disp1 {
remote-endpoint = <&display0_in>;
};
&ipu_di1_disp2 {
remote-endpoint = <&display1_in>;
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
linux,keymap = <
MATRIX_KEY(0, 0, KEY_UP)
MATRIX_KEY(0, 1, KEY_DOWN)
MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
MATRIX_KEY(0, 3, KEY_HOME)
MATRIX_KEY(1, 0, KEY_RIGHT)
MATRIX_KEY(1, 1, KEY_LEFT)
MATRIX_KEY(1, 2, KEY_ENTER)
MATRIX_KEY(1, 3, KEY_VOLUMEUP)
MATRIX_KEY(2, 0, KEY_F6)
MATRIX_KEY(2, 1, KEY_F8)
MATRIX_KEY(2, 2, KEY_F9)
MATRIX_KEY(2, 3, KEY_F10)
MATRIX_KEY(3, 0, KEY_F1)
MATRIX_KEY(3, 1, KEY_F2)
MATRIX_KEY(3, 2, KEY_F3)
MATRIX_KEY(3, 3, KEY_POWER)
>;
status = "okay";
};
&pmu {
secure-reg-access;
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_hub_reset>;
fsl,usbphy = <&usbphy1>;
phy_type = "ulpi";
status = "okay";
};
&usbphy0 {
vcc-supply = <&vusb_reg>;
};
&usbotg {
dr_mode = "otg";
disable-over-current;
phy_type = "utmi_wide";
status = "okay";
};
&iomuxc {
imx51-babbage {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>;
};
pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
fsl,pins = <
MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
>;
};
pinctrl_clk26mhz_osc: clk26mhzoscgrp {
fsl,pins = <
MX51_PAD_DI1_PIN12__GPIO3_1 0x85
>;
};
pinctrl_clk26mhz_usb: clk26mhzusbgrp {
fsl,pins = <
MX51_PAD_EIM_D17__GPIO2_1 0x85
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
MX51_PAD_GPIO1_0__GPIO1_0 0x100
MX51_PAD_GPIO1_1__GPIO1_1 0x100
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX51_PAD_EIM_A27__GPIO2_21 0x5
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX51_PAD_EIM_D22__GPIO2_6 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
>;
};
pinctrl_ipu_disp1: ipudisp1grp {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
>;
};
pinctrl_ipu_disp2: ipudisp2grp {
fsl,pins = <
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
MX51_PAD_DI_GP4__DI2_PIN15 0x5
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
>;
};
pinctrl_usbh1reg: usbh1reggrp {
fsl,pins = <
MX51_PAD_EIM_D21__GPIO2_5 0x85
>;
};
pinctrl_usbotgreg: usbotgreggrp {
fsl,pins = <
MX51_PAD_GPIO1_7__GPIO1_7 0x85
>;
};
};
};

768
arch/arm/dts/imx51-pinfunc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#ifndef __DTS_IMX51_PINFUNC_H
#define __DTS_IMX51_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0
#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0
#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0
#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0
#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0
#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0
#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0
#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0
#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0
#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0
#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0
#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0
#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0
#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0
#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0
#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0
#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0
#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0
#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0
#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0
#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0
#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0
#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0
#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0
#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0
#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0
#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0
#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0
#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0
#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0
#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0
#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0
#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0
#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0
#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0
#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0
#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0
#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0
#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0
#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0
#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0
#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0
#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0
#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0
#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0
#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0
#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0
#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0
#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0
#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0
#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0
#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0
#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0
#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0
#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0
#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0
#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0
#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0
#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0
#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0
#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0
#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0
#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0
#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0
#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0
#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0
#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0
#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0
#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0
#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0
#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0
#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0
#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0
#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0
#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0
#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0
#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0
#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0
#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0
#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0
#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0
#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0
#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0
#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0
#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0
#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0
#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0
#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0
#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0
#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0
#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0
#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0
#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0
#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0
#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0
#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0
#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0
#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0
#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0
#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0
#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0
#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0
#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0
#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0
#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0
#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0
#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0
#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0
#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0
#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0
#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0
#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0
#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0
#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0
#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0
#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0
#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0
#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0
#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1
#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0
#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0
#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0
#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0
#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0
#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1
#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0
#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0
#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0
#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0
#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0
#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1
#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0
#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0
#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0
#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0
#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0
#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1
#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0
#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0
#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0
#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0
#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0
#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0
#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0
#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0
#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0
#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0
#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0
#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0
#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0
#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0
#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0
#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0
#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0
#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0
#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0
#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0
#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0
#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0
#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0
#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0
#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0
#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0
#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0
#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0
#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0
#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0
#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0
#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0
#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0
#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0
#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0
#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0
#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0
#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0
#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0
#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0
#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0
#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0
#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0
#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0
#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0
#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0
#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0
#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0
#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0
#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0
#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0
#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0
#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0
#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0
#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0
#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0
#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0
#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0
#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0
#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0
#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0
#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0
#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0
#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0
#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0
#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0
#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0
#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0
#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1
#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0
#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0
#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0
#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0
#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0
#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1
#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0
#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0
#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0
#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1
#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0
#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0
#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0
#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0
#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1
#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0
#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0
#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0
#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0
#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1
#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0
#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0
#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0
#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0
#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0
#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0
#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0
#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0
#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0
#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0
#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0
#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0
#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0
#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0
#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0
#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0
#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0
#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0
#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0
#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0
#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0
#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0
#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0
#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0
#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0
#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0
#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0
#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0
#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0
#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0
#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0
#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0
#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0
#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1
#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0
#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0
#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0
#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0
#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0
#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0
#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0
#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0
#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0
#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0
#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0
#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0
#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0
#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0
#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0
#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0
#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0
#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0
#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0
#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0
#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0
#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0
#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0
#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0
#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0
#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0
#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0
#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0
#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0
#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0
#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2
#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0
#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0
#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0
#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1
#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1
#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0
#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1
#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1
#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0
#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1
#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0
#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1
#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0
#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0
#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0
#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0
#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0
#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0
#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0
#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0
#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0
#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0
#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0
#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2
#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0
#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0
#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0
#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0
#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0
#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0
#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4
#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0
#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0
#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0
#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0
#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0
#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0
#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0
#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0
#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0
#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0
#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0
#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0
#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0
#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0
#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0
#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1
#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0
#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0
#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0
#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4
#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1
#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0
#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0
#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0
#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1
#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0
#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2
#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0
#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1
#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2
#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0
#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0
#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0
#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6
#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0
#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0
#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0
#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0
#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0
#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1
#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1
#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0
#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0
#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1
#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1
#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0
#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1
#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0
#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0
#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0
#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1
#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1
#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0
#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1
#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1
#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0
#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0
#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0
#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0
#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0
#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0
#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1
#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1
#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0
#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0
#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1
#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1
#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0
#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0
#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1
#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0
#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1
#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0
#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1
#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1
#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8
#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1
#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1
#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1
#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1
#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1
#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1
#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1
#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1
#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1
#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1
#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1
#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1
#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1
#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0
#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1
#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1
#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1
#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1
#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1
#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1
#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1
#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1
#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1
#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1
#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2
#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0
#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1
#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2
#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2
#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1
#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0
#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2
#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0
#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2
#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0
#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2
#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1
#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0
#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0
#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0
#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0
#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2
#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0
#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0
#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0
#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3
#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2
#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0
#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3
#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2
#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3
#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0
#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0
#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1
#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0
#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0
#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0
#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3
#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1
#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0
#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0
#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3
#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1
#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0
#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0
#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1
#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1
#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0
#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0
#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0
#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0
#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0
#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0
#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0
#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0
#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0
#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0
#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0
#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0
#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0
#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2
#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0
#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0
#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0
#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0
#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0
#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0
#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0
#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0
#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0
#endif /* __DTS_IMX51_PINFUNC_H */

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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
#include "imx51-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
/*
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
*/
chosen {};
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &i2c1;
i2c1 = &i2c2;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
mmc3 = &esdhc4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &cspi;
};
tzic: tz-interrupt-controller@e0000000 {
compatible = "fsl,imx51-tzic", "fsl,tzic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xe0000000 0x4000>;
};
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0>;
clock-latency = <62500>;
clocks = <&clks IMX5_CLK_CPU_PODF>;
clock-names = "cpu";
operating-points = <
166000 1000000
600000 1050000
800000 1100000
>;
voltage-tolerance = <5>;
};
};
pmu: pmu {
compatible = "arm,cortex-a8-pmu";
interrupt-parent = <&tzic>;
interrupts = <77>;
};
usbphy0: usbphy0 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
clock-names = "main_clk";
#phy-cells = <0>;
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu_csi0>, <&ipu_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>, <&ipu_di1>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&tzic>;
ranges;
iram: sram@1ffe0000 {
compatible = "mmio-sram";
reg = <0x1ffe0000 0x20000>;
};
gpu: gpu@30000000 {
compatible = "amd,imageon-200.1", "amd,imageon";
reg = <0x30000000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <12>;
interrupt-names = "kgsl_3d0_irq";
clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
clock-names = "core_clk", "mem_iface_clk";
};
ipu: ipu@40000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ipu";
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
ipu_csi0: port@0 {
reg = <0>;
};
ipu_csi1: port@1 {
reg = <1>;
};
ipu_di0: port@2 {
reg = <2>;
ipu_di0_disp1: endpoint {
};
};
ipu_di1: port@3 {
reg = <3>;
ipu_di1_disp2: endpoint {
};
};
};
bus@70000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x70000000 0x10000000>;
ranges;
spba@70000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x70000000 0x40000>;
ranges;
esdhc1: mmc@70004000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
esdhc2: mmc@70008000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
uart3: serial@7000c000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi1: spi@70010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
reg = <0x70010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
ssi2: ssi@70014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
<&clks IMX5_CLK_SSI2_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
esdhc3: mmc@70020000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
esdhc4: mmc@70024000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
};
aipstz1: bridge@73f00000 {
compatible = "fsl,imx51-aipstz";
reg = <0x73f00000 0x60>;
};
usbotg: usb@73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
};
usbh1: usb@73f80200 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
usbh2: usb@73f80400 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
usbh3: usb@73f80600 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
status = "disabled";
};
usbmisc: usbmisc@73f80800 {
#index-cells = <1>;
compatible = "fsl,imx51-usbmisc";
reg = <0x73f80800 0x200>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
};
gpio1: gpio@73f84000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f84000 0x4000>;
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@73f88000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f88000 0x4000>;
interrupts = <52 53>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@73f8c000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f8c000 0x4000>;
interrupts = <54 55>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@73f90000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f90000 0x4000>;
interrupts = <56 57>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
kpp: kpp@73f94000 {
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
reg = <0x73f94000 0x4000>;
interrupts = <60>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
wdog1: watchdog@73f98000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
clocks = <&clks IMX5_CLK_DUMMY>;
};
wdog2: watchdog@73f9c000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f9c000 0x4000>;
interrupts = <59>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
gpt: timer@73fa0000 {
compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
reg = <0x73fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
iomuxc: iomuxc@73fa8000 {
compatible = "fsl,imx51-iomuxc";
reg = <0x73fa8000 0x4000>;
};
pwm1: pwm@73fb4000 {
#pwm-cells = <3>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
pwm2: pwm@73fb8000 {
#pwm-cells = <3>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
uart1: serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@73fc0000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
src: reset-controller@73fd0000 {
compatible = "fsl,imx51-src";
reg = <0x73fd0000 0x4000>;
interrupts = <75>;
#reset-cells = <1>;
};
clks: ccm@73fd4000{
compatible = "fsl,imx51-ccm";
reg = <0x73fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
#clock-cells = <1>;
};
};
bus@80000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x10000000>;
ranges;
aipstz2: bridge@83f00000 {
compatible = "fsl,imx51-aipstz";
reg = <0x83f00000 0x60>;
};
iim: efuse@83f98000 {
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
clocks = <&clks IMX5_CLK_IIM_GATE>;
};
tigerp: tigerp@83fa0000 {
compatible = "fsl,imx51-tigerp";
reg = <0x83fa0000 0x28>;
};
owire: owire@83fa4000 {
compatible = "fsl,imx51-owire", "fsl,imx21-owire";
reg = <0x83fa4000 0x4000>;
interrupts = <88>;
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
status = "disabled";
};
ecspi2: spi@83fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
reg = <0x83fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
sdma: sdma@83fb0000 {
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
cspi: spi@83fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
reg = <0x83fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c2: i2c@83fc4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks IMX5_CLK_I2C2_GATE>;
status = "disabled";
};
i2c1: i2c@83fc8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc8000 0x4000>;
interrupts = <62>;
clocks = <&clks IMX5_CLK_I2C1_GATE>;
status = "disabled";
};
ssi1: ssi@83fcc000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
<&clks IMX5_CLK_SSI1_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
audmux: audmux@83fd0000 {
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
reg = <0x83fd0000 0x4000>;
clocks = <&clks IMX5_CLK_DUMMY>;
clock-names = "audmux";
status = "disabled";
};
m4if: m4if@83fd8000 {
compatible = "fsl,imx51-m4if";
reg = <0x83fd8000 0x1000>;
};
weim: weim@83fda000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx51-weim";
reg = <0x83fda000 0x1000>;
clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
ranges = <
0 0 0xb0000000 0x08000000
1 0 0xb8000000 0x08000000
2 0 0xc0000000 0x08000000
3 0 0xc8000000 0x04000000
4 0 0xcc000000 0x02000000
5 0 0xce000000 0x02000000
>;
status = "disabled";
};
nfc: nand@83fdb000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx51-nand";
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
interrupts = <8>;
clocks = <&clks IMX5_CLK_NFC_GATE>;
status = "disabled";
};
pata: pata@83fe0000 {
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks IMX5_CLK_PATA_GATE>;
status = "disabled";
};
ssi3: ssi@83fe8000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>;
interrupts = <96>;
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
<&clks IMX5_CLK_SSI3_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 46 0 0>,
<&sdma 47 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
fec: ethernet@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
vpu: vpu@83ff4000 {
compatible = "fsl,imx51-vpu", "cnm,codahx4";
reg = <0x83ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
<&clks IMX5_CLK_VPU_GATE>;
clock-names = "per", "ahb";
resets = <&src 1>;
iram = <&iram>;
};
sahara: crypto@83ff8000 {
compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
reg = <0x83ff8000 0x4000>;
interrupts = <19 20>;
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
<&clks IMX5_CLK_SAHARA_IPG_GATE>;
clock-names = "ipg", "ahb";
};
};
};
};

387
arch/arm/dts/imx53-qsb-common.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
#include "imx53.dtsi"
/ {
chosen {
stdout-path = &uart1;
};
memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
display0: disp0 {
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
port@1 {
reg = <1>;
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
label = "Volume Down";
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio7_7>;
user {
label = "Heartbeat";
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};
panel {
compatible = "sii,43wvf1g";
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p2v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_usb_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio7 8 0>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx53-qsb-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-qsb-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
&cpu0 {
/* CPU rated to 1GHz, not 1.2GHz as per the default settings */
operating-points = <
/* kHz uV */
166666 850000
400000 900000
800000 1050000
1000000 1200000
>;
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&ipu_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&ssi2 {
status = "okay";
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3>;
cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
bus-width = <8>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx53-qsb {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
>;
};
led_pin_gpio7_7: led_gpio7_7 {
fsl,pins = <
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
pinctrl_codec: codecgrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
MX53_PAD_EIM_DA13__GPIO3_13 0xe4
>;
};
pinctrl_esdhc3: esdhc3grp {
fsl,pins = <
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
>;
};
/* open drain */
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_ipu_disp0: ipudisp0grp {
fsl,pins = <
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
};
pinctrl_vga_sync: vgasync-grp {
fsl,pins = <
/* VGA_HSYNC, VSYNC with max drive strength */
MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
>;
};
};
};
&tve {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vga_sync>;
ddc-i2c-bus = <&i2c2>;
fsl,tve-mode = "vga";
fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */
fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_codec>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sata {
status = "okay";
};
&vpu {
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
phy_type = "utmi";
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx53-qsb-common.dtsi"
/ {
model = "Freescale i.MX53 Quick Start Board";
compatible = "fsl,imx53-qsb", "fsl,imx53";
};
&i2c1 {
pmic: dialog@48 {
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
interrupt-parent = <&gpio7>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */
regulators {
buck1_reg: buck1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
regulator-always-on;
};
buck3_reg: buck3 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
buck4_reg: buck4 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo5_reg: ldo5 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo6_reg: ldo6 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo7_reg: ldo7 {
regulator-min-microvolt = <2750000>;
regulator-max-microvolt = <2750000>;
};
ldo8_reg: ldo8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo9_reg: ldo9 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo10_reg: ldo10 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
};
};
};
&tve {
dac-supply = <&ldo7_reg>;
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
&fec1 {
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <1>;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
u-boot,dm-spl;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key_erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
};
&A53_0 {
cpu-supply = <&buck3_reg>;
};
&A53_1 {
cpu-supply = <&buck3_reg>;
};
&A53_2 {
cpu-supply = <&buck3_reg>;
};
&A53_3 {
cpu-supply = <&buck3_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
pinctrl-0 = <&pinctrl_gsc>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@16 {
gw,mode = <4>;
reg = <0x16>;
label = "fan_tach";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_adc1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_adc2";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_dram";
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_1p2";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_1p0";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_2p5";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_0p95";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_1p8";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
fan-controller@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "gw,gsc-fan";
reg = <0x0a>;
};
};
gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
pmic@69 {
compatible = "mps,mp5416";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x69>;
regulators {
buck1 {
regulator-name = "vdd_0p95";
regulator-min-microvolt = <805000>;
regulator-max-microvolt = <1000000>;
regulator-max-microamp = <2500000>;
regulator-boot-on;
};
buck2 {
regulator-name = "vdd_soc";
regulator-min-microvolt = <805000>;
regulator-max-microvolt = <900000>;
regulator-max-microamp = <1000000>;
regulator-boot-on;
};
buck3_reg: buck3 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <805000>;
regulator-max-microvolt = <1000000>;
regulator-max-microamp = <2200000>;
regulator-boot-on;
};
buck4 {
regulator-name = "vdd_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-max-microamp = <500000>;
regulator-boot-on;
};
ldo1 {
regulator-name = "nvcc_snvs_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-max-microamp = <300000>;
regulator-boot-on;
};
ldo2 {
regulator-name = "vdd_snvs_0p8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
};
ldo3 {
regulator-name = "vdd_0p95";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
};
ldo4 {
regulator-name = "vdd_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
};
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
>;
};
pinctrl_gsc: gscgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include "imx8mm-venice-gw700x-u-boot.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw71xx.dtsi"
/ {
model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit";
compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* off-board header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
>;
};
pinctrl_reg_usb1_en: regusb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include "imx8mm-venice-gw700x-u-boot.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw72xx.dtsi"
/ {
model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit";
compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg2_vbus: regulator-usb-otg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* off-board header */
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* off-board header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* RS232 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
>;
};
pinctrl_reg_usb1_en: regusb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
pinctrl_reg_usb2_en: regusb2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include "imx8mm-venice-gw700x-u-boot.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw73xx.dtsi"
/ {
model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit";
compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg2_vbus: regulator-usb-otg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_wifi_en: regulator-wifi-en {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wl>;
compatible = "regulator-fixed";
regulator-name = "wl";
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* off-board header */
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* bluetooth HCI */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
};
/* RS232 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
/* SDIO WiFi */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
non-removable;
vmmc-supply = <&reg_wifi_en>;
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
>;
};
pinctrl_bten: btengrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
>;
};
pinctrl_reg_wl: regwlgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
>;
};
pinctrl_reg_usb1_en: regusb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
pinctrl_reg_usb2_en: regusb2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

103
arch/arm/dts/imx8mm-venice-u-boot.dtsi Normal file
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@ -0,0 +1,103 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};

152
arch/arm/dts/imx8mm-venice.dts Normal file
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@ -0,0 +1,152 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
/ {
model = "Gateworks Venice i.MX8MM board";
compatible = "gw,imx8mm-venice", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

2
arch/arm/dts/imx8mp-evk-u-boot.dtsi
View file

@ -142,4 +142,6 @@
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};

4
arch/arm/dts/imx8mq-evk-u-boot.dtsi
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@ -1,9 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
&usdhc1 {
mmc-hs400-1_8v;
};

22
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
View file

@ -117,4 +117,26 @@
};
};
#if defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
&uboot_blob {
filename = "signed-u-boot-nodtb.bin";
};
&atf_blob {
filename = "signed-bl31.bin";
};
&uboot_fdt_blob {
filename = "signed-u-boot.dtb";
};
&kernel_blob {
filename = "signed-Image";
};
&kernel_fdt_blob {
filename = "signed-linux.dtb";
};
#endif
#endif

4
arch/arm/dts/stm32mp151.dtsi
View file

@ -1136,6 +1136,10 @@
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
<&clk_lse>, <&clk_lsi>;
};
pwr_regulators: pwr@50001000 {

2
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
View file

@ -69,8 +69,6 @@
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
#endif
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000

2
arch/arm/include/asm/arch-imx8/imx-regs.h
View file

@ -26,6 +26,8 @@
#define LPI2C4_BASE_ADDR 0x5A830000
#define LPI2C5_BASE_ADDR 0x5A840000
#define FEC_QUIRK_ENET_MAC
#ifdef CONFIG_IMX8QXP
#define LVDS0_PHYCTRL_BASE 0x56221000
#define LVDS1_PHYCTRL_BASE 0x56241000

1
arch/arm/include/asm/arch-imx8m/imx-regs.h
View file

@ -63,6 +63,7 @@
#define DDR_CSD1_BASE_ADDR 0x40000000
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
#define FEC_QUIRK_ENET_MAC
#if !defined(__ASSEMBLY__)
#include <asm/types.h>

4
arch/arm/mach-imx/Makefile
View file

@ -202,10 +202,10 @@ append = cat $(filter-out $< $(PHONY), $^) >> $@
quiet_cmd_pad_cat = CAT $@
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
u-boot-with-spl.imx: SPL u-boot.uim FORCE
u-boot-with-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
$(call if_changed,pad_cat)
u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
$(call if_changed,pad_cat)
quiet_cmd_u-boot-nand-spl_imx = GEN $@

7
arch/arm/mach-imx/imx8m/Kconfig
View file

@ -43,6 +43,12 @@ config TARGET_IMX8MM_EVK
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
select IMX8MN
@ -95,6 +101,7 @@ source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"

19
arch/arm/mach-imx/imx8m/soc.c
View file

@ -154,6 +154,17 @@ static struct mm_region imx8m_mem_map[] = {
struct mm_region *mem_map = imx8m_mem_map;
static unsigned int imx8m_find_dram_entry_in_mem_map(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
}
void enable_caches(void)
{
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
@ -167,10 +178,11 @@ void enable_caches(void)
* please make sure that entry initial value matches
* imx8m_mem_map for DRAM1
*/
int entry = 5;
int entry = imx8m_find_dram_entry_in_mem_map();
u64 attrs = imx8m_mem_map[entry].attrs;
while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8m_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
break;
imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
@ -198,6 +210,7 @@ __weak int board_phys_sdram_size(phys_size_t *size)
int dram_init(void)
{
unsigned int entry = imx8m_find_dram_entry_in_mem_map();
phys_size_t sdram_size;
int ret;
@ -212,7 +225,7 @@ int dram_init(void)
gd->ram_size = sdram_size;
/* also update the SDRAM size in the mem_map used externally */
imx8m_mem_map[5].size = sdram_size;
imx8m_mem_map[entry].size = sdram_size;
#ifdef PHYS_SDRAM_2_SIZE
gd->ram_size += PHYS_SDRAM_2_SIZE;

37
arch/arm/mach-imx/mx6/soc.c
View file

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <linux/delay.h>
#include <linux/errno.h>
@ -696,11 +697,47 @@ void imx_setup_hdmi(void)
#endif
#ifdef CONFIG_ARCH_MISC_INIT
/*
* UNIQUE_ID describes a unique ID based on silicon wafer
* and die X/Y position
*
* UNIQUE_ID offset 0x410
* 31:0 fuse 0
* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
*
* UNIQUE_ID offset 0x420
* 31:24 fuse 1
* The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
* 23:16 fuse 1
* The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
* 15:11 fuse 1
* The wafer number of the wafer on which the device was fabricated/SJC
* CHALLENGE/ Unique ID
* 10:0 fuse 1
* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
*/
static void setup_serial_number(void)
{
char serial_string[17];
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
if (env_get("serial#"))
return;
snprintf(serial_string, sizeof(serial_string), "%08x%08x",
fuse->uid_low, fuse->uid_high);
env_set("serial#", serial_string);
}
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
setup_serial_number();
return 0;
}
#endif

2
arch/arm/mach-mvebu/include/mach/cpu.h
View file

@ -164,7 +164,7 @@ int serdes_phy_config(void);
int ddr3_init(void);
/* Auto Voltage Scaling */
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
#if defined(CONFIG_ARMADA_38X)
void mv_avs_init(void);
void mv_rtc_config(void);
#else

46
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
View file

@ -14,11 +14,6 @@
#include "sys_env_lib.h"
#include "ctrl_pex.h"
#if defined(CONFIG_ARMADA_38X)
#elif defined(CONFIG_ARMADA_39X)
#else
#error "No device is defined"
#endif
/*
@ -79,11 +74,6 @@ u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = {
{ NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */
{ NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */
{ NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */
#ifdef CONFIG_ARMADA_39X
{ NA, NA, 0x5, NA, 0x8, NA, 0x2 }, /* SGMII3 */
{ NA, NA, NA, 0x8, 0x9, 0x8, 0x4 }, /* XAUI */
{ NA, NA, NA, NA, NA, 0x8, 0x4 }, /* RXAUI */
#endif
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */
};
@ -798,11 +788,9 @@ struct op_params serdes_power_down_params[] = {
*/
u8 hws_ctrl_serdes_rev_get(void)
{
#ifdef CONFIG_ARMADA_38X
/* for A38x-Z1 */
if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID)
return MV_SERDES_REV_1_2;
#endif
/* for A39x-Z1, A38x-A0 */
return MV_SERDES_REV_2_1;
@ -1351,9 +1339,6 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
case SGMII0:
case SGMII1:
case SGMII2:
#ifdef CONFIG_ARMADA_39X
case SGMII3:
#endif
if (baud_rate == SERDES_SPEED_1_25_GBPS)
seq_id = SGMII_1_25_SPEED_CONFIG_SEQ;
else if (baud_rate == SERDES_SPEED_3_125_GBPS)
@ -1362,14 +1347,6 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
case QSGMII:
seq_id = QSGMII_5_SPEED_CONFIG_SEQ;
break;
#ifdef CONFIG_ARMADA_39X
case XAUI:
seq_id = XAUI_3_125_SPEED_CONFIG_SEQ;
break;
case RXAUI:
seq_id = RXAUI_6_25_SPEED_CONFIG_SEQ;
break;
#endif
default:
return SERDES_LAST_SEQ;
}
@ -2054,13 +2031,6 @@ int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
(serdes_num,
PEX_CONFIG_REF_CLOCK_100MHZ_SEQ));
return MV_OK;
#ifdef CONFIG_ARMADA_39X
case REF_CLOCK_40MHZ:
CHECK_STATUS(mv_seq_exec
(serdes_num,
PEX_CONFIG_REF_CLOCK_40MHZ_SEQ));
return MV_OK;
#endif
default:
printf
("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n",
@ -2104,22 +2074,6 @@ int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
return MV_BAD_PARAM;
}
break;
#ifdef CONFIG_ARMADA_39X
case SGMII3:
case XAUI:
case RXAUI:
if (ref_clock == REF_CLOCK_25MHZ) {
data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
} else if (ref_clock == REF_CLOCK_40MHZ) {
data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
} else {
printf
("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
serdes_type);
return MV_BAD_PARAM;
}
break;
#endif
default:
DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n");
return MV_BAD_PARAM;

24
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
View file

@ -12,7 +12,6 @@
#include "seq_exec.h"
#include "sys_env_lib.h"
#ifdef CONFIG_ARMADA_38X
enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
/* 6820 6810 6811 6828 */
/* PEX_UNIT_ID */ { 4, 3, 3, 4},
@ -24,19 +23,6 @@ enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
/* XAUI_UNIT_ID */ { 0, 0, 0, 0},
/* RXAUI_UNIT_ID */ { 0, 0, 0, 0}
};
#else /* if (CONFIG_ARMADA_39X) */
enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
/* 6920 6928 */
/* PEX_UNIT_ID */ { 4, 4},
/* ETH_GIG_UNIT_ID */ { 3, 4},
/* USB3H_UNIT_ID */ { 1, 2},
/* USB3D_UNIT_ID */ { 0, 1},
/* SATA_UNIT_ID */ { 0, 4},
/* QSGMII_UNIT_ID */ { 0, 1},
/* XAUI_UNIT_ID */ { 1, 1},
/* RXAUI_UNIT_ID */ { 1, 1}
};
#endif
u32 g_dev_id = -1;
@ -202,11 +188,7 @@ u16 sys_env_model_get(void)
return ctrl_id;
default:
/* Device ID Default for A38x: 6820 , for A39x: 6920 */
#ifdef CONFIG_ARMADA_38X
default_ctrl_id = MV_6820_DEV_ID;
#else
default_ctrl_id = MV_6920_DEV_ID;
#endif
printf("%s: Error retrieving device ID (%x), using default ID = %x\n",
__func__, ctrl_id, default_ctrl_id);
return default_ctrl_id;
@ -261,9 +243,6 @@ void mv_rtc_config(void)
{
u32 i, val;
if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
return;
/* Activate pipe0 for read/write transaction, and set XBAR client number #1 */
val = 0x1 << DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS |
0x1 << DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS;
@ -278,9 +257,6 @@ void mv_avs_init(void)
{
u32 sar_freq;
if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
return;
reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);

35
arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
View file

@ -118,12 +118,8 @@
/* TWSI addresses */
/* starting from A38x A0, i2c address of EEPROM is 0x57 */
#ifdef CONFIG_ARMADA_39X
#define EEPROM_I2C_ADDR 0x50
#else
#define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \
MV_88F68XX_Z1_ID ? 0x50 : 0x57)
#endif
#define RD_GET_MODE_ADDR 0x4c
#define DB_GET_MODE_SLM1363_ADDR 0x25
#define DB_GET_MODE_SLM1364_ADDR 0x24
@ -216,7 +212,6 @@
#define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \
A39X_MARVELL_BOARD_ID_BASE)
#ifdef CONFIG_ARMADA_38X
#define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE
#define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0
#define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1
@ -227,18 +222,6 @@
#define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM
#define MV_DEFAULT_BOARD_ID DB_68XX_ID
#define MV_DEFAULT_DEVICE_ID MV_6811
#elif defined(CONFIG_ARMADA_39X)
#define CUTOMER_BOARD_ID_BASE A39X_CUSTOMER_BOARD_ID_BASE
#define CUSTOMER_BOARD_ID0 A39X_CUSTOMER_BOARD_ID0
#define CUSTOMER_BOARD_ID1 A39X_CUSTOMER_BOARD_ID1
#define MV_MAX_CUSTOMER_BOARD_ID A39X_MV_MAX_CUSTOMER_BOARD_ID
#define MV_CUSTOMER_BOARD_NUM A39X_MV_CUSTOMER_BOARD_NUM
#define MARVELL_BOARD_ID_BASE A39X_MARVELL_BOARD_ID_BASE
#define MV_MAX_MARVELL_BOARD_ID A39X_MV_MAX_MARVELL_BOARD_ID
#define MV_MARVELL_BOARD_NUM A39X_MV_MARVELL_BOARD_NUM
#define MV_DEFAULT_BOARD_ID A39X_DB_69XX_ID
#define MV_DEFAULT_DEVICE_ID MV_6920
#endif
#define MV_INVALID_BOARD_ID 0xffffffff
@ -295,11 +278,7 @@ enum {
#define MV_6920_INDEX 0
#define MV_6928_INDEX 1
#ifdef CONFIG_ARMADA_38X
#define MAX_DEV_ID_NUM 4
#else
#define MAX_DEV_ID_NUM 2
#endif
#define MV_6820_INDEX 0
#define MV_6810_INDEX 1
@ -340,21 +319,13 @@ enum suspend_wakeup_status {
* If suspend to RAM is not supported set '-1'
*/
#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
#ifdef CONFIG_ARMADA_38X
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{A38X_CUSTOMER_BOARD_ID0, -1 }, \
{A38X_CUSTOMER_BOARD_ID0, -1 }, \
};
#else
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{A39X_CUSTOMER_BOARD_ID0, -1 }, \
{A39X_CUSTOMER_BOARD_ID0, -1 }, \
};
#endif /* CONFIG_ARMADA_38X */
#else
#ifdef CONFIG_ARMADA_38X
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{RD_NAS_68XX_ID, -2 }, \
{DB_68XX_ID, -1 }, \
@ -364,12 +335,6 @@ enum suspend_wakeup_status {
{DB_BP_6821_ID, -2 }, \
{DB_AMC_6820_ID, -2 }, \
};
#else
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{A39X_RD_69XX_ID, -1 }, \
{A39X_DB_69XX_ID, -1 }, \
};
#endif /* CONFIG_ARMADA_38X */
#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
u32 mv_board_tclk_get(void);

3
arch/arm/mach-omap2/omap3/board.c
View file

@ -179,6 +179,8 @@ void early_system_init(void)
hw_data_init();
}
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
@ -207,6 +209,7 @@ void s_init(void)
ehci_clocks_enable();
#endif
}
#endif
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)

6
arch/arm/mach-omap2/omap3/lowlevel_init.S
View file

@ -45,7 +45,7 @@ ENDPROC(do_omap3_emu_romcode_call)
ENTRY(cpy_clk_code)
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* copy from start of go_to_speed... */
adr r2, lowlevel_init /* ... up to start of low_level_init */
adr r2, go_to_speed_end /* ... up to start of go_to_speed_end */
next2:
ldmia r0!, {r3 - r10} /* copy from source address [r0] */
stmia r1!, {r3 - r10} /* copy to target address [r1] */
@ -167,8 +167,11 @@ pll_div_add5:
pll_div_val5:
.word CLSEL1_EMU_VAL
go_to_speed_end:
#endif
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
str ip, [sp] /* stash ip register */
@ -187,6 +190,7 @@ ENTRY(lowlevel_init)
b s_init
ENDPROC(lowlevel_init)
#endif
/* the literal pools origin */
.ltorg

20
arch/arm/mach-socfpga/Kconfig
View file

@ -6,6 +6,21 @@ config ERR_PTR_OFFSET
config NR_DRAM_BANKS
default 1
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
depends on TARGET_SOCFPGA_AGILEX
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
select SPL_FIT_IMAGE_POST_PROCESS
help
All images loaded from FIT will be authenticated by Secure Device
Manager.
config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
bool "Allow non-FIT VAB signed images"
depends on SOCFPGA_SECURE_VAB_AUTH
config SPL_SIZE_LIMIT
default 0x10000 if TARGET_SOCFPGA_GEN5
@ -38,6 +53,7 @@ config TARGET_SOCFPGA_AGILEX
select FPGA_INTEL_SDM_MAILBOX
select NCORE_CACHE
select SPL_CLK if SPL
select TARGET_SOCFPGA_SOC64
config TARGET_SOCFPGA_ARRIA5
bool
@ -75,12 +91,16 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
config TARGET_SOCFPGA_SOC64
bool
config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF
select FPGA_INTEL_SDM_MAILBOX
select TARGET_SOCFPGA_SOC64
choice
prompt "Altera SOCFPGA board select"

3
arch/arm/mach-socfpga/Makefile
View file

@ -4,6 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
# Copyright (C) 2017-2020 Intel Corporation <www.intel.com>
obj-y += board.o
obj-y += clock_manager.o
@ -47,8 +48,10 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif

45
arch/arm/mach-socfpga/board.c
View file

@ -6,14 +6,17 @@
*/
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
#include <init.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/secure_vab.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <fdtdec.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
@ -98,3 +101,37 @@ __weak int board_fit_config_name_match(const char *name)
return 0;
}
#endif
#if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
if (socfpga_vendor_authentication(p_image, p_size))
hang();
}
}
#endif
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(bootm_headers_t *images)
{
if (!IS_ENABLED(CONFIG_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
/*
* Ensure the OS is always booted from FIT and with
* VAB signed certificate
*/
if (!images->fit_uname_cfg) {
printf("Please use FIT with VAB signed images!\n");
hang();
}
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
if (env_get("linux_qspi_enable"))
run_command(env_get("linux_qspi_enable"), 0);
}
}
#endif

1
arch/arm/mach-socfpga/include/mach/mailbox_s10.h
View file

@ -118,6 +118,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
#define MBOX_RECONFIG_MSEL 7
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
#define MBOX_VAB_SRC_CERT 11
#define MBOX_QSPI_OPEN 50
#define MBOX_QSPI_CLOSE 51
#define MBOX_QSPI_DIRECT 59

3
arch/arm/mach-socfpga/include/mach/reset_manager.h
View file

@ -43,8 +43,7 @@ void socfpga_per_reset_all(void);
#include <asm/arch/reset_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/reset_manager_arria10.h>
#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#elif defined(CONFIG_TARGET_SOCFPGA_SOC64)
#include <asm/arch/reset_manager_soc64.h>
#endif

63
arch/arm/mach-socfpga/include/mach/secure_vab.h Normal file
View file

@ -0,0 +1,63 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
*
*/
#ifndef _SECURE_VAB_H_
#define _SECURE_VAB_H_
#include <linux/sizes.h>
#include <linux/stddef.h>
#include <u-boot/sha512.h>
#define VAB_DATA_SZ 64
#define SDM_CERT_MAGIC_NUM 0x25D04E7F
#define FCS_HPS_VAB_MAGIC_NUM 0xD0564142
#define MAX_CERT_SIZE (SZ_4K)
/*
* struct fcs_hps_vab_certificate_data
* @vab_cert_magic_num: VAB Certificate Magic Word (0xD0564142)
* @flags: TBD
* @fcs_data: Data words being certificate signed.
* @cert_sign_keychain: Certificate Signing Keychain
*/
struct fcs_hps_vab_certificate_data {
u32 vab_cert_magic_num; /* offset 0x10 */
u32 flags;
u8 rsvd0_1[8];
u8 fcs_sha384[SHA384_SUM_LEN]; /* offset 0x20 */
};
/*
* struct fcs_hps_vab_certificate_header
* @cert_magic_num: Certificate Magic Word (0x25D04E7F)
* @cert_data_sz: size of this certificate header (0x80)
* Includes magic number all the way to the certificate
* signing keychain (excludes cert. signing keychain)
* @cert_ver: Certificate Version
* @cert_type: Certificate Type
* @data: VAB HPS Image Certificate data
*/
struct fcs_hps_vab_certificate_header {
u32 cert_magic_num; /* offset 0 */
u32 cert_data_sz;
u32 cert_ver;
u32 cert_type;
struct fcs_hps_vab_certificate_data d; /* offset 0x10 */
/* keychain starts at offset 0x50 */
};
#define VAB_CERT_HEADER_SIZE sizeof(struct fcs_hps_vab_certificate_header)
#define VAB_CERT_MAGIC_OFFSET offsetof \
(struct fcs_hps_vab_certificate_header, d)
#define VAB_CERT_FIT_SHA384_OFFSET offsetof \
(struct fcs_hps_vab_certificate_data, \
fcs_sha384[0])
int socfpga_vendor_authentication(void **p_image, size_t *p_size);
#endif /* _SECURE_VAB_H_ */

3
arch/arm/mach-socfpga/include/mach/system_manager.h
View file

@ -8,8 +8,7 @@
phys_addr_t socfpga_get_sysmgr_addr(void);
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
#include <asm/arch/system_manager_soc64.h>
#else
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)

186
arch/arm/mach-socfpga/secure_vab.c Normal file
View file

@ -0,0 +1,186 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
*
*/
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/secure_vab.h>
#include <asm/arch/smc_api.h>
#include <asm/unaligned.h>
#include <common.h>
#include <exports.h>
#include <linux/errno.h>
#include <linux/intel-smc.h>
#include <log.h>
#define CHUNKSZ_PER_WD_RESET (256 * SZ_1K)
/*
* Read the length of the VAB certificate from the end of image
* and calculate the actual image size (excluding the VAB certificate).
*/
static size_t get_img_size(u8 *img_buf, size_t img_buf_sz)
{
u8 *img_buf_end = img_buf + img_buf_sz;
u32 cert_sz = get_unaligned_le32(img_buf_end - sizeof(u32));
u8 *p = img_buf_end - cert_sz - sizeof(u32);
/* Ensure p is pointing within the img_buf */
if (p < img_buf || p > (img_buf_end - VAB_CERT_HEADER_SIZE))
return 0;
if (get_unaligned_le32(p) == SDM_CERT_MAGIC_NUM)
return (size_t)(p - img_buf);
return 0;
}
/*
* Vendor Authorized Boot (VAB) is a security feature for authenticating
* the images such as U-Boot, ARM trusted Firmware, Linux kernel,
* device tree blob and etc loaded from FIT. User can also trigger
* the VAB authentication from U-Boot command.
*
* This function extracts the VAB certificate and signature block
* appended at the end of the image, then send to Secure Device Manager
* (SDM) for authentication. This function will validate the SHA384
* of the image against the SHA384 hash stored in the VAB certificate
* before sending the VAB certificate to SDM for authentication.
*
* RETURN
* 0 if authentication success or
* if authentication is not required and bypassed on a non-secure device
* negative error code if authentication fail
*/
int socfpga_vendor_authentication(void **p_image, size_t *p_size)
{
int retry_count = 20;
u8 hash384[SHA384_SUM_LEN];
u64 img_addr, mbox_data_addr;
size_t img_sz, mbox_data_sz;
u8 *cert_hash_ptr, *mbox_relocate_data_addr;
u32 resp = 0, resp_len = 1;
int ret;
img_addr = (uintptr_t)*p_image;
debug("Authenticating image at address 0x%016llx (%ld bytes)\n",
img_addr, *p_size);
img_sz = get_img_size((u8 *)img_addr, *p_size);
debug("img_sz = %ld\n", img_sz);
if (!img_sz) {
puts("VAB certificate not found in image!\n");
return -ENOKEY;
}
if (!IS_ALIGNED(img_sz, sizeof(u32))) {
printf("Image size (%ld bytes) not aliged to 4 bytes!\n",
img_sz);
return -EBFONT;
}
/* Generate HASH384 from the image */
sha384_csum_wd((u8 *)img_addr, img_sz, hash384, CHUNKSZ_PER_WD_RESET);
cert_hash_ptr = (u8 *)(img_addr + img_sz + VAB_CERT_MAGIC_OFFSET +
VAB_CERT_FIT_SHA384_OFFSET);
/*
* Compare the SHA384 found in certificate against the SHA384
* calculated from image
*/
if (memcmp(hash384, cert_hash_ptr, SHA384_SUM_LEN)) {
puts("SHA384 not match!\n");
return -EKEYREJECTED;
}
mbox_data_addr = img_addr + img_sz - sizeof(u32);
/* Size in word (32bits) */
mbox_data_sz = (ALIGN(*p_size - img_sz, sizeof(u32))) >> 2;
debug("mbox_data_addr = 0x%016llx\n", mbox_data_addr);
debug("mbox_data_sz = %ld words\n", mbox_data_sz);
/*
* Relocate certificate to first memory block before trigger SMC call
* to send mailbox command because ATF only able to access first
* memory block.
*/
mbox_relocate_data_addr = (u8 *)malloc(mbox_data_sz * sizeof(u32));
if (!mbox_relocate_data_addr) {
puts("Out of memory for VAB certificate relocation!\n");
return -ENOMEM;
}
memcpy(mbox_relocate_data_addr, (u8 *)mbox_data_addr, mbox_data_sz * sizeof(u32));
*(u32 *)mbox_relocate_data_addr = 0;
debug("mbox_relocate_data_addr = 0x%p\n", mbox_relocate_data_addr);
do {
if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
/* Invoke SMC call to ATF to send the VAB certificate to SDM */
ret = smc_send_mailbox(MBOX_VAB_SRC_CERT, mbox_data_sz,
(u32 *)mbox_relocate_data_addr, 0, &resp_len,
&resp);
} else {
/* Send the VAB certficate to SDM for authentication */
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_VAB_SRC_CERT,
MBOX_CMD_DIRECT, mbox_data_sz,
(u32 *)mbox_relocate_data_addr, 0, &resp_len,
&resp);
}
/* If SDM is not available, just delay 50ms and retry again */
if (ret == MBOX_RESP_DEVICE_BUSY)
mdelay(50);
else
break;
} while (--retry_count);
/* Free the relocate certificate memory space */
free(mbox_relocate_data_addr);
/* Exclude the size of the VAB certificate from image size */
*p_size = img_sz;
debug("ret = 0x%08x, resp = 0x%08x, resp_len = %d\n", ret, resp,
resp_len);
if (ret) {
/*
* Unsupported mailbox command or device not in the
* owned/secure state
*/
if (ret == MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS) {
/* SDM bypass authentication */
printf("%s 0x%016llx (%ld bytes)\n",
"Image Authentication bypassed at address",
img_addr, img_sz);
return 0;
}
puts("VAB certificate authentication failed in SDM");
if (ret == MBOX_RESP_DEVICE_BUSY) {
puts(" (SDM busy timeout)\n");
return -ETIMEDOUT;
} else if (ret == MBOX_RESP_UNKNOWN) {
puts(" (Not supported)\n");
return -ESRCH;
}
puts("\n");
return -EKEYREJECTED;
} else {
/* If Certificate Process Status has error */
if (resp) {
puts("VAB certificate process failed\n");
return -ENOEXEC;
}
}
printf("%s 0x%016llx (%ld bytes)\n",
"Image Authentication passed at address", img_addr, img_sz);
return 0;
}

34
arch/arm/mach-socfpga/vab.c Normal file
View file

@ -0,0 +1,34 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
*
*/
#include <asm/arch/secure_vab.h>
#include <command.h>
#include <common.h>
#include <linux/ctype.h>
static int do_vab(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
unsigned long addr, len;
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
len = simple_strtoul(argv[2], NULL, 16);
if (socfpga_vendor_authentication((void *)&addr, (size_t *)&len) != 0)
return CMD_RET_FAILURE;
return 0;
}
U_BOOT_CMD(
vab, 3, 2, do_vab,
"perform vendor authorization",
"addr len - authorize 'len' bytes starting at\n"
" 'addr' via vendor public key"
);

18
arch/arm/mach-stm32mp/Kconfig
View file

@ -121,23 +121,6 @@ config STM32_ETZPC
help
Say y to enable STM32 Extended TrustZone Protection
config CMD_STM32PROG
bool "command stm32prog for STM32CudeProgrammer"
select DFU
select DFU_RAM
select DFU_VIRT
select PARTITION_TYPE_GUID
imply CMD_GPT if MMC
imply CMD_MTD if MTD
imply DFU_MMC if MMC
imply DFU_MTD if MTD
help
activate a specific command stm32prog for STM32MP soc family
witch update the device with the tools STM32CubeProgrammer,
using UART with STM32 protocol or USB with DFU protocol
NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based
on U-Boot DFU framework
config CMD_STM32KEY
bool "command stm32key to fuse public key hash"
default y
@ -177,6 +160,7 @@ config DEBUG_UART_CLOCK
default 64000000
endif
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
source "board/st/stm32mp1/Kconfig"
source "board/dhelectronics/dh_stm32mp1/Kconfig"

2
arch/arm/mach-stm32mp/Makefile
View file

@ -11,7 +11,7 @@ obj-y += bsec.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog/
obj-y += cmd_stm32prog/
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_TFABOOT) += boot_params.o

10
arch/arm/mach-stm32mp/bsec.c
View file

@ -6,6 +6,7 @@
#define LOG_CATEGORY UCLASS_MISC
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
@ -490,6 +491,15 @@ static int stm32mp_bsec_probe(struct udevice *dev)
{
int otp;
struct stm32mp_bsec_plat *plat;
struct clk_bulk clk_bulk;
int ret;
ret = clk_get_bulk(dev, &clk_bulk);
if (!ret) {
ret = clk_enable_bulk(&clk_bulk);
if (ret)
return ret;
}
/*
* update unlocked shadow for OTP cleared by the rom code

34
arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig Normal file
View file

@ -0,0 +1,34 @@
config CMD_STM32PROG
bool "command stm32prog for STM32CudeProgrammer"
select DFU
select DFU_RAM
select DFU_VIRT
select PARTITION_TYPE_GUID
imply CMD_GPT if MMC
imply CMD_MTD if MTD
imply DFU_MMC if MMC
imply DFU_MTD if MTD
help
activate a specific command stm32prog for STM32MP soc family
witch update the device with the tools STM32CubeProgrammer
NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based
on U-Boot DFU framework
config CMD_STM32PROG_USB
bool "support stm32prog over USB"
depends on CMD_STM32PROG
default y
help
activate the command "stm32prog usb" for STM32MP soc family
witch update the device with the tools STM32CubeProgrammer,
using USB with DFU protocol
config CMD_STM32PROG_SERIAL
bool "support stm32prog over UART"
depends on CMD_STM32PROG
default y
help
activate the command "stm32prog serial" for STM32MP soc family
with the tools STM32CubeProgrammer using U-Boot serial device
and UART protocol.

8
arch/arm/mach-stm32mp/cmd_stm32prog/Makefile
View file

@ -3,7 +3,7 @@
# Copyright (C) 2020, STMicroelectronics - All Rights Reserved
#
obj-y += cmd_stm32prog.o
obj-y += stm32prog.o
obj-y += stm32prog_serial.o
obj-y += stm32prog_usb.o
obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog.o
obj-$(CONFIG_CMD_STM32PROG) += stm32prog.o
obj-$(CONFIG_CMD_STM32PROG_SERIAL) += stm32prog_serial.o
obj-$(CONFIG_CMD_STM32PROG_USB) += stm32prog_usb.o

4
arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
View file

@ -50,9 +50,9 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc,
if (argc < 3 || argc > 5)
return CMD_RET_USAGE;
if (!strcmp(argv[1], "usb"))
if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) && !strcmp(argv[1], "usb"))
link = LINK_USB;
else if (!strcmp(argv[1], "serial"))
else if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && !strcmp(argv[1], "serial"))
link = LINK_SERIAL;
if (link == LINK_UNDEFINED) {

27
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
View file

@ -177,9 +177,30 @@ char *stm32prog_get_error(struct stm32prog_data *data);
/* Main function */
int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size);
int stm32prog_serial_init(struct stm32prog_data *data, int link_dev);
bool stm32prog_serial_loop(struct stm32prog_data *data);
bool stm32prog_usb_loop(struct stm32prog_data *data, int dev);
void stm32prog_clean(struct stm32prog_data *data);
#ifdef CONFIG_CMD_STM32PROG_SERIAL
int stm32prog_serial_init(struct stm32prog_data *data, int link_dev);
bool stm32prog_serial_loop(struct stm32prog_data *data);
#else
static inline int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
{
return -ENOSYS;
}
static inline bool stm32prog_serial_loop(struct stm32prog_data *data)
{
return false;
}
#endif
#ifdef CONFIG_CMD_STM32PROG_USB
bool stm32prog_usb_loop(struct stm32prog_data *data, int dev);
#else
static inline bool stm32prog_usb_loop(struct stm32prog_data *data, int dev)
{
return false;
}
#endif
#endif

29
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
View file

@ -187,36 +187,19 @@ static int stm32prog_read(struct stm32prog_data *data, u8 phase, u32 offset,
int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
{
struct udevice *dev = NULL;
int node;
char alias[10];
const char *path;
struct dm_serial_ops *ops;
/* no parity, 8 bits, 1 stop */
u32 serial_config = SERIAL_DEFAULT_CONFIG;
down_serial_dev = NULL;
sprintf(alias, "serial%d", link_dev);
path = fdt_get_alias(gd->fdt_blob, alias);
if (!path) {
log_err("%s alias not found", alias);
return -ENODEV;
}
node = fdt_path_offset(gd->fdt_blob, path);
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node,
&dev)) {
down_serial_dev = dev;
} else if (node > 0 &&
!lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
&dev, false)) {
if (!device_probe(dev))
down_serial_dev = dev;
}
if (!down_serial_dev) {
log_err("%s = %s device not found", alias, path);
if (uclass_get_device_by_seq(UCLASS_SERIAL, link_dev, &dev)) {
log_err("serial %d device not found\n", link_dev);
return -ENODEV;
}
down_serial_dev = dev;
/* force silent console on uart only when used */
if (gd->cur_serial_dev == down_serial_dev)
gd->flags |= GD_FLG_DISABLE_CONSOLE | GD_FLG_SILENT;
@ -226,11 +209,11 @@ int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
ops = serial_get_ops(down_serial_dev);
if (!ops) {
log_err("%s = %s missing ops", alias, path);
log_err("serial %d = %s missing ops\n", link_dev, dev->name);
return -ENODEV;
}
if (!ops->setconfig) {
log_err("%s = %s missing setconfig", alias, path);
log_err("serial %d = %s missing setconfig\n", link_dev, dev->name);
return -ENODEV;
}

28
arch/arm/mach-stm32mp/cpu.c
View file

@ -252,8 +252,10 @@ static void early_enable_caches(void)
if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
return;
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = (unsigned long)&early_tlb;
if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = (unsigned long)&early_tlb;
}
/* enable MMU (default configuration) */
dcache_enable();
@ -285,7 +287,8 @@ int arch_cpu_init(void)
boot_mode = get_bootmode();
if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#if defined(CONFIG_DEBUG_UART) && \
!defined(CONFIG_TFABOOT) && \
@ -485,7 +488,6 @@ static void setup_boot_mode(void)
unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
struct udevice *dev;
int alias;
log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
__func__, boot_ctx, boot_mode, instance, forced_mode);
@ -493,19 +495,23 @@ static void setup_boot_mode(void)
case BOOT_SERIAL_UART:
if (instance > ARRAY_SIZE(serial_addr))
break;
/* serial : search associated alias in devicetree */
/* serial : search associated node in devicetree */
sprintf(cmd, "serial@%x", serial_addr[instance]);
if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
/* restore console on error */
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
gd->flags &= ~(GD_FLG_SILENT |
GD_FLG_DISABLE_CONSOLE);
printf("uart%d = %s not found in device tree!\n",
instance, cmd);
break;
if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
dev_of_offset(dev), &alias))
break;
sprintf(cmd, "%d", alias);
}
sprintf(cmd, "%d", dev_seq(dev));
env_set("boot_device", "serial");
env_set("boot_instance", cmd);
/* restore console on uart when not used */
if (gd->cur_serial_dev != dev) {
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
gd->flags &= ~(GD_FLG_SILENT |
GD_FLG_DISABLE_CONSOLE);
printf("serial boot with console enabled!\n");

8
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -51,14 +51,17 @@ config TARGET_P5040DS
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
select ARCH_MPC8541
select FSL_VIA
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
select FSL_VIA
config TARGET_MPC8555CDS
bool "Support MPC8555CDS"
select ARCH_MPC8555
select FSL_VIA
config TARGET_MPC8568MDS
bool "Support MPC8568MDS"
@ -1409,6 +1412,10 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
config FSL_VIA
bool
source "board/emulation/qemu-ppce500/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
@ -1417,7 +1424,6 @@ source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xrdb/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"

2
arch/powerpc/cpu/mpc85xx/cpu.c
View file

@ -395,7 +395,9 @@ int cpu_mmc_init(struct bd_info *bis)
void print_reginfo(void)
{
print_tlbcam();
#ifdef CONFIG_FSL_LAW
print_laws();
#endif
#if defined(CONFIG_FSL_LBC)
print_lbc_regs();
#endif

2
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
View file

@ -123,7 +123,9 @@ void cpu_init_early_f(void *fdt)
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
#endif
#ifdef CONFIG_FSL_LAW
init_laws();
#endif
/*
* Work Around for IFC Erratum A003399, issue will hit only when execution

2
arch/powerpc/include/asm/arch-mpc85xx/gpio.h
View file

@ -18,7 +18,7 @@
#endif
struct mpc8xxx_gpio_plat {
ulong addr;
phys_addr_t addr;
unsigned long size;
uint ngpios;
};

1
arch/powerpc/include/asm/immap_85xx.h
View file

@ -272,6 +272,7 @@ typedef struct ccsr_gpio {
u32 gpier;
u32 gpimr;
u32 gpicr;
u32 gpibe;
} ccsr_gpio_t;
#endif

15
arch/powerpc/include/asm/io.h
View file

@ -10,7 +10,10 @@
#include <asm/byteorder.h>
#ifdef CONFIG_ADDR_MAP
#include <asm/global_data.h>
#include <addr_map.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#define SIO_CONFIG_RA 0x398
@ -303,20 +306,20 @@ static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
static inline void *phys_to_virt(phys_addr_t paddr)
{
#ifdef CONFIG_ADDR_MAP
return addrmap_phys_to_virt(paddr);
#else
return (void *)((unsigned long)paddr);
if (gd->flags & GD_FLG_RELOC)
return addrmap_phys_to_virt(paddr);
#endif
return (void *)((unsigned long)paddr);
}
#define phys_to_virt phys_to_virt
static inline phys_addr_t virt_to_phys(void * vaddr)
{
#ifdef CONFIG_ADDR_MAP
return addrmap_virt_to_phys(vaddr);
#else
return (phys_addr_t)((unsigned long)vaddr);
if (gd->flags & GD_FLG_RELOC)
return addrmap_virt_to_phys(vaddr);
#endif
return (phys_addr_t)((unsigned long)vaddr);
}
#define virt_to_phys virt_to_phys

24
arch/x86/Kconfig
View file

@ -1001,6 +1001,28 @@ config PCIEX_LENGTH_128MB
config PCIEX_LENGTH_64MB
bool
config INTEL_SOC
bool
help
This is enabled on Intel SoCs that can support various advanced
features such as power management (requiring asm/arch/pm.h), system
agent (asm/arch/systemagent.h) and an I/O map for ACPI
(asm/arch/iomap.h).
This cannot be selected in a defconfig file. It must be enabled by a
'select' in the SoC's Kconfig.
if INTEL_SOC
config INTEL_ACPIGEN
bool "Support ACPI table generation for Intel SoCs"
depends on ACPIGEN
help
This option adds some functions used for programmatic generation of
ACPI tables on Intel SoCs. This provides features for writing CPU
information such as P states and T stages. Also included is a way
to create a GNVS table and set it up.
config INTEL_GMA_ACPI
bool "Generate ACPI table for Intel GMA graphics"
help
@ -1023,4 +1045,6 @@ config INTEL_GMA_SWSMISCI
Select this option for Atom-based platforms which use the SWSMISCI
register (0xe0) rather than the SWSCI register (0xe8).
endif # INTEL_SOC
endmenu

1
arch/x86/cpu/apollolake/Kconfig
View file

@ -9,6 +9,7 @@ config INTEL_APOLLOLAKE
select HAVE_FSP
select ARCH_MISC_INIT
select USE_CAR
select INTEL_SOC
select INTEL_PMC
select TPL_X86_TSC_TIMER_NATIVE
select SPL_PCH_SUPPORT

2
arch/x86/cpu/intel_common/lpc.c
View file

@ -53,7 +53,7 @@ int lpc_common_early_init(struct udevice *dev)
count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),
"intel,gen-dec", (u32 *)values,
sizeof(values) / sizeof(u32));
sizeof(values) / (sizeof(u32)));
if (count < 0)
return -EINVAL;

4
arch/x86/include/asm/intel_gnvs.h
View file

@ -107,6 +107,10 @@ struct __packed acpi_global_nvs {
u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
#endif
};
#ifdef CONFIG_CHROMEOS
check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#else
check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
#endif /* _INTEL_GNVS_H_ */

4
board/beacon/imx8mn/Kconfig
View file

@ -13,6 +13,10 @@ config IMX8MN_FORCE_NOM_SOC
bool "Force to use nominal mode for SOC and ARM"
default n
config IMX8MN_BEACON_2GB_LPDDR
bool "Enable 2GB LPDDR"
default n
source "board/freescale/common/Kconfig"
endif

1
board/beacon/imx8mn/MAINTAINERS
View file

@ -4,3 +4,4 @@ S: Maintained
F: board/beacon/imx8mn/
F: include/configs/imx8mn_beacon.h
F: configs/imx8mn_beacon_defconfig
F: configs/imx8mn_beacon_2g_defconfig

7
board/beacon/imx8mn/Makefile
View file

@ -8,6 +8,9 @@ obj-y += imx8mn_beacon.o
obj-y += ../../freescale/common/
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
ifdef CONFIG_IMX8MN_BEACON_2GB_LPDDR
obj-y += lpddr4_2g_timing.o
else
obj-y += lpddr4_timing.o
endif
endif

1440
board/beacon/imx8mn/lpddr4_2g_timing.c Normal file
View file

File diff suppressed because it is too large Load diff

2
board/freescale/qemu-ppce500/Kconfig → board/emulation/qemu-ppce500/Kconfig
View file

@ -4,7 +4,7 @@ config SYS_BOARD
default "qemu-ppce500"
config SYS_VENDOR
default "freescale"
default "emulation"
config SYS_CONFIG_NAME
default "qemu-ppce500"

7
board/emulation/qemu-ppce500/MAINTAINERS Normal file
View file

@ -0,0 +1,7 @@
QEMU-PPCE500 BOARD
M: Alexander Graf <agraf@csgraf.de>
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
F: board/emulation/qemu-ppce500/
F: include/configs/qemu-ppce500.h
F: configs/qemu-ppce500_defconfig

0
board/freescale/qemu-ppce500/Makefile → board/emulation/qemu-ppce500/Makefile
View file

176
board/freescale/qemu-ppce500/qemu-ppce500.c → board/emulation/qemu-ppce500/qemu-ppce500.c
View file

@ -1,11 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
* Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <dm.h>
#include <env.h>
#include <init.h>
#include <log.h>
@ -23,12 +25,17 @@
#include <fdtdec.h>
#include <errno.h>
#include <malloc.h>
#include <virtio_types.h>
#include <virtio.h>
DECLARE_GLOBAL_DATA_PTR;
static void *get_fdt_virt(void)
{
return (void *)CONFIG_SYS_TMPVIRT;
if (gd->flags & GD_FLG_RELOC)
return (void *)gd->fdt_blob;
else
return (void *)CONFIG_SYS_TMPVIRT;
}
static uint64_t get_fdt_phys(void)
@ -74,33 +81,14 @@ uint64_t get_phys_ccsrbar_addr_early(void)
return r;
}
int board_early_init_f(void)
{
return 0;
}
int checkboard(void)
{
return 0;
}
static int pci_map_region(void *fdt, int pci_node, int range_id,
phys_size_t *ppaddr, pci_addr_t *pvaddr,
pci_size_t *psize, ulong *pmap_addr)
static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr)
{
uint64_t addr;
uint64_t size;
ulong map_addr;
int r;
r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
if (r)
return r;
if (ppaddr)
*ppaddr = addr;
if (psize)
*psize = size;
if (!pmap_addr)
return 0;
@ -115,90 +103,52 @@ static int pci_map_region(void *fdt, int pci_node, int range_id,
return -1;
/* Map virtual memory for range */
assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO));
*pmap_addr = map_addr + size;
if (pvaddr)
*pvaddr = map_addr;
return 0;
}
void pci_init_board(void)
int misc_init_r(void)
{
struct pci_controller *pci_hoses;
void *fdt = get_fdt_virt();
int pci_node = -1;
int pci_num = 0;
int pci_count = 0;
struct udevice *dev;
struct pci_region *io;
struct pci_region *mem;
struct pci_region *pre;
ulong map_addr;
int ret;
puts("\n");
/* Ensure PCI is probed */
uclass_first_device(UCLASS_PCI, &dev);
pci_get_regions(dev, &io, &mem, &pre);
/* Start MMIO and PIO range maps above RAM */
map_addr = CONFIG_SYS_PCI_MAP_START;
/* Count and allocate PCI buses */
pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
"device_type", "pci", 4);
while (pci_node != -FDT_ERR_NOTFOUND) {
pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
"device_type", "pci", 4);
pci_count++;
}
/* Map MMIO range */
ret = pci_map_region(mem->phys_start, mem->size, &map_addr);
if (ret)
return ret;
if (pci_count) {
pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
} else {
printf("PCI: disabled\n\n");
return;
}
/* Map PIO range */
ret = pci_map_region(io->phys_start, io->size, &map_addr);
if (ret)
return ret;
/* Spawn PCI buses based on device tree */
pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
"device_type", "pci", 4);
while (pci_node != -FDT_ERR_NOTFOUND) {
struct fsl_pci_info pci_info = { };
const fdt32_t *reg;
int r;
/*
* Make sure virtio bus is enumerated so that peripherals
* on the virtio bus can be discovered by their drivers.
*/
virtio_init();
reg = fdt_getprop(fdt, pci_node, "reg", NULL);
pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
/*
* U-Boot is relocated to RAM already, let's delete the temporary FDT
* virtual-physical mapping that was used in the pre-relocation phase.
*/
disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1));
/* Map MMIO range */
r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
&pci_info.mem_size, &map_addr);
if (r)
break;
/* Map PIO range */
r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
&pci_info.io_size, &map_addr);
if (r)
break;
/*
* The PCI framework finds virtual addresses for the buses
* through our address map, so tell it the physical addresses.
*/
pci_info.mem_bus = pci_info.mem_phys;
pci_info.io_bus = pci_info.io_phys;
/* Instantiate */
pci_info.pci_num = pci_num + 1;
fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
printf("PCI: base address %lx\n", pci_info.regs);
fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
/* Jump to next PCI node */
pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
"device_type", "pci", 4);
pci_num++;
}
puts("\n");
return 0;
}
int last_stage_init(void)
@ -219,9 +169,6 @@ int last_stage_init(void)
if (prop && (len >= 8))
env_set_hex("qemu_kernel_addr", *prop);
/* Give the user a variable for the host fdt */
env_set_hex("fdt_addr_r", (ulong)fdt);
return 0;
}
@ -241,30 +188,6 @@ static uint64_t get_linear_ram_size(void)
panic("Couldn't determine RAM size");
}
int board_eth_init(struct bd_info *bis)
{
return pci_eth_init(bis);
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
FT_FSL_PCI_SETUP;
return 0;
}
#endif
void print_laws(void)
{
/* We don't emulate LAWs yet */
}
phys_size_t fixed_sdram(void)
{
return get_linear_ram_size();
}
phys_size_t fsl_ddr_sdram_size(void)
{
return get_linear_ram_size();
@ -303,11 +226,6 @@ void init_tlbs(void)
1024 * 1024, TLB_MAP_RAM));
}
void init_laws(void)
{
/* We don't emulate LAWs yet */
}
static uint32_t get_cpu_freq(void)
{
void *fdt = get_fdt_virt();
@ -380,3 +298,19 @@ u32 cpu_mask(void)
{
return (1 << cpu_numcores()) - 1;
}
/**
* Return the virtual address of FDT that was passed by QEMU
*
* @return virtual address of FDT received from QEMU in r3 register
*/
void *board_fdt_blob_setup(void)
{
return get_fdt_virt();
}
/* See CONFIG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */
int get_serial_clock(void)
{
return get_bus_freq(0);
}

27
board/freescale/common/Kconfig
View file

@ -21,18 +21,37 @@ config CMD_ESBC_VALIDATE
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
config VID
depends on DM_I2C
bool "Enable Freescale VID"
help
This option enables setting core voltage based on individual
values saved in SoC fuses.
config VOL_MONITOR_LTC3882_READ
depends on VID
bool "Enable the LTC3882 voltage monitor read"
default n
help
This option enables LTC3882 voltage monitor read
functionality. It is used by common VID driver.
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
depends on VID
bool "Enable the LTC3882 voltage monitor set"
default n
help
This option enables LTC3882 voltage monitor set
functionality. It is used by common VID driver.
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_READ
depends on VID
bool "Enable the ISL68233 voltage monitor read"
help
This option enables ISL68233 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_SET
depends on VID
bool "Enable the ISL68233 voltage monitor set"
help
This option enables ISL68233 voltage monitor set
functionality. It is used by the common VID driver.

842
board/freescale/common/vid.c
View file

File diff suppressed because it is too large Load diff

11
board/freescale/common/vid.h
View file

@ -7,16 +7,17 @@
#ifndef __VID_H_
#define __VID_H_
/* IR36021 command codes */
#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A
#define IR36021_LOOP1_VOUT_OFFSET 0x9A
#define IR36021_MFR_ID_OFFSET 0x92
#define IR36021_MFR_ID 0x43
#define IR36021_INTEL_MODE_OOFSET 0x14
#define IR36021_INTEL_MODE_OFFSET 0x14
#define IR36021_MODE_MASK 0x20
#define IR36021_INTEL_MODE 0x00
#define IR36021_AMD_MODE 0x20
/* step the IR regulator in 5mV increments */
/* Step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
#define IR_VDD_STEP_UP 5
@ -50,15 +51,16 @@
#define VDD_MV_MAX 925
#endif
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
defined(CONFIG_TARGET_LX2160ARDB)
/* PM Bus commands code for LTC3882*/
#define PWM_CHANNEL0 0x0
#define PMBUS_CMD_PAGE 0x0
#define PMBUS_CMD_READ_VOUT 0x8B
#define PMBUS_CMD_VOUT_MODE 0x20
#define PMBUS_CMD_VOUT_COMMAND 0x21
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
defined(CONFIG_TARGET_LX2160ARDB)
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
@ -68,5 +70,6 @@ defined(CONFIG_TARGET_LX2160ARDB)
#endif
int adjust_vdd(ulong vdd_override);
u16 soc_get_fuse_vid(int vid_index);
#endif /* __VID_H_ */

6
board/freescale/corenet_ds/MAINTAINERS
View file

@ -19,9 +19,3 @@ F: configs/P5040DS_NAND_defconfig
F: configs/P5040DS_SDCARD_defconfig
F: configs/P5040DS_SPIFLASH_defconfig
F: configs/P5040DS_SECURE_BOOT_defconfig
CORENET_DS_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
F: configs/P5040DS_NAND_SECURE_BOOT_defconfig

6
board/freescale/ls1012afrdm/MAINTAINERS
View file

@ -1,5 +1,4 @@
LS1012AFRDM BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1012afrdm/
@ -10,12 +9,9 @@ F: configs/ls1012afrwy_tfa_defconfig
F: configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
LS1012AFRWY BOARD
M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012afrwy/
F: include/configs/ls1012afrwy.h
F: configs/ls1012afrwy_qspi_defconfig
M: Vinitha V Pillai <vinitha.pillai@nxp.com>
S: Maintained
F: configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig

2
board/freescale/ls1012aqds/MAINTAINERS
View file

@ -1,6 +1,6 @@
LS1012AQDS BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012aqds/
F: include/configs/ls1012aqds.h

7
board/freescale/ls1012ardb/MAINTAINERS
View file

@ -1,6 +1,6 @@
LS1012ARDB BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012ardb/
F: include/configs/ls1012ardb.h
@ -8,13 +8,10 @@ F: configs/ls1012ardb_qspi_defconfig
F: configs/ls1012ardb_tfa_defconfig
F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
F: configs/ls1012a2g5rdb_tfa_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
LS1012A2G5RDB BOARD
M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012ardb/
F: include/configs/ls1012a2g5rdb.h

2
board/freescale/ls1021aiot/MAINTAINERS
View file

@ -1,5 +1,5 @@
LS1021AIOT BOARD
M: Feng Li <feng.li_2@nxp.com>
M: Alison Wang <alison.wang@nxp.com>
S: Maintained
F: board/freescale/ls1021aiot/
F: include/configs/ls1021aiot.h

3
board/freescale/ls1021atwr/MAINTAINERS
View file

@ -9,7 +9,4 @@ F: configs/ls1021atwr_nor_lpuart_defconfig
F: configs/ls1021atwr_sdcard_ifc_defconfig
F: configs/ls1021atwr_sdcard_qspi_defconfig
F: configs/ls1021atwr_qspi_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig

4
board/freescale/ls1028a/MAINTAINERS
View file

@ -1,6 +1,4 @@
LS1028AQDS BOARD
M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
M: Rai Harninder <harninder.rai@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Tang Yuantian <andy.tang@nxp.com>
S: Maintained
@ -11,8 +9,6 @@ F: configs/ls1028aqds_tfa_defconfig
F: configs/ls1028aqds_tfa_lpuart_defconfig
LS1028ARDB BOARD
M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
M: Rai Harninder <harninder.rai@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Tang Yuantian <andy.tang@nxp.com>
S: Maintained

4
board/freescale/ls1043ardb/MAINTAINERS
View file

@ -10,10 +10,6 @@ F: configs/ls1043ardb_nand_defconfig
F: configs/ls1043ardb_sdcard_defconfig
F: configs/ls1043ardb_tfa_defconfig
F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
LS1043A_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/ls1043ardb_SECURE_BOOT_defconfig
F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig

3
board/freescale/ls1046aqds/MAINTAINERS
View file

@ -12,7 +12,4 @@ F: configs/ls1046aqds_qspi_defconfig
F: configs/ls1046aqds_lpuart_defconfig
F: configs/ls1046aqds_tfa_defconfig
F: configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1046aqds_SECURE_BOOT_defconfig

7
board/freescale/ls1046ardb/MAINTAINERS
View file

@ -11,13 +11,6 @@ F: configs/ls1046ardb_sdcard_defconfig
F: configs/ls1046ardb_emmc_defconfig
F: configs/ls1046ardb_tfa_defconfig
F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
LS1046A_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/ls1046ardb_SECURE_BOOT_defconfig
F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained
F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig

6
board/freescale/ls1088a/MAINTAINERS
View file

@ -1,5 +1,4 @@
LS1088ARDB BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Ashish Kumar <Ashish.Kumar@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
@ -11,7 +10,6 @@ F: configs/ls1088ardb_tfa_defconfig
F: configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
LS1088AQDS BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Ashish Kumar <Ashish.Kumar@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
@ -25,17 +23,15 @@ F: configs/ls1088aqds_tfa_defconfig
LS1088AQDS_QSPI_SECURE_BOOT BOARD
M: Udit Agarwal <udit.agarwal@nxp.com>
M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
S: Maintained
F: configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
LS1088ARDB_QSPI_SECURE_BOOT BOARD
M: Udit Agarwal <udit.agarwal@nxp.com>
M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
S: Maintained
F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
LS1088ARDB_SD_SECURE_BOOT BOARD
M: Sumit Garg <sumit.garg@nxp.com>
M: Udit Agarwal <udit.agarwal@nxp.com>
S: Maintained
F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig

40
board/freescale/ls1088a/ls1088a.c
View file

@ -186,6 +186,46 @@ int init_func_vid(void)
return 0;
}
u16 soc_get_fuse_vid(int vid_index)
{
static const u16 vdd[32] = {
10250,
9875,
9750,
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
9000,
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
10000, /* 1.0000V */
10125,
10250,
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
};
return vdd[vid_index];
};
#endif
int is_pb_board(void)

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