Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.
There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
fetches initial device boot image from FMC chip select(CS) 0.
- SPI1: Play the role of a SPI Master controller. Or, there is a
dedicated path for HOST(X86) to access its BIOS flash mounted
under BMC. spi-aspeed-smc.c implements the control sequence when
SPI1 is a SPI master.
- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
mounted under it are for pure storage purpose.
ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
13h is used to fetch boot image from SPI flash.
- AST2500: Only 03h command can be used after power on
or reset.
- AST2600: If FMC04[6:4] is set, 13h command is used,
otherwise, 03h command.
The address length is decided by FMC04[2:0].
- Command mode: SPI controller can send command and address
automatically when CPU read/write the related remapped
or decoded address area. The command used by this mode
can be configured by FMC10/14/18[23:16]. Also, the
address length is decided by FMC04[2:0]. This mode will
be implemented in the following patch series.
- User mode: It is a traditional and pure SPI operation, where
SPI transmission is controlled by CPU. It is the main
mode in this patch.
Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.
This patch only implements user mode initially. Command read/write
mode will be implemented in the following patches.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group.
On AST2500 EVB, FWSPICS1 can be supported by default.
An extra jumper, J45, should be configured before
enabling SPI1CS1.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = <&scu ASPEED_CLK_AHB>".
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
cmd:
- bdinfo - guard LMB code to run only when LMB is enabled
timer:
- convert arm twd timer to DM
power-domain:
- Skip loading config object for Versal
xilinx:
- Fix logic when dfu_alt_info is generated
- Define only mmc devnum not partition
- Add xlnx prefix to GEM compatible string
- Add missing tca6416 to zynqmp SC - vck190
- Add env redund offset
- Enable CMD_GREPENV/SETEXPR by default
- Move board_get_usable_ram_top() to common location
- Add support for SOC detection
net/gem:
- Check rate before setting it up
microblaze:
- drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
- Show cache size in bdinfo
spi:
- cadence_qspi: driver updates
- zynqmp_gqspi: driver updates
- zynqmp_gqspi: Add tap delays for Versal
zynq:
- Enable mkeficapsule compilation
- Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info
- Align bss and end of u-boot image to 64bits
- Align qspi node name with Linux kernel
- DT: List OCM memory
zynqmp:
- Fix AES cache handling with a user provided key
- SOM: Add mtd partition for secure OS storage area
- Add ref_clk property for REFCLKPER calculation
- Fix mdio bus description for vck190-sc
xilinx-mini:
- Remove unneeded configs
- Disable LMB
versal:
- Enable i2c mux pca954x by default
- Define CONFIG_CQSPI_REF_CLK
- Enable power domain driver
- Enable zynqmp_gqspi driver
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Merge tag 'xilinx-for-v2023.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1
cmd:
- bdinfo - guard LMB code to run only when LMB is enabled
timer:
- convert arm twd timer to DM
power-domain:
- Skip loading config object for Versal
xilinx:
- Fix logic when dfu_alt_info is generated
- Define only mmc devnum not partition
- Add xlnx prefix to GEM compatible string
- Add missing tca6416 to zynqmp SC - vck190
- Add env redund offset
- Enable CMD_GREPENV/SETEXPR by default
- Move board_get_usable_ram_top() to common location
- Add support for SOC detection
net/gem:
- Check rate before setting it up
microblaze:
- drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
- Show cache size in bdinfo
spi:
- cadence_qspi: driver updates
- zynqmp_gqspi: driver updates
- zynqmp_gqspi: Add tap delays for Versal
zynq:
- Enable mkeficapsule compilation
- Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info
- Align bss and end of u-boot image to 64bits
- Align qspi node name with Linux kernel
- DT: List OCM memory
zynqmp:
- Fix AES cache handling with a user provided key
- SOM: Add mtd partition for secure OS storage area
- Add ref_clk property for REFCLKPER calculation
- Fix mdio bus description for vck190-sc
xilinx-mini:
- Remove unneeded configs
- Disable LMB
versal:
- Enable i2c mux pca954x by default
- Define CONFIG_CQSPI_REF_CLK
- Enable power domain driver
- Enable zynqmp_gqspi driver
To quote the author:
This series makes a further attempt to get closer to having all tests
run in parallel. It introduces a new 'make pcheck' option which runs
tests in parallel, skipping those that are not compatible.
A number of fixes are included for existing tests. The vboot test is
updated to only run a single scenario in 'quick' mode.
This makes use of pytest's parallel-testing features. The resulting
times (including incremental building with LTO) on a 16-core machine are
as follows:
make pcheck - 1 minute 6 seconds
make qcheck - 3 minutes
make check - 5 minutes 15 seconds
Note that this is not a fair comparison, since 'make pcheck' omits a
number of tests, even more than 'make qcheck'.
Code supports board detection based on information available in EEPROM in
legacy or FRU format. But this is not enough for emulation and simulation
systems which are lacking these identification EEPROMs. But SOC itself has
normally registers for SOC identification. Based on them it is possible to
compose detected name. That's why prepare infrastructure in common location
for SOC platform detection which is called before board platform detection.
SOC platform detection shouldn't detect real silicon and should fallback to
current existing mechanism to identify boards based on EEPROMs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/329a8da338927b082e26a958bf69bb18af072420.1662460837.git.michal.simek@amd.com
Few lines are extented to next line though they can fit in 80 character
limit, align them to single line. No functional change.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-6-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
As the flash sizes are increasing day by day, QSPI can have devices of
size > 512MB. In qspi driver we are trying to read all the data at once
using DMA.
The DMA descriptor destination size is only 29bits long.
QSPIDMA_DST_SIZE 0xFF0F0804
BITS: 1:0 Reserved to keep word alignment
BITS: 28:2 Number of 4-byte words the DMA will transfer
BITS: 31:29 Reserved: Returns 0 when read, writes ignored
So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes.
Anything above will overflow this register and will ignore higher bits
above 29 bits.
Change the DMA functionality if the requested size is greater than or
equal to 512MB to read 256MB chunks.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add support for io-mode transfers. This is necessary for UBIFS to work
properly with spi-nor devices. The driver will work in IO mode when
"has-io-mode" is passed from device tree instead of DMA.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
GQSPI driver is using it but this function is never called for Versal
because it is removed by linker. But function should be declared to avoid
this build warning:
drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay':
drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function
'zynqmp_mmio_write' [-Wimplicit-function-declaration]
378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
As per driver model we should enumerate plat structure only in
of_to_plat() and should be used only in probe(). Copy required
plat structure info into priv structure in probe() and use priv
structure across the driver. So replace plat with priv structure across
the driver.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
In cadence_spi_read_id we are using STIG mode to read flash id's.
Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data
bus width properly before cadence_qspi_apb_command_read().
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset
the flash device. Looks like there is a mistake in previous series of
patches where it is defined as cadence_spi_versal_flash_reset() but
called as cadence_qspi_versal_flash_reset. Since there is a weak function
defined with the same name this issue was not caught.
Fix the issue by renaming cadence_spi_versal_flash_reset as
cadence_qspi_versal_flash_reset().
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add bdinfo_print_size() helper to display size variables (such as cache
sizes) in bdinfo format. The size is printed as "xxx Bytes", "xxx KiB",
"xxx MiB", "xxx GiB", etc as needed;
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Check snprintf() return value for errors.
Make microblaze_cpu_get_desc() directly return snprintf() error code if
ret < 0. Otherwise, if the return value is greater than or equal to size,
the resulting string is truncated, so return -ENOSPC.
Fixes: 816226d27e ("cpu: add CPU driver for microblaze")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
These macros are not used anymore in microblaze code since commit
f113d7d303 ("Convert CONFIG_SPL_STACK to Kconfig"), so remove them.
Fixes: f113d7d303 ("Convert CONFIG_SPL_STACK to Kconfig")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The commit ce39ee28ec ("zynqmp: Do not place u-boot to reserved memory
location") adds functionality for ZynqMP to read reserved memory node and
do not place U-Boot to reserved location. This functionality is generic
across all Xilinx SOCs that's why move it to common location to be used by
all Xilinx SOCs.
On zynq platform this is also fixing issue where U-Boot was placed to
locating which was reserved already which ends up with error message
"ERROR: reserving fdt memory region failed (addr=30000000 size=10000000
flags=4)" which is shown when bdinfo is called.
Tested on vck190, zcu102, zc706 and kc705 to cover all platforms.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com
ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env
variables is overwriting data at 0 offset, which is wrong. So add default
redund env offset for Zynq, ZynqMP, Versal and microblaze platforms.
Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE).
In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead
of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000.
Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of
ENV_IS_IN_SPI_FLASH config.
Below table specifies platform specific env and env redund offsets.
PLAT ENV_OFFSET ENV_OFFSET_REDUND
---- ---------- -----------------
ZYNQ 0xE0000 0xE40000
ZYNQMP 0x1E00000 0x1E80000
VERSAL 0x7F40000 0x7F00000
MICROBLAZE 0x1080000 0x10C0000
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ
calculation. This property configure correct value for SOF/ITP counter
and period of ref_clk.
This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores.
Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
Update MTD partitions of Kria device trees to allocate 128KB of QSPI
memory for secure OS. Increased "SHA256" partition size & changed
starting address of "User" partition to accommodate the new partition
"Secure OS Storage"
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9cc64b8c731d11439de73d0af54c65080068f00b.1661242681.git.michal.simek@amd.com
The commit 53b406369e ("DFU: Check the number of arguments and argument
string strictly") added strict control over string that 0:1 partition
definition is not valid anymore that's why use only device number without
partition ID. Device is specified by 2nd parameter and partition by 3rd.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/840eca944f4f2abeeb63b5d724f9ba5fe9a9213b.1660055571.git.michal.simek@amd.com
Zynq can use efi capsule infrastructure that's why enable it by default.
For capsule generation for zynq you can use:
pushd spl
../tools/mkeficapsule -g "1ba29a15-9969-40aa-b424-e86121618664" boot.bin \
--index 1 ../capsule1.bin
popd
./tools/mkeficapsule -g "1a5178f0-87d3-4f36-ac63-3b31a23be305" u-boot.img \
--index 2 capsule2.bin
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a8194ecfa7932f2d8ada5ee508b2a026c782f15e.1660055571.git.michal.simek@amd.com
With commit 55b3ba4c2b ("spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK
to Kconfig") CONFIG_CQSPI_REF_CLK is moved to Kconfig.
The static value via Kconfig is a fallback option in case of clock
framework is not enabled or fails for some reason.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe7c38a19e878c307d5b75311bbfd8cf6c1f601e.1659691195.git.michal.simek@amd.com
Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") moved code from file cpu.c to lowlevel.c,
which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to
SOC_REGS_PHY_BASE.
But the steps describing how to do it correctly were documented only in
older U-Boot versions and commit cefd764222 ("arm: mvebu: Fix internal
register config on A38x") probably unintentionally removed important
details about MMU from code comments around.
Commit 5bb2c550b1 ("arm: mvebu: Move internal registers in
arch_very_early_init() function") implemented code movement according to
(now incomplete) comments which resulted in semi-broken code.
The result is that I-cache is currently disabled for all Armada 38x boards
and maybe there are some other (unreported / undetected) issues.
Reimplement it correctly. First flush all caches, then disable MMU and L2
cache and then move Marvell internal registers. There is no need to
explicitly disable I-cache.
After this change lzmadec command with lzma image of 0x7000000 bytes is
doing decompression just 5 seconds. Before this change it was 30 seconds.
To make lowlevel.S code more readable, extend asm/pl310.h header file to be
compatible with assembler and use macros from this file.
Fixes: 5bb2c550b1 ("arm: mvebu: Move internal registers in arch_very_early_init() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
For some unknown reason when L2 cache is disabled on Armada 385 then loadb,
loadx and loady commands do not work with higher baudrates than 115200
(they just abort transfer) and lzmadec command with lzma image of size
0x7000000 (maybe even smaller, we tested this one) is doing decompression
for more than 2 minutes. After enabling L2 cache decompression takes only
30s and loadb, loadx and loady are stable and working fine.
git bisect identified problematic commit 3308933d2f ("arm: mvebu: Avoid
reading MVEBU_REG_PCIE_DEVID register too many times"). Before this commit
above issues were not present.
But investigation showed that above issue was possible to reproduce also by
reverting that commit and forcing compiler to do inline optimization of
mvebu_soc_family() function. Which seems that the root of this issue is in
caches and position of instruction of segments. So currently it is unknown
what is or was broken, but code movement, code inlining or other compiler
optimization triggered it.
Commit 3e5ce7ceeb ("arm: mvebu: Enable L2 cache on Armada XP") mentioned
that enabling L2 cache on Armada XP improved performance and that Armada
38x has L2 disabled (which is default state) and if needed it has to be
enabled in separate patch. As enabling L2 cache also improve performance
on Armada 38x, enable it.
Note that Aurora cache in no outer mode is available only on Armada XP,
hence it is not touched for Armada 38x code.
Fixes: 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Reported-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Replace magic constant 1 when disabling MMU by macro CR_M from include
header file asm/system.h.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit c86d53fd88 ("arm: mvebu: Don't disable cache at startup on Armada
XP at all") introduced branch for non-AXP code which was guarded by A38X
condition. Fix this issue by checking for AXP platform, not by A38X.
Fixes: c86d53fd88 ("arm: mvebu: Don't disable cache at startup on Armada XP at all")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Commit 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID
register too many times") broke support for caches on all Armada SoCs.
Before that commit there was code:
if (mvebu_soc_family() != MVEBU_SOC_A375) {
dcache_enable();
}
And after that commit there is code:
if (IS_ENABLED(CONFIG_ARMADA_375)) {
dcache_enable();
}
Comment above this code says that d-cache should be disabled on Armada 375.
But new code inverted logic and broke Armada 375 and slowed down all other
Armada SoCs (including A38x).
Fix this issue by changing logic to:
if (!IS_ENABLED(CONFIG_ARMADA_375)) {
dcache_enable();
}
Which matches behavior prior that commit.
Fixes: 3308933d2f ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Turris Omnia has two serial ports. Both are already specified in device
tree file. But U-Boot by default does not allow to use more than one serial
port unless CONFIG_SERIAL_PROBE_ALL is not enabled.
After enabling CONFIG_SERIAL_PROBE_ALL, U-Boot see also second serial port
(but is inactive by default):
=> coninfo
List of available devices:
serial@12000 00000007 IO stdin stdout stderr
serial@12100 00000007 IO
To allow simultaneously to use more input / output devices it is needed to
enable CONFIG_CONSOLE_MUX option.
With CONFIG_CONSOLE_MUX it is possible to call:
=> setenv stdout 'serial@12000,serial@12100'
And U-Boot output is then visible on both serial ports.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
TCGETS2 is defined in header file asm/ioctls.h provided by linux kernel.
On glib systems it is automatically included by some other glibc include
header file and therefore TCGETS2 is present in termios_linux.h when
linux kernel provides it.
On non-glibc systems (e.g. musl) asm/ioctls.h is not automatically included
which results in the strange error that BOTHER is supported, TCGETS2 not
defined and struct termios does not provide c_ispeed member.
tools/kwboot.c: In function 'kwboot_tty_change_baudrate':
tools/kwboot.c:662:6: error: 'struct termios' has no member named 'c_ospeed'
662 | tio.c_ospeed = tio.c_ispeed = baudrate;
| ^
Fix this issue by explicitly including asm/ioctls.h file which provides
TCGETS2 macro (if supported on selected architecture) to not depending on
glibc auto-include behavior and because termios_linux.h requires it.
With this change it is possible compile kwboot with musl libc.
Reported-by: Michal Vasilek <michal.vasilek@nic.cz>
Signed-off-by: Pali Rohár <pali@kernel.org>
$fdt_addr is mandatory for systems which provides DTB in HW (e.g. ROM) and
wishes to pass that DTB to Linux.
Turris Mox contains DTB binary in SPI NOR memory at "dtb" partition which
starts at offset 0x7f0000 and is 0x10000 bytes long.
Armada 3700 CPU does not allow mapping SPI NOR memory into physical address
space like on other architectures and therefore set $fdt_addr variable to
memory range in RAM and loads this DTB binary from SPI NOR in misc_init_r()
function.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
